LTC1657L

Parallel 16-Bit Rail-to-Rail

Micropower DAC

April 2000

16-Bit Monotonic Over Temperature

3V Single Supply Operation

Deglitched Rail-to-Rail Voltage Output: 8nV ˇ s

: 650

A Typ

Maximum DNL Error:

1LSB

Settling Time: 20

s to

1LSB

Internal or External Reference

Internal Power-On Reset to 0V

Asynchronous CLR Pin

Output Buffer Configurable for Gain of 1 or 2

Parallel 16-Bit or 2-Byte Double Buffered Interface

Narrow 28-Lead SSOP Package

5V Version Available (LTC1657)

The LTC

1657L is a complete single supply, rail-to-rail

voltage output, 16-bit digital-to-analog converter (DAC) in
a 28-pin SSOP or PDIP package. It includes a rail-to-rail
output buffer amplifier, an internal 1.25V reference and a
double buffered parallel digital interface.

The LTC1657L operates from a 2.7V to 5.5V supply. It has
a separate reference input pin that can be driven by an
external reference. The full-scale output can be 1 or 2
times the reference voltage depending on how the X1/X2
pin is connected.

The LTC1657L is similar to Linear Technology Corporation's
LTC1450 12-bit V

OUT

DAC family allowing an easy up-

grade path. It is the only buffered 16-bit parallel DAC in a
28-lead SSOP package and includes an onboard reference
for stand alone performance.

FEATURES

DESCRIPTIO

, LTC and LT are registered trademarks of Linear Technology Corporation.

Instrumentation

Industrial Process Control

Automatic Test Equipment

Communication Test Equipment

APPLICATIO

Differential Nonlinearity

vs Input Code

CODE

1.0

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

1.0

DNL ERROR (LSB)

16484

32768

1657 TA02

49152

65535

Final Electrical Specifications

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

BLOCK DIAGRA

REFLO

GND

0V TO
2.5V

2.7V TO 5.5V

16-BIT

DAC

REFHI

REFOUT

X1/X2

1657 TA01

OUT

D15 (MSB)

DATA IN FROM

MICROPROCESSOR

DATA BUS

FROM

MICROPROCESSOR

DECODE LOGIC

FROM

SYSTEM RESET

D0 (LSB)

REFERENCE

1.25V

16-BIT

DAC

POWER-ON

RESET

LDAC

CLR

CSMSB

CSLSB

LSB

8-BIT

INPUT

MSB

8-BIT

INPUT

LTC1657L

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I

FOR

ATIO

(Note 1)

to GND .............................................. 0.5V to 7.5V

TTL Input Voltage,

REFHI, REFLO, X1/X2 .......................... 0.5V to 7.5V

OUT

, REFOUT ............................ 0.5V to (V

+ 0.5V)

Operating Temperature Range

LTC1657LC ............................................. 0

C to 70

LTC1657LI ......................................... 40

C to 85

Maximum Junction Temperature .......................... 125

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec)................. 300

ORDER PART

NUMBER

Consult factory for Military grade parts.

JMAX

= 125

= 95

C/ W (G)

JMAX

= 125

= 58

C/ W (N)

LTC1657LCGN
LTC1657LCN
LTC1657LIGN
LTC1657LIN

TOP VIEW

GN PACKAGE

28-LEAD PLASTIC SSOP

N PACKAGE

28-LEAD PDIP

CSLSB

CSMSB

(LSB) D0

D10

LDAC

CLR

X1/X2

OUT

REFOUT

REFHI

REFLO

GND

D15 (MSB)

D14

D13

D12

D11

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 2.7V to 5.5V, V

OUT

unloaded, REFOUT tied to REFHI,

REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DAC (Note 2)

Resolution

Bits

Monotonicity

Bits

DNL

Differential Nonlinearity

Guaranteed Monotonic (Note 3)

0.5

1.0

LSB

INL

Integral Nonlinearity

(Note 3)

LSB

ZSE

Zero Scale Error

Offset Error

Measured at Code 200

0.3

Offset Error Tempco

Gain Error

LSB

Gain Error Drift

ppm/

Power Supply

Positive Supply Voltage

For Specified Performance

2.7

5.5

Supply Current

2.7V

5.5V (Note 4)

650

1200

Op Amp DC Performance

Short-Circuit Current Low

OUT

Shorted to GND

120

Short-Circuit Current High

OUT

Shorted to V

140

Output Impedance to GND

Input Code = 0

120

275

Output Line Regulation

Input Code = 65535, V

= 2.7V to 5.5V

mV/V

LTC1657L

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 2.7V to 5.5V, V

OUT

unloaded, REFOUT tied to REFHI,

REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: External reference REFHI = 1.3V, V

= 3V

Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale).
See Applications Information.

Note 4: Digital inputs at 0V or V

Note 5: DAC switched between all 1s all 0s, slew rate is measured from
0.8V to 2V. V

=3V.

Note 6: Guaranteed by design. Not subject to test.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AC Performance

Voltage Output Slew Rate

(Note 5)

0.3

0.7

Voltage Output Settling Time

(Note 5) to 0.0015% (16-Bit Settling Time)

(Note 5) to 0.012% (13-Bit Settling Time)

Digital Feedthrough

0.3

nVˇs

Midscale Glitch Impulse

DAC Switch Between 8000

and 7FFF

nVˇs

Output Voltage Noise

At 1kHz

200

nV/

Spectral Density

Digital I/O (V

= 3V)

Digital Input High Voltage

2.0

Digital Input Low Voltage

0.6

LEAK

Digital Input Leakage

= GND to V

Digital Input Capacitance

(Note 6)

Switching Characteristics (V

= 3V)

CS (MSB or LSB) Pulse Width

WR Pulse Width

CWS

CS to WR Setup

CWH

CS to WR Hold

DWS

Data Valid to WR Setup

DWH

Data Valid to WR Hold

LDAC

LDAC Pulse Width

CLR

CLR Pulse Width

Reference Output (REFOUT)

Reference Output Voltage

1.24

1.25

1.26

Reference Output

ppm/

Temperature Coefficient

Reference Line Regulation

= 2.7V to 5.5V

mV/V

Reference Load Regulation

Measured at I

OUT

= 100

mV/A

Short-Circuit Current

REFOUT Shorted to GND

100

Reference Input

REFHI, REFLO Input Range

(Note 6) See Applications Information

X1/X2 Tied to V

OUT

1.5

X1/X2 Tied to GND

REFHI Input Resistance

LTC1657L

WR (Pin 1): Write Input (Active Low). Used with CSMSB
and/or CSLSB to control the input registers. While WR and
CSMSB and/or CSLSB are held low, data writes into the
input register.

CSLSB (Pin 2): Chip Select Least Significant Byte (Active
Low). Used with WR to control the LSB 8-bit input regis-
ters. While WR and CSLSB are held low, the LSB byte
writes into the LSB input register. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 16-bit bus.

CSMSB (Pin 3): Chip Select Most Significant Byte (Active
Low). Used with WR to control the MSB 8-bit input
registers. While WR and CSMSB are held low, the MSB
byte writes into the MSB input register. Can be connected
to CSLSB for simultaneous loading of both sets of input
latches on a 16-bit bus.

D0 to D7 (Pins 4 to 11): Input data for the Least Significant
Byte. Written into LSB input register when WR = 0 and
CSLSB = 0.

D8 to D15 (Pins 12 to 19): Input data for the Most Signifi-
cant Byte. Written into MSB input register when WR = 0
and CSMSB = 0.

GND (Pin 20): Ground.

REFLO (Pin 21): Lower input terminal of the DAC's inter-
nal resistor ladder. Typically connected to Analog Ground.
An input code of (0000)

will connect the positive input of

CTIO

the output buffer to this end of the ladder. Can be used to
offset the zero scale above ground.

REFHI (Pin 22): Upper input terminal of the DAC's internal
resistor ladder. Typically connected to REFOUT. An input
code of (FFFF)

will connect the positive input of the

output buffer to 1LSB below this voltage.

REFOUT (Pin 23): Output of the internal 1.25V reference.
Typically connected to REFHI to drive internal DAC resistor
ladder.

(Pin 24): Positive Power Supply Input. 2.7V

5.5V. Requires a 0.1

F bypass capacitor to ground.

OUT

(Pin 25): Buffered DAC Output.

X1/X2 (Pin 26): Gain Setting Resistor Pin. Connect to GND
for G = 2 or to V

OUT

for G = 1. This pin should always be

tied to a low impedance source, such as ground or V

OUT

to ensure stability of the output buffer when driving
capacitive loads.

CLR (Pin 27): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all input and DAC
registers to 0s.

LDAC (Pin 28): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
registers to the DAC register which updates the output
voltage. If held low, the DAC register loads data from the
input registers which will immediately update V

OUT

LTC1657L

DIGITAL I

TERFACE TRUTH TABLE

CLR

CSMSB

CSLSB

LDAC

FUNCTION

Clears input and DAC registers to zero

Loads DAC register with contents of input registers

Freezes contents of DAC register

Writes MSB byte into MSB input register

Writes LSB byte into LSB input register

Writes MSB and LSB bytes into MSB and LSB input registers

Inhibits write to MSB and LSB input registers

Inhibits write to MSB input register

Inhibits write to LSB input register

Data bus flows directly through input and DAC registers

G DIAGRA

CSMSB

LDAC

1657 TD

CSLSB

DATA

CWS

CWH

DWS

LDAC

DAC UPDATE

DWH

DATA VALID

LTC1657L

Figure 1. Effect of Negative Offset

Resolution (n): Resolution is defined as the number of
digital input bits (n). It defines the number of DAC output
states (2

) that divide the full-scale range. Resolution does

not imply linearity.

Full-Scale Voltage (V

): This is the output of the DAC

when all bits are set to 1.

Voltage Offset Error (V

): Normally, the DAC offset is the

voltage at the output when the DAC is loaded with all zeros.
The DAC can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.

DEFI ITIO S

DAC CODE

1657 F01

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:

= V

OUT

[(Code)(V

)/(2

1)]

Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.

LSB = (V

)/(2

1) = (V

)/65535

Nominal LSBs:

LTC1657L LSB = 2.5V/65535 = 38.1

DAC Transfer Characteristic:

REFHI REFLO

CODE

REFLO

OUT

( )

65536

G = 1 for X1/X2 connected to V

OUT

G = 2 for X1/X2 connected to GND

CODE = Decimal equivalent of digital input
(0

CODE

65535)

Zero-Scale Error (ZSE): The output voltage when the
DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.

Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:

INL (In LSBs) = [V

OUT

)

(code/65535)]

OUT

= The output voltage of the DAC measured at

the given input code

Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:

DNL = (

OUT

LSB)/LSB

OUT

= The measured voltage difference between
two adjacent codes

Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV ˇ s.

LTC1657L

used or the resistor ladder can be driven by an external
source in multiplying applications. The external reference
or source must be capable of driving the 16k (minimum)
DAC ladder resistance.

Internal reference output voltage noise spectral density
can be reduced with a bypass capacitor to ground. (Note:
The reference does not require a bypass capacitor to
ground for nominal operation.) When bypassing the refer-
ence, a small value resistor in series with the capacitor is
recommended to help reduce peaking on the output. A
10

resistor in series with a 4.7

F capacitor is optimum

for reducing reference generated noise. Internal reference
output noise at 1kHz is typically 80nV/

Hz.

DAC Resistor Ladder

The high and low end of the DAC ladder resistor string
(REFHI and REFLO, respectively) are not connected inter-
nally on this part. Typically, REFHI will be connected to
REFOUT and REFLO will be connected to GND. X1/X2
connected to GND will give the LTC1657L a full-scale
output swing of 2.5V.

Either of these pins can be driven up to V

1.5V when

using the buffer in the gain-of-1 configuration. The resis-
tor string pins can be driven to V

/2 when the buffer is in

the gain of 2 configuration. The resistance between these
two pins is typically 30k (16k min).

Voltage Output

The output buffer for the LTC1657L can be configured for
two different gain settings. By tying the X1/X2 pin to GND,
the gain is set to 2. By tying the X1/X2 pin to V

OUT

, the gain

is set to unity.

The LTC1657L rail-to-rail buffered output can source or
sink 5mA to within 500mV of the positive supply voltage
or ground at room temperature. The output stage is
equipped with a deglitcher that results in a midscale glitch
impulse of 8nV ˇ s. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40

when driving a load to

the rails.

Parallel Interface

The data on the input of the DAC is written into the DAC's
input registers when Chip Select (CSLSB and/or CSMSB)
and WR are at a logic low. The data that is written into the
input registers will depend on which of the Chip Selects
are at a logic low (see Digital Interface Truth Table). If WR
and CSLSB are both low and CSMSB is high, then only
data on the eight LSBs (D0 to D7) is written into the input
registers. Similarly, if WR and CSMSB are both low and
CSLSB is high, then only data on the eight MSBs (D8 to
D15) is written into the input registers. Data is written into
both the Least Significant Data Bits (D0 to D7) and the Most
Significant Bits (D8 to D15) at the same time if WR, CSLSB
and CSMSB are low. If WR is high or both CSMSB and
CSLSB are high, then no data is written into the input
registers.

Once data is written into the input registers, it can be
written into the DAC register. This will update the analog
voltage output of the DAC. The DAC register is written by
a logic low on LDAC. The data in the DAC register will be
held when LDAC is high.

When WR, CSLSB, CSMSB and LDAC are all low, the
registers are transparent and data on pins D0 to D15 flows
directly into the DAC register.

For an 8-bit data bus connection, tie the MSB byte data
pins to their corresponding LSB byte pins (D15 to D7, D14
to D6, etc).

Power-On Reset

The LTC1657L has an internal power-on reset that resets
all internal registers to 0's on power-up (equivalent to the
CLR pin function).

Reference

The LTC1657L includes an internal 1.25V reference, giv-
ing the LTC1657L a full-scale range of 2.5V in the gain-of-
2 configuration. The onboard reference in the LTC1657L is
not internally connected to the DAC's reference resistor
string but is provided on an adjacent pin for flexibility.
Because the internal reference is not internally connected
to the DAC resistor ladder, an external reference can be

OPERATIO

LTC1657L

APPLICATIO

S I

FOR

ATIO

Rail-to-Rail Output Considerations

In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.

If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.

Similarly, limiting can occur near full scale when the REF
pin is tied to V

/2. If V

REF

= V

/2 and the DAC full-scale

error (FSE) is positive, the output for the highest codes
limits at V

as shown in Figure 1c. No full-scale limiting

can occur if V

REF

is less than (V

FSE)/2.

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.

Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V

REF

= V

1657 F02

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

32768

65535

INPUT CODE

OUTPUT

VOLTAGE

(a)

REF

= V

REF

= V

(c)

INPUT CODE

OUTPUT
VOLTAGE

POSITIVE
FSE

LTC1657L

0.386 0.393*

(9.804 9.982)

GN28 (SSOP) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

9 10 11 12

0.229 0.244

(5.817 6.198)

0.150 0.157**

(3.810 3.988)

19 18 17

13 14

1615

0.016 0.050

(0.406 1.270)

0.015

0.004

(0.38

0.10)

TYP

0.0075 0.0098

(0.191 0.249)

0.053 0.069

(1.351 1.748)

0.008 0.012

(0.203 0.305)

0.004 0.009

(0.102 0.249)

0.0250

(0.635)

BSC

0.033

(0.838)

REF

PACKAGE DESCRIPTIO

GN Package

28-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

Dimensions in inches (millimeters) unless otherwise noted.

LTC1657L

N28 1098

0.255

0.015*

(6.477

0.381)

1.370*

(34.789)

MAX

0.020

(0.508)

MIN

0.125

(3.175)

MIN

0.130

0.005

(3.302

0.127)

0.065

(1.651)

TYP

0.045 0.065

(1.143 1.651)

0.018

0.003

(0.457

0.076)

0.005

(0.127)

MIN

0.100

(2.54)

BSC

0.009 0.015

(0.229 0.381)

0.300 0.325

(7.620 8.255)

0.325

+0.035
0.015

+0.889
0.381

8.255

(

)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

PACKAGE DESCRIPTIO

N Package

28-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

Dimensions in inches (millimeters) unless otherwise noted.

LTC1657L

PART NUMBER

DESCRIPTION

COMMENTS

LTC1446(L)

Dual 12-Bit V

OUT

DACs in SO-8 Package

= 5V (3V), V

OUT

= 0V to 4.095V (0V to 2.5V)

LTC1450(L)

Single 12-Bit V

OUT

DACs with Parallel Interface

= 5V (3V), V

OUT

= 0V to 4.095V (0V to 2.5V)

LTC1458(L)

Quad 12-Bit Rail-to-Rail Output DACs

= 5V (3V), V

OUT

= 0V to 4.095V (0V to 2.5V)

with Added Functionality

LTC1650

Single 16-Bit V

OUT

Industrial DAC in 16-Pin SO

5V, Low Power, Deglitched, 4-Quadrant Multiplying V

OUT

LTC1655(L)

Single 16-Bit V

OUT

DAC with Serial Interface in SO-8

= 5V (3V), Low Power, Deglitched, V

OUT

= 0V to 4.096V (0V to 2.5V)

LTC1657

Single 16-Bit V

OUT

DAC with Parallel Interface

= 5V, Low Power, Deglitched, V

OUT

= 0V to 4.096V

with Internal Reference

LINEAR TECHNOLOGY CORPORATION 2000

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

1657Li LT/TP 0400 4K ˇ PRINTED IN USA

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