LTC1645

Dual-Channel Hot Swap

Controller/Power Sequencer

The LTC

1645 is a 2-channel Hot Swap

controller that

allows a board to be safely inserted and removed from a
live backplane. Using external N-channel pass transistors,
the supply voltages can be ramped at a programmable
rate. Two high side switch drivers control the N-channel
gates for supply voltages ranging from 1.2V to 12V. The
two channels can be set to ramp up and down separately,
or they can be programmed to rise and fall simultaneously,
ensuring power supply tracking at the two outputs.

Programmable electronic circuit breakers protect against
shorts at either output. The RESET output can be used to
generate a system reset when a supply voltage falls below
a user-programmed voltage. An additional spare com-
parator is available for monitoring a second supply
voltage.

The LTC1645 is available in the 8- and 14-pin SO packages.

Hot Board Insertion

Power Supply Sequencing

Electronic Circuit Breaker

Allows Safe Board Insertion and Removal from a
Live Backplane

Programmable Power Supply Sequencing

Programmable Electronic Circuit Breaker

User-Programmable Supply Voltage Power-Up and
Power-Down Rate

High Side Drivers for External N-Channel FETs

Controls Supply Voltages from 1.2V to 12V

Ensures Proper Power-Up Behavior

Undervoltage Lockout

Glitch Filter Protects Against Spurious RESET Signals

, LTC and LT are registered trademarks of Linear Technology Corporation.

Hot Swap is a trademark of Linear Technology Corporation.

5V and 3.3V Hot Swap

5V and 3.3V Hot Swap Waveforms

5V/DIV

GATE

10V/DIV

OUT2

5V/DIV

OUT1

5V/DIV

0.005

IRF7413

0.005

10k

LOAD2

LOAD1

OUT1

5V
5A

OUT2

3.3V
5A

1645 TA01

0.01

25V

0.01

25V

IN2

IN1

GND

PLUG-IN CARD

BACKPLANE

SENSE1

CC2

GATE1

SENSE2 GATE2

LTC1645

(8-LEAD)

CONNECTOR 1

CONNECTOR 2

CC1

*LRF1206-01-R005-J (IRC)

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LTC1645

Supply Voltage (V

CC1

, V

CC2

) ................................. 13.2V

Input Voltage

FB, ON, COMP

..................... 0.3V to (V

CC1

+ 0.3V)

TIMER ................................................. 0.3V to 2.5V
SENSE1 ..................... (V

CC1

0.7V) to (V

CC1

+ 0.3V)

SENSE2 ...................... (V

CC1

0.7V) to (V

CC2

+ 0.3V)

Output Voltage

RESET, COMPOUT, FAULT ..................... 0.3V to 16V
GATE1, GATE2 ................. Internally Limited (Note 3)

Output Current

GATE1, GATE2 ...............................................

20mA

Operating Temperature Range

LTC1645C ............................................... 0

C to 70

LTC1645I ............................................ 40

C to 85

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC Characteristics

CC1

Supply Current

ON = V

CC1

= 5V, V

CC2

= 3.3V

1.1

2.0

CC2

Supply Current

ON = V

CC1

= 5V, V

CC2

= 3.3V

0.28

0.4

LKO1

CC1

Undervoltage Lockout

High to Low

2.16

2.23

2.3

LKO2

CC2

Undervoltage Lockout

High to Low

1.06

1.12

1.18

LKH

Undervoltage Lockout Hysteresis

FB Pin Voltage Threshold

High to Low

1.226

1.238

1.250

FB Pin Threshold Line Regulation

High to Low, V

CC1

= 2.375V to 12V

FBHST

FB Pin Voltage Threshold Hysteresis

COMP

Pin Voltage Threshold

High to Low

1.226

1.238

1.250

COMP

Pin Threshold Line Regulation

High to Low, V

CC1

= 2.375V to 12V

COMPHST

COMP

Pin Voltage Threshold Hysteresis

(Note 1)

The

denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T

= 25

2.375V

CC1

12V, 1.2V

CC2

12V unless otherwise noted (Note 2).

TOP VIEW

S PACKAGE

14-LEAD PLASTIC SO

CC2

SENSE2

GATE2

FAULT

RESET

GND

CC1

SENSE1

GATE1

TIMER

COMPOUT

COMP

JMAX

= 125

= 110

C/ W

TOP VIEW

CC1

SENSE1

GATE1

CC2

SENSE2

GATE2

GND

S8 PACKAGE

8-LEAD PLASTIC SO

JMAX

= 125

= 150

C/ W

ORDER PART

NUMBER

S8 PART MARKING

1645
1645I

LTC1645CS8
LTC1645IS8

ORDER PART

NUMBER

LTC1645CS
LTC1645IS

Consult factory for Military grade parts.

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

ELECTRICAL CHARACTERISTICS

LTC1645

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

TIMER Pin Voltage Threshold

1.212

1.230

1.248

TIMER Pin Threshold Line Regulation

CC1

= 2.375V to 12V

TIMER Pin Current

Timer On, V

TIMER

= 0.6V, V

CC1

= 5V

2.3

1.7

Timer Off, V

TIMER

= 1.5V

CB1

Circuit Breaker Trip Voltage 1

CB1

= (V

CC1

SENSE1

)

CB2

Circuit Breaker Trip Voltage 2

CB2

= (V

CC2

SENSE2

)

CBD

Circuit Breaker Trip Delay

= (V

SENSE

) > 60mV

1.5

GATE

n Pin Output Current

ON = 2.2V, V

GATE

= V

, V

CC1

= 5V, V

CC2

= 3.3V

12.5

7.5

ON = 0.7V, V

GATE

= V

, V

CC1

= 5V, V

CC2

= 3.3V

ON = 0.3V, V

GATE

= V

, V

CC1

= 5V, V

CC2

= 3.3V

GATE

External N-Channel Gate Drive

GATE

= (V

GATE

)

4.5

ONFPD

ON Pin Fast Pull-Down Threshold

Low to High

0.375

0.4

0.425

High to Low, Fast Pull-Down Engaged

0.35

0.375

0.4

ON1

ON Pin Threshold #1

Low to High, GATE1 Turns On

0.8

0.825

0.85

High to Low, GATE1 Turns Off

0.775

0.8

0.825

ON2

ON Pin Threshold #2

Low to High, GATE2 Turns On

2.025

2.050

High to Low, GATE2 Turns Off

1.975

2.025

ONHYST

ON Pin Hysteresis

ON Pin Input Current

CC1

= 5V, V

CC2

= 3.3V

0.01

Output Low Voltage

RESET, FAULT, COMPOUT, I

OUT

= 1.6mA, V

CC1

= 5V

0.16

0.4

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.

The

denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T

= 25

2.375V

CC1

12V, 1.2V

CC2

12V unless otherwise noted (Note 2).

Note 3: An internal zener on the GATE

n pins clamps the charge pump

voltage to a typical maximum operating voltage of 22V. External overdrive
of a GATE pin (for example, from capacitive coupling of V

glitches)

beyond the internal zener voltage may damage the device. If a lower
GATE

n pin clamp voltage is desired, use an external zener diode.

CC1

Supply Current vs Voltage

CC2

Supply Current vs Voltage

CC1

(V)

CC1

(mA)

1.0

2.0

3.0

0.5

1.5

2.5

1645 G01

= 25

CC2

= 1.5V

CC2

= 12V

CC2

(V)

CC2

(mA)

0.5

1.5

2.0

2.5

3.5

1645 G02

1.0

3.0

10 11 12

= 25

CC1

= 2.375V

CC1

= 12V

Supply Current vs Temperature

TEMPERATURE (

0.8

1.0

1.4

1645 G03

0.6

0.4

100

0.2

1.2

(mA)

CC1

= 5V

CC2

= 3.3V

CC1

CC2

ELECTRICAL CHARACTERISTICS

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1645

GATE Voltage vs Supply Voltage

GATE Voltage vs Temperature

Glitch Filter Time
vs Feedback Transient

RESET, FAULT, COMPOUT Output
Voltage vs Temperature

RESET, FAULT, COMPOUT Output
Voltage vs V

CC1

Fast Pull-Down Current vs V

CC1

HIGHEST V

(V)

GATE

(V)

1645 G04

= 25

TEMPERATURE (

14.0

GATE

(V)

14.2

14.6

14.8

15.0

16.0

15.4

1645 G05

14.4

15.6

15.8

15.2

100

CC1

= 5V

CC2

= 3.3V

FEEDBACK TRANSIENT (mV)

GLITCH FILTER TIME (

100

160

200

1645 G06

120

240

280

= 25

TEMPERATURE (

OUTPUT VOLTAGE (mV)

150

200

250

450

1645 G07

100

300

350

400

CC1

= 5V

SINK CURRENT = 3mA

SINK CURRENT = 1.6mA

CC1

(V)

OUTPUT VOLTAGE (mV)

800

700

600

500

400

300

200

100

1645 G08

= 25

SINK CURRENT = 3mA

SINK CURRENT = 1.6mA

CC1

(V)

FAST PULL-DOWN CURRENT (mA)

1645 G09

= 25

CC2

= 1.5V

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1645

CC2

(Pin 1/Pin 1): Positive Supply Input. V

CC2

can range

from 1.2V to 12V for normal operation. I

CC2

is typically

0.2mA. An undervoltage lockout circuit disables the
LTC1645 whenever the voltage at V

CC2

is less than 1.12V.

SENSE2 (Pin 2/Pin 2): V

CC2

Circuit Breaker Set Pin. With

a sense resistor placed in the supply path between V

CC2

and SENSE2, the circuit breaker trips when the voltage
across the resistor exceeds 50mV for more than 1.5

s. If

the circuit breaker trip current is set to twice the normal
operating current, only 25mV is dropped across the sense
resistor during normal operation. To disable the circuit
breaker, short V

CC2

and SENSE2 together.

GATE2 (Pin 3/Pin 3): Channel 2 High Side Gate Drive.
Connect to the gate of an external N-channel MOSFET. An
internal charge pump guarantees at least 4.5V of gate
drive. The charge pump is powered by the higher of V

CC1

and V

CC2

. When the ON pin exceeds 2V, GATE2 is turned

on by connecting a 10

A current source from the charge

pump output to the GATE2 pin and the voltage starts to
ramp up with a slope dv/dt = 10

A/C

GATE2

. While the ON

pin is below 2V but above 0.4V, a 40

A current source

pulls GATE2 toward ground. If the ON pin is below 0.4V,
the circuit breaker trips or the undervoltage lockout circuit
trips, the GATE2 pin is immediately pulled to ground with
a 12mA (typ) current source.

FAULT (Pin 4/NA): Circuit Breaker Fault. FAULT is an
open-drain output that pulls low when the circuit breaker
function trips. The circuit breaker is reset by pulling the ON
pin below 0.4V. An external pull-up is required to generate
a logic high at the FAULT pin. When the ON pin is low,
FAULT will release.

The circuit breaker can be programmed to automatically
reset by connecting the FAULT pin to the ON pin. In this
circuit configuration, if a logic device is driving the ON pin,
use a series resistor between the logic output and the ON
pin to prevent large currents from flowing.

RESET (Pin 5/NA): Open-Drain RESET Output. The RESET
pin is pulled low when the voltage at the FB pin goes below
1.238V or V

CC1

is below the undervoltage lockout thresh-

old. The RESET pin goes high one timing cycle after the
voltage at the FB pin goes above the FB pin threshold. The
ON pin must remain above 0.8V during this timing cycle.

An external pull-up is required to generate a logic high at
the RESET pin.

FB (Pin 6/NA): RESET Comparator Input. The FB pin is
used to monitor the output supply voltage with an external
resistive divider. When the voltage on the FB pin is lower
than 1.238V, the RESET pin is pulled low. A glitch filter on
the FB pin prevents fast transients from forcing RESET
low. When the voltage on the FB pin rises above the trip
point, the RESET pin goes high after one timing cycle.

GND (Pin 7/Pin 4): Ground. Connect to a ground plane for
optimum performance.

COMP

(Pin 8/NA): Spare Comparator Noninverting In-

put. When the voltage on COMP

is lower than 1.238V,

COMPOUT pulls low.

COMPOUT (Pin 9/NA): Open-Drain Spare Comparator
Output. COMPOUT pulls low when the voltage on COMP

is below 1.238V or V

CC1

is below the undervoltage lockout

threshold. An external pull-up is required to generate a
logic high at the COMPOUT pin.

ON (Pin 10/Pin 5): Analog Control Input. If the ON pin
voltage is below 0.4V, both GATE1 and GATE2 are imme-
diately pulled to ground. While the voltage is between 0.4V
and 0.8V, both GATE1 and GATE2 are each pulled to
ground with a 40

A current source. While the voltage is

between 0.8V and 2V, the GATE1 pull-up is turned on after
one timing cycle, but GATE2 continues to be pulled to
ground with a 40

A current source. When the voltage

exceeds 2V, both the GATE1 and GATE2 pull-ups are
turned on one timing cycle after the voltage exceeds 0.8V.

The ON pin is also used to reset the electronic circuit
breaker. If the ON pin is brought below and then above
0.4V following the trip of the circuit breaker, the circuit
breaker resets, and a normal power-up sequence occurs.

TIMER: (Pin 11/NA): System Timing Pin. The TIMER pin
requires an external capacitor to ground to generate a
timing delay. The pin is used to set the delay before the
RESET pin goes high after the output supply voltage is
good as sensed by the FB pin. It is also used to set the delay
between the ON pin exceeding 0.8V and the GATE1 and
GATE2 pins turning on (GATE2 turns on only if the ON pin
exceeds 2V).

(14-Lead Package/8-Lead Package)

PI FU CTIO S

LTC1645

(14-Lead Package/8-Lead Package)

Whenever the timer is inactive, an internal N-channel FET
shorts the TIMER pin to ground. Activating the timer
connects a 2

A current source from V

CC1

to the TIMER pin

and the voltage starts to ramp up with a slope dv/dt = 2

TIMER

. When the voltage reaches the trip point (1.23V),

the timer is reset by pulling the TIMER pin back to ground.
The timer period is (1.23V ˇ C

TIMER

)/2

GATE1 (Pin 12/Pin 6): Channel 1 High Side Gate Drive.
Connect to the gate of an external N-channel MOSFET. An
internal charge pump guarantees at least 4.5V of gate
drive. The charge pump is powered by the higher of V

CC1

and V

CC2

. When the ON pin exceeds 0.8V, GATE1 is turned

on by connecting a 10

A current source from the charge

pump output to the GATE1 pin and the voltage starts to
ramp up with a slope dv/dt = 10

A/C

GATE1

. While the ON

pin is below 0.8V but above 0.4V, a 40

A current source

pulls GATE1 toward ground. If the ON pin is below 0.4V,

the circuit breaker trips or the undervoltage lockout circuit
trips, the GATE1 pin is immediately pulled to ground with
a 12mA (typ) current source.

SENSE1 (Pin 13/Pin 7): V

CC1

Circuit Breaker Set Pin. With

a sense resistor placed in the supply path between V

CC1

and SENSE1, the circuit breaker trips when the voltage
across the resistor exceeds 50mV for more than 1.5

s. If

the circuit breaker trip current is set to twice the normal
operating current, only 25mV is dropped across the sense
resistor during normal operation. To disable the circuit
breaker, short V

CC1

and SENSE1 together.

CC1

(Pin 14/Pin 8): Positive Supply Input. V

CC1

can range

from 2.375V to 12V for normal operation. I

CC1

is typically

1mA. An undervoltage lockout circuit disables the chip
whenever the voltage at V

CC1

is less than 2.23V. All internal

logic is powered by V

CC1

2.23V

UVL

0.8V

0.4V

REF

1.5

FILTER

1.12V

UVL

1.5

FILTER

LOGIC

GLITCH

FILTER

REF

CHARGE

PUMP

1.238V

REFERENCE

50mV

CC1

SENSE1

CC2

SENSE2

GATE1

GATE2

RESET

GND

COMP

COMPOUT

FAULT 4

1645 BD

TIMER 11

PI FU CTIO S

BLOCK DIAGRA

LTC1645

Hot Circuit Insertion

When a circuit board is inserted into a live backplane, the
supply bypass capacitors on the board can draw huge
transient currents from the backplane power bus as they
charge. These transient currents can cause permanent
damage to the connector pins and produce glitches on the
system supply, resetting other boards in the system.

The LTC1645 is designed to turn a board's supply voltages
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
provides a system reset signal and a spare comparator to
indicate when board supply voltages drop below user-
programmable voltages, and a fault signal to indicate if an
overcurrent condition has occurred.

The LTC1645 can be located before or after the connector
as shown in Figure 1. A staggered PCB connector can
sequence pin connections when plugging and unplugging
circuit boards. Alternatively, the control signal can be
generated by processor control.

Power Supply Tracking and Sequencing

Some applications require that the potential difference
between two power supplies not exceed a certain voltage.
This requirement applies during power-up and power-
down as well as during steady state operation, often to
prevent latch-up in a dual supply ASIC. Other systems
require one supply to come up after another, for example,
if a system clock needs to start before a block of logic.
Typical dual supplies or backplane connections may come
up at arbitrary rates depending on load current, capacitor
size, soft-start rates, etc. Traditional solutions are cum-
bersome and require complex circuitry to meet the power
supply requirements.

The LTC1645 provides a simple solution to power supply
tracking and sequencing needs. The LTC1645 guarantees
supply tracking by ramping the supplies up and down
together (see Figure 15). The sequencing capabilities of
the LTC1645 allow nearly any combination of supply
ramping (e.g., see Figure 17) to satisfy various sequenc-
ing specifications. See the Power Supply Tracking and
Sequencing Applications section for more information.

APPLICATIO S I FOR ATIO

SENSE

FAULT

OUT

FAULT

GND

GATE

LTC1645

BACKPLANE

CONNECTOR

STAGGERED PCB
EDGE CONNECTOR

LOAD

(a) Hot Swap Controller on Motherboard

SENSE

FAULT

OUT

FAULT

GND

GATE

LTC1645

1645 F01

LOAD

BACKPLANE

CONNECTOR

STAGGERED PCB
EDGE CONNECTOR

(b) Hot Swap Controller on Daughterboard

Figure 1. Staggered Pins Connection

LTC1645

Power Supply Ramping

The power supplies on a board are controlled by placing
external N-channel pass transistors in the power paths as
shown in Figure 2. Consult Table 1 for a selection of
N-channel FETs suitable for use with the LTC1645. R

SENSE1

and R

SENSE2

provide current fault detection and R1 and R2

prevent high frequency oscillation. By ramping the gates
of the pass transistors up and down at a controlled rate,
the transient surge current (I = C ˇ dv/dt) drawn from the
main backplane supply is limited to a safe value when the
board makes connection.

When power is first applied to the chip, the gates of the
N-channels (GATE1 and GATE2 pins) are pulled low. After
the ON pin is held above 0.8V for at least one timing cycle,
the voltage at GATE1 begins to rise with a slope equal to
dv/dt = 10

A/C1 (Figure 3), where C1 is the external

capacitor connected between the GATE1 pin and GND. If
the ON pin is brought above 2V (and the ON pin has been
held above 0.8V for at least one timing cycle), the voltage
at GATE2 begins to rise with a slope equal to dv/dt =
10

A/C2.

The ramp time for each supply is t = (V

ˇ C

n)/10

A. If

the ON pin is pulled below 2V for GATE2 or 0.8V for GATE1
(but above 0.4V), a 40

A current source is connected from

GATE

n to GND, and the voltage at the GATEn pin will ramp

down, as shown in Figure 4.

Ringing

Good engineering practice calls for bypassing the supply
rail of any circuit. Bypass capacitors are often placed at the
supply connection of every active device, in addition to one
or more large value bulk bypass capacitors per supply rail.
If power is connected abruptly, the bypass capacitors slow
the rate of rise of voltage and heavily damp any parasitic
resonance of lead or trace inductance working against the
supply bypass capacitors.

The opposite is true for LTC1645 Hot Swap circuits on a
daughterboard. In most cases, on the powered side of the
N-channel FET switches (V

) there is no supply bypass

capacitor present. An abrupt connection, produced by
plugging a board into a backplane connector, results in a
fast rising edge applied to the V

line of the LTC1645.

APPLICATIO S I FOR ATIO

Figure 4. Supply Turning Off

Figure 3. Supply Turning On

Figure 2. Typical Hot Swap Connection

SENSE2

R2
10

TIMER

LOAD1

LOAD2

R1
10

CC1

FAULT

SENSE1

GATE2

CC2

CC1

OUT2

OUT1

LTC1645

(14-LEAD)

TIMER

GND

COMP

COMPOUT

SENSE2

GATE1

1645 F02

RESET

SENSE1

OUT

GATE

1645 F03

GATE

SLOPE = 10

A/C

OUT

GATE

1645 F04

GATE

SLOPE = 40

A/C

LTC1645

APPLICATIO S I FOR ATIO

(a) Undamped V

Waveform (48" Leads)

(b) Undamped V

Waveform (8" Leads)

Figure 5. Ring Experiment

No bulk capacitance is present to slow the rate of rise and
heavily damp the parasitic resonance. Instead, the fast
edge shock excites a resonant circuit formed by a combi-
nation of wiring harness, backplane and circuit board
parasitic inductances and FET capacitance. In theory, the
peak voltage should rise to 2X the input supply, but in
practice the peak can reach 2.5X, owing to the effects of
voltage dependent FET capacitance.

The absolute maximum V

potential for the LTC1645 is

13.2V; any circuit with an input of 5V or greater should be
scrutinized for ringing. A well-bypassed backplane should
not escape suspicion: circuit board trace inductances of as
little as 10nH can produce sufficient ringing to overvoltage
V

Check ringing with a fast storage oscilloscope (such as a
LECROY 9314AL DSO) by attaching coax or a probe to V

and GND, then repeatedly inserting the circuit board into
the backplane. Figures 5a and 5b show typical results in a
12V application with different V

lead lengths. The peak

amplitude reaches 22V, breaking down the ESD protection
diode in the process.

There are two methods for eliminating ringing: clipping
and snubbing. A transient voltage suppressor is an effec-
tive means of limiting peak voltage to a safe level.
Figure 6 shows the effect of adding an ON Semiconductor,
1SMA12CAT3, on the waveform of Figure 5.

Figures 7a and 7b show the effects of snubbing with
different RC networks. The capacitor value is chosen as
10X to 100X the FET C

OSS

under bias and R is selected for

best damping--1

to 50

depending on the value of

parasitic inductance.

OUT

0.1

1645 F05

0.01

12V

IRF7413

LOAD

LTC1645

POWER

LEADS

SCOPE
PROBE

s/DIV

1645 F05a

4V/DIV

24V

s/DIV

4V/DIV

1645 F05b

24V

LTC1645

APPLICATIO S I FOR ATIO

(a) V

Short-Circuit Supply Current Glitch Without Any Limiting

(b) V

Supply Glitch Without Any Limiting

(c) V

Short-Circuit Supply Current Glitch

with 2

H Series Inductor

(d) V

Supply Glitch with 2

H Series Inductor

Figure 8. Supply Glitch

Supply Glitching

LTC1645 Hot Swap circuits on the backplane are generally
used to provide power-up/down sequence at insertion/
removal as well as overload/short-circuit protection. If a
short-circuit occurs at supply ramp-up, the circuit breaker

trips. The partially enhanced FET is easily disconnected
without any supply glitch.

If a dead short occurs after a supply connection is made
(Figure 8), the sense resistor R1 and the R

DS(ON)

of the

fully enhanced FET provide a low impedance path for

0.1

1645 F08

0.01

12V

IRF7413

LTC1645

SUPPLY

GLITCH

BACKPLANE CONNECTOR

BOARD WITH POSSIBLE

SHORT-CIRCUIT FAULT

100

s/DIV

25A/DIV

1645 F08a

s/DIV

4V/DIV

1645 F08b

GATE

s/DIV

5A/DIV

1645 F08c

s/DIV

4V/DIV

1645 F08d

GATE

LTC1645

nearly unlimited current flow. The LTC1645 discharges
the GATE pin in a few microseconds, but during this
discharge time current on the order of 150 amperes flows
from the V

power supply. This current spike glitches the

power supply, causing V

to dip (Figure 8a and 8b).

On recovery from overload, some supplies may over-
shoot. Other devices attached to this supply may reset or
malfunction and the overshoot may also damage some
components. An inductor (1

H to 10

H) in series with the

FET's source limits the short-circuit di/dt, thereby limiting
the peak current and the supply glitch (Figure 8c and 8d).
Additional power supply bypass capacitance also reduces
the magnitude of the V

glitch.

Reset

The LTC1645 uses an internal 1.238V bandgap reference,
a precision voltage comparator, and a resistive divider to
monitor the output supply voltage (Figure 9).

Whenever the voltage at the FB pin rises above its reset
threshold (1.238V), the comparator output goes high, and
a timing cycle starts (see Figure 10, time points 1 and 4).
After a complete timing cycle, RESET is released. An
external pull-up is required for the RESET pin to rise to a
logic high.

When the voltage at the FB pin drops below its reset
threshold, the comparator output goes low. After passing
through a glitch filter, RESET is pulled low (time point 2).
If the FB pin rises above the reset threshold for less than
a timing cycle, the RESET output remains low (time
point 3).

APPLICATIO S I FOR ATIO

Glitch Filter

The LTC1645 has a glitch filter to prevent RESET from
generating a spurious system reset in the presence of
transients on the FB pin. The filter is 20

s for large

transients (greater than 150mV) and up to 80

s for

smaller transients. The relationship between glitch filter
time and the transient voltage is shown in Typical Perfor-
mance Characteristics: Glitch Filter Time vs Feedback
Transient.

Timer

The system timing for the LTC1645 is generated by the
circuitry shown in Figure 11. The timer is used to set the
turn-on delay after the ON pin goes high. It also sets the
delay before the RESET pin goes high after the FB pin
exceeds 1.238V.

Whenever the timer is off, the internal N-channel shorts
the TIMER pin to ground (Figure 11). Activating the timer
connects a 2

A current from V

CC1

to the TIMER pin and the

Figure 10. Supply Monitor Waveforms

Figure 9. Supply Monitor Block Diagram

Figure 11. System Timing Block Diagram

COMP

TIMER

RESET

OUT

TIMER

10k

1645 F09

RESET

LOGIC

1.238V

REFERENCE

1.23V

1645 F10

OUT

TIMER

RESET

COMP

TIMER

1.23V

SUPPLY

MONITOR

1645 F11

LOGIC

LTC1645

voltage on the external capacitor C

TIMER

starts to ramp up

with a slope dv/dt = 2

A/C

TIMER

. When the voltage reaches

the trip point (1.23V), the timer is reset by pulling the
TIMER pin back to ground. The timer period is
t = (1.23V ˇ C

TIMER

)/2

A. For a 200ms delay, use a 0.33

capacitor.

Electronic Circuit Breaker

The LTC1645 features an electronic circuit breaker func-
tion that protects against short circuits or excessive out-
put currents. By placing sense resistors between the
supply inputs and sense pins of the supplies, the circuit
breaker trips whenever the voltage across either sense
resistor is greater than 50mV for more than 1.5

s. If the

circuit breaker trips, both GATE

pins are immediately

pulled to ground and the external N-channels FETs are
quickly turned off (time point 6 in Figure 12). The circuit
breaker resets and another timing cycle starts by taking

the ON pin below 0.4V and then high as shown at time
point 7.

At the end of the timer cycle (time point 8), the charge
pump turns on again. If the circuit breaker feature is not
required, short the SENSE

n pin to V

If the 1.5

s response time is too fast to reject supply noise,

add external resistors and capacitors R

and C

to the

sense circuit as shown in Figure 13.

The ON Pin

The ON pin is used to control system operation as shown
in Figure 14. At time point 1, the board makes connection
and the supplies power up the chip. At time point 2, the ON
pin goes high and a timer cycle starts as long as both V

pins are higher than the undervoltage lockout trip point
(2.23V for V

CC1

and 1.12V for V

CC2

) and an overcurrent

fault is not detected. At the end of the timer cycle (time
point 3), the charge pump is turned on and the GATE

n pin

voltages start to ramp up with the output supply voltages,
V

OUT

, following one gate-to-source voltage drop lower.

At time point 4, V

OUT2

reaches its power-good trip level

(this example assumes the FB pin resistive divider is
connected to V

OUT2

) and a timing cycle starts. At the end

of the timing cycle (time point 5), RESET goes high and the
power-up process is complete.

APPLICATIO S I FOR ATIO

Figure 13. Extending the Short-Circuit Protection Delay

Figure 12. Current Fault Timing

Figure 14. ON Pin Waveforms

1645 F14

0.8V
0.4V

1 2

6 7

10 11 12 13 14 15 16 17

18 19 20

GATE1

GATE2

OUT1

OUT2

TIMER

RESET

RAMPING UP AND

DOWN TOGETHER

RAMPING UP AND

TURNING OFF FAST

RAMPING UP AND

DOWN SEPARATELY

SENSE

LTC1645

GATE

1645 G13

RESET

OUT

GATE

1645 F12

TIMER

SENSE

1 2

RAMPING UP

RESET FAULT

AND RAMP UP

CURRENT

FAULT

LTC1645

An external hard reset is initiated at time point 6. The ON
pin is forced below 0.8V but above 0.4V, and the GATE

pin voltages start to ramp down. V

OUT

also starts to ramp

down, and RESET goes low when V

OUT2

drops below the

power-good trip level at time point 7.

Time points 8 to 15 are similar to time points 1 to 7, except
the ON pin's different voltage thresholds are used to ramp
V

OUT1

and V

OUT2

separately. At time point 8, the ON pin

goes above 0.8V but below 2V, and one timing cycle later
(time point 9) GATE1 begins to ramp up with V

OUT1

following one gate-to-source voltage drop lower. At time
point 10, the ON pin goes above 2V and GATE2 immedi-
ately begins ramping up with V

OUT2

following one gate-to-

source voltage drop lower. As soon as V

OUT2

reaches its

power-good trip level at time point 11, a timing cycle
starts. At the end of the timing cycle (time point 12),
RESET goes high and the power-up process is complete.

The ON pin is forced below 2V but above 0.8V at time point
13 and the GATE2 pin voltage starts to ramp down. V

OUT2

also starts to ramp down and RESET goes low when V

OUT2

drops below the power-good trip level at time point 14.
When the ON pin goes below 0.8V but above 0.4V at time
point 15, GATE1 and V

OUT1

ramp down.

Time points 16 to 19 show the same power-up sequence
as time points 2 to 5, while time point 20 demonstrates the
GATE

n pins being pulled immediately to ground (instead

of ramping down) by the ON pin going below 0.4V.

Power Supply Tracking and Sequencing Applications

The LTC1645 is able to sequence V

OUT

in a number of

ways, including ramping V

OUT1

up first and down last;

ramping V

OUT1

up first and down first; ramping V

OUT1

first and V

OUT1

and V

OUT2

down together; and ramping

OUT1

and V

OUT2

up and down together.

Figure 15 shows an application ramping V

OUT1

and V

OUT2

up and down together. The ON pin must reach 0.8V to
ramp up V

OUT1

and V

OUT2

. The spare comparator pulls the

ON pin low until V

CC2

is above 2.3V, and the ON pin cannot

reach 0.8V before V

CC1

is above 3V. Thus, both input

supplies must be within regulation before a timing cycle
can start. At the end of the timing cycle, the output voltages
ramp up together. If either input supply falls out of
regulation, the gates of Q1 and Q2 are pulled low together.
Figure 16 shows an oscilloscope photo of the circuit in
Figure 15.

APPLICATIO S I FOR ATIO

Figure 15. Ramping 3.3V and 2.5V Up and Down Together

1/2 Si4920DY

0.01

1.18k
1%

10k

1.37k
1%

0.1

25V

0.33

*WSL1206-01-1% (VISHAY DALE)

LOAD1

LOAD2

D1
1N4002

D3
MBR0530T1

D2
1N4002

BOTH CURRENT LIMITS: 5A

CC1

FAULT

TIMER

GND

SENSE1

GATE2

GATE1

CC2

TRIP

POINT:

IN1

3.3V

IN2

2.5V

OUT1

3.3V
2.5A

OUT2

2.5V
2.5A

P RESET

LTC1645

(14-LEAD)

COMP

COMPOUT

SENSE2

1645 F15

RESET

1.18k
1%

4.99k
1%

10k

1.37k
1%

1.82k
1%

LTC1645

IN2

5V/DIV

IN1

5V/DIV

OUT2

5V/DIV

OUT1

5V/DIV

TIMER

2V/DIV

RESET

5V/DIV

Figure 16. Ramping 3.3V and 2.5V Up and Down Together

APPLICATIO S I FOR ATIO

This circuit guarantees that: (1) V

OUT1

never exceeds

OUT2

by more than 1.2V, and (2) V

OUT2

is never greater

than V

OUT1

by more than 0.4V. On power-up, V

OUT1

and

OUT2

ramp up together. On power-down, the LTC1645

turns off Q1 and Q2 simultaneously. Charge remains
stored on C

LOAD1

and C

LOAD2

and the output voltages will

vary depending on the loads. D1 and D2 turn on at

(

0.5V each), ensuring condition 1 is satisfied, while D3

prevents violations of condition 2. Different diodes may be
necessary for different output voltage configurations.
Barring an overvoltage condition at the input(s), the only
time these diodes might conduct current is during a
power-down event, and then only to discharge C

LOAD1

LOAD2

. In the case of an input overvoltage condition that

causes excess current to flow, the circuit breaker will trip
if the current limit level is set appropriately.

Figure 17 shows an application circuit where V

OUT1

ramps up before V

OUT2

. V

OUT1

is initially discharged and

D1 is reverse-biased, thus the voltage at the ON pin is
determined only by V

CC1

through the resistor divider R1

and R2. The voltage at the ON pin exceeds 0.8V if V

CC1

above 4.6V and V

OUT1

begins to ramp up after a timing

cycle. As V

OUT1

ramps up, D1 becomes forward-biased

and pulls the ON pin above 2V when V

OUT1

4.5V. This

turns on GATE2 and V

OUT2

ramps up. The FB comparator

monitors V

OUT2

, and the spare comparator monitors

OUT1

with R

HYST

creating

50mV of hysteresis.

Power Supply Multiplexer

Using back-to-back FETs, the LTC1645 can Hot Swap two
supplies to the same output, automatically selecting the
primary supply if present or the secondary supply if the
primary supply is not available. Referring to Figure 18, a
diode-or circuit provides power to the LTC1645 if either
supply is up. Schottky diodes are used to prevent the
voltage at V

CC1

from approaching the undervoltage lock-

out threshold. This application assumes that if a supply is
not present, the supply input is floating.

If only the 3.3V supply is present, the voltage at the COMP

pin is below the trip point and COMPOUT pulls the base of
Q3 low, allowing the GATE1 pin to ramp up normally. The
voltage at the ON pin exceeds 0.8V if the 3.3V supply is
greater than 3V, ramping up GATE1 and turning on Q1A and
Q1B. The ON pin does not exceed 2V (unless the 3.3V supply
exceeds 7.5V!), keeping GATE2 low and Q2A and Q2B off.

If only the 5V supply is present or if both supplies are
present, the COMP

pin is above 1.238V and COMPOUT

allows the base of Q3 to be pulled high by R2. This turns
Q3 on, keeping GATE1 low and Q1A and Q1B off. The
voltage at the ON pin is pulled above 2V by R1 and GATE2
turns Q2A and Q2B on.

LTC1645

Figure 17. Ramping Up 5V Followed by 3.3V

IRF7413

28k
1%

HYST

681k

14.7k
1%

10k
1%

0.01

25V

0.33

FAULT

TIMER

GND

CC1

SENSE1

GATE2

GATE1

CC2

IN2

3.3V

IN1

OUT1

5V
5A

D1
1N4148

OUT2

3.3V
5A

LTC1645

(14-LEAD)

COMP

COMPOUT

SENSE2

FAULT

1645 F17

0.01

25V

RESET

LOAD1

LOAD2

10k

R1
47.5k
1%

R2
10k
1%

10k

10k
1%

P RESET2

P RESET

0.005

13k
1%

*LRF1206-01-R005-J (IRC)

BOTH CURRENT LIMITS: 10A

APPLICATIO S I FOR ATIO

Figure 18. Power Supply Multiplexer

Q1A

Q1B

R2
10k

0.1

25V

0.33

CC1

FAULT

TIMER

GND

SENSE1

GATE2

GATE1

CC2

IN1

3.3V

IN2

D1
1/2 BAT54C

D2
1/2
BAT54C

Q3
PN2222

OUT

5V OR
3.3V
5A

LTC1645

(14-LEAD)

COMP

COMPOUT

SENSE2

1645 F18

0.1

25V

RESET

22.6k
1%

10k

11.3k
1%

IRF7313

Q2A

Q2B

IRF7313

LTC1645

APPLICATIO S I FOR ATIO

Using the LTC1645 as a Linear Regulator

This application uses the LTC1645 to Hot Swap one
primary supply and generate a secondary low dropout
regulated supply. Figure 19 shows how to switch a 5V
supply and create a 3.3V supply using the spare compara-
tor and one additional transistor. The COMP

pin is used

to monitor the 3.3V output. As the voltage on the gate of
Q2 increases, the 3.3V output increases. At the 3.3V
threshold the spare comparator trips. The COMPOUT pin

goes high which turns on Q3. This lowers the voltage on
the gate of Q2. This feedback loop is compensated by
capacitors C1 and C2 and resistor R1. When power is first
applied, the FB pin is low and RESET holds one side of C2
low, slowing the ramp-up of V

OUT2

. As V

OUT2

exceeds

2.75V, RESET releases to allow improved loop transient
response. Figure 20 shows the load transient response
and voltage ripple of the generated supply.

IRF7413

0.01

IRFZ24

10k

R1
200k

Q3
PN2222

1.5k
1%

12.1k
1%

10k
1%

2.49k
1%

C2
0.1

25V

C1
0.033

0.1

25V

0.33

470

F**

LOAD1

BOTH CURRENT LIMITS: 5A

CC1

FAULT

SENSE1

TIMER

GND

GATE2

CC2

OUT2

3.3V
2.5A

OUT1

5V
2.5A

LTC1645

(14-LEAD)

COMP

COMPOUT

SENSE2

GATE1

1645 F19

RESET

LRF1206-01-R010-J (IRC)
T510X477K006AS (KEMET)

Figure 19. Switching 5V and Generating 3.3V

OUT2

0.1V/DIV

OUT2

1A/DIV

2.5A

0.5A

Figure 20. Load Transient Response and Voltage Ripple

LTC1645

APPLICATIO S I FOR ATIO

Switching Regulator Supply Sequencing

Figure 21 shows the LTC1645 sequencing two power
supplies, the lower of which is generated by the LTC1430A
switching regulator. Connecting the regulator's FB pin
resistor divider (R1 and R2) to the other side of the pass
FET (Q1) allows the LTC1430A to compensate for the
voltage drop across R

SENSE1

and Q1, assuring an accurate

voltage output. The spare comparator holds the LTC1645's
ON pin low until the LTC1430A's output is at least 3V, and
shuts both channels off if it drops below 3V. When the
ON/OFF signal is taken high to 5V (turn-on), the voltage at
the ON pin rises with an RC exponential characteristic,
reaching 0.8V first. This starts a timing cycle, and GATE1
begins to rise. GATE2 starts to ramp up after the ON pin
reaches 2V. As long as the timing cycle is shorter than the
time for the ON pin to rise from 0.8V to 2V, V

OUT2

ramps

up after V

OUT1

. RESET goes high one timing cycle after

OUT1

exceeds 3V. When the ON/OFF signal is brought

low, the voltage at the ON pin exponentially decays and
GATE2 ramps down before GATE1. RESET goes low as
soon as V

OUT1

falls below 3V. Figure 22 shows the power-

up and power-down sequences of the circuit in Figure 21.

Switching Regulator Hot Swapping

High current switching regulators usually require large
bypass capacitors on both input and output for proper
operation. The application in Figure 23 controls the inrush
current to the LTC1649's input bypass capacitors and
ramps the two output voltages up and down together. As
with the previous application, connecting the regulator's
FB pin resistor divider to the other side of the output pass
FET (Q2) allows the LTC1649 to compensate for the
voltage drop across Q2, assuring an accurate voltage
output. The voltage at the LTC1645's ON pin reaches 0.8V
when V

exceeds 3V, and GATE1 begins to ramp up one

timing cycle later. As the regulator's output rises, D2 pulls
the ON pin above 2V and GATE2 begins to rise, ramping
V

OUT1

and V

OUT2

up together. RESET goes high one timing

cycle after V

OUT1

exceeds 3V and V

OUT2

exceeds 2.35V.

Figure 24 shows the circuit in Figure 23 powering up.

Care should be taken connecting a switching regulator's
FB or SENSE pins to a node other than its output. Depend-
ing on the regulator's internal architecture, unusual be-
havior may occur as it tries in vain to raise the voltage at

2V/DIV

OUT1

2V/DIV

REGOUT

2V/DIV

Figure 22. Switching Regulator Supply Sequencing

OUT2

2V/DIV

RESET

5V/DIV

LTC1645

1/2 Si4920DY

2.67k

3.16k

1.87k

0.047

25V

REGOUT

4700pF

0.1

2.4

CDRH1272R4

0.33

FAULT

TIMER

GND

SENSE1

CC1

GATE2

GATE1

CC2

OUT1

3.3V

2.5A

OUT2

2.5A

LTC1645

(14-LEAD)

COMP

COMPOUT

SENSE2

ON/OFF

FAULT

1645 F21

0.047

25V

RESET

LOAD1

LOAD2

1500

6.3V

130k

162k

22k

10k

MBRS130T3

Si4410DY

MBR0530T1

10k

1.15k

RESET

SENSE2

0.01

SENSE1

0.01

16.5k

16.9k

*LRF1206-01-R010-J (IRC)

0.1

10V

1500

6.3V

4700pF

270pF

680pF

CC2

SHDN

COMP

CC1

GND

LTC1430ACS8

Figure 21. Switching Regulator Supply Sequencing

APPLICATIO S I FOR ATIO

LTC1645

Figure 23. Switching Regulator Hot Swap

FDB8030L

FDS6680

1500

6.3V

1500

6.3V

220

MBR0530LT1

1.02k

2.67k

1.13k

0.01

25V

220pF

0.015

0.01

2200pF

5.1

1.2

REGOUT

REGIN

100

0.33

0.1

100k

MBR0530LT1

0.1

0.33

0.01

FAULT

TIMER

GND

CC1

SENSE1

GATE2

GATE1

CC2

OUT1

3.3V

10A

LTC1645

(14-LEAD)

COMP

COMPOUT

SENSE2

FAULT

1645 F23

0.047

25V

3.01k

3.09k

RESET

LOAD2

LOAD1

OUT2

2.5V

15A

3.3V

GND

10k

4.99k

1.82k

MBR0530T1

10k

33k

1.8k

1N4148

1.87k

GND

RESET

0.003

*LRF2010-01-R003-J (IRC)

**MBRS340T (ON SEMICONDUCTOR)

ETQP6F1R2HFA (PANASONIC)

0.33

0.1

18k

IRF7801

CC2

MAX

COMP

CPOUT

CC1

GND

SHDN

LTC1649

APPLICATIO S I FOR ATIO

LTC1645

Table 1. N-Channel Selection Guide

CURRENT

PART

LEVEL

NUMBER

MANUFACTURER

DESCRIPTION

1A to 2A

NDH8503N

Fairchild

Dual N-Channel
R

DS(ON)

= 0.033

SuperSOT-8

1A to 2A

Si6928DQ

Siliconix

Dual N-Channel
R

DS(ON)

= 0.035

TSSOP-8

2A to 5A

Si4920DY

Siliconix

Dual N-Channel
R

DS(ON)

= 0.025

SO-8

2A to 5A

IRF7313

International

Dual N-Channel

Rectifier

DS(ON)

= 0.029

SuperSOT-8

5A to 10A

Si4420

Siliconix

Single N-Channel
R

DS(ON)

= 0.009

SO-8

5A to 10A

FDS6680

Fairchild

Single N-Channel
R

DS(ON)

= 0.01

SO-8

5A to 10A

IRF7413

International

Single N-Channel

Rectifier

DS(ON)

= 0.011

SO-8

5A to 10A

MMSF3300

ON Semiconductor

Single N-Channel
R

DS(ON)

= 0.0125

SO-8

10A to 20A

FDB8030L

Fairchild

Single N-Channel
R

DS(ON)

= 0.0035

TO-263AB

10A to 20A

SUD75N03-04

Siliconix

Single N-Channel
R

DS(ON)

= 0.004

PAK

2V/DIV

OUT2

2V/DIV

REGOUT

2V/DIV

Figure 24. Switching Regulator Hot Swap

OUT1

2V/DIV

REGIN

2V/DIV

RESET

5V/DIV

APPLICATIO S I FOR ATIO

OUT

*USER SELECTED VOLTAGE CLAMP
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET

1645 F25

D1*

1N4148

D4*

1N4148

Figure 25. Optional Gate Clamp

its FB or SENSE pin. In the case of the LTC1649, large peak
currents result if the FB pin is at ground and not connected
directly to the output inductor and capacitors. To keep the
peak currents under control, R1, R2 and D1 hold the FB pin
above ground but below its normal regulated value until
V

OUT2

ramps up and D1 reverse-biases.

Power N-Channel Selection

The R

DS(ON)

of the external pass transistors must be low

enough so that the voltage drop across them is 100mV or
less at full current. If the R

DS(ON)

is too high, the voltage

drop across the transistor can cause the output voltage to
trip the reset circuit. The transistors listed in Table 1 or
other similar transistors are recommended for use with
the LTC1645.

Low voltage applications may require the use of logic-level
FETs; ensure their maximum V

rating is sufficient for the

application. GATE voltage as a function of V

is illustrated

in the Typical Performance curves. If lower GATE drive is
desired, connect a diode in series with a zener between
GATE and V

or between GATE and V

OUT

as shown in

Figure 25.

LTC1645

Dimensions in inches (millimeters) unless otherwise noted.

S Package

14-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.150 0.157**

(3.810 3.988)

0.337 0.344*

(8.560 8.738)

0.228 0.244

(5.791 6.197)

0.016 0.050

(0.406 1.270)

0.010 0.020

(0.254 0.508)

TYP

0.008 0.010

(0.203 0.254)

S14 1298

0.053 0.069

(1.346 1.752)

0.014 0.019

(0.355 0.483)

TYP

0.004 0.010

(0.101 0.254)

0.050

(1.270)

BSC

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

PACKAGE DESCRIPTIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1645

1645f LT/TP 0400 4K ˇ PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1999

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LTC1643H

LTC1647

Dual Hot Swap Controller

Dual ON Pins for Supplies from 3V to 15V

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

1/2 Si4920DY

0.01

1.18k
1%

10k

1.37k
1%

0.1

25V

0.33

*WSL1206-01-1% (VISHAY DALE)

LOAD1

LOAD2

D1
1N4002

D3
MBR0530T1

D2
1N4002

BOTH CURRENT LIMITS: 5A

CC1

FAULT

TIMER

GND

SENSE1

GATE2

GATE1

CC2

TRIP

POINT:

IN1

3.3V

IN2

2.5V

OUT1

3.3V
2.5A

OUT2

2.5V
2.5A

P RESET

LTC1645

(14-LEAD)

COMP

COMPOUT

SENSE2

1645 F15

RESET

1.18k
1%

4.99k
1%

10k

1.37k
1%

1.82k
1%

Dual Supply Hot Swap with Tracking Outputs

TYPICAL APPLICATIO

Part Number LTC1645