1
LTC1595/LTC1596/LTC1596-1
Serial 16-Bit
Multiplying DACs
FEATURES
s
SO-8 Package (LTC1595)
s
DNL and INL: 1LSB Max
s
Low Glitch Impulse: 1nV-s Typ
s
Fast Settling to 1LSB: 2
µ
s (with LT1468)
s
Pin Compatible with Industry Standard
12-Bit DACs: DAC8043 and DAC8143/AD7543
s
4-Quadrant Multiplication
s
Low Supply Current: 10
µ
A Max
s
Power-On Reset
LTC1595/LTC1596: Resets to Zero Scale
LTC1596-1: Resets to Midscale
s
3-Wire SPI and MICROWIRE
TM
Compatible
Serial Interface
s
Daisy-Chain Serial Output (LTC1596)
s
Asynchronous Clear Input
LTC1596: Clears to Zero Scale
LTC1596-1: Clears to Midscale
DESCRIPTIO
N
U
The LTC
®
1595/LTC1596/LTC1596-1 are serial input,
16-bit multiplying current output DACs. The LTC1595 is
pin and hardware compatible with the 12-bit DAC8043 and
comes in 8-pin PDIP and SO packages. The LTC1596 is pin
and hardware compatible with the 12-bit DAC8143/AD7543
and comes in 16-pin PDIP and SO wide packages.
Both are specified over the industrial temperature range.
Sensitivity of INL to op amp V
OS
is reduced by five times
compared to the industry standard 12-bit DACs, so most
systems can be easily upgraded to true 16-bit resolution
and linearity without requiring more precise op amps.
These DACs include an internal deglitching circuit that
reduces the glitch impulse by more than ten times to less
than 1nV-s typ.
The DACs have a clear input and a power-on reset. The
LTC1595 and LTC1596 reset to zero scale. The LTC1596-1
is a version of the LTC1596 that resets to midscale.
MICROWIRE is a trademark of National Semiconductor Corporation.
, LTC and LT are registered trademarks of Linear Technology Corporation.
V
DD
V
REF
LTC1595
R
FB
GND
4
7
6
5
8
5V
V
IN
CLOCK
DATA
LOAD
CLK
SRI
LD
1
2
3
OUT1
33pF
V
OUT
1595/96 TA01
+
LT
®
1468
DIGITAL INPUT CODE
0
1.0
INTEGRAL NONLINEARITY (LSB)
0.6
0.8
0.4
0.4
0.6
0.8
1.0
0.2
0.2
0
16384
32768
1595/96 TA02
49152
65535
Integral Nonlinearity
SO-8 Multiplying 16-Bit DAC Has Easy 3-Wire Serial Interface
APPLICATIO
N
S
U
s
Process Control and Industrial Automation
s
Software Controlled Gain Adjustment
s
Digitally Controlled Filter and Power Supplies
s
Automatic Test Equipment
TYPICAL APPLICATIO
N
U
2
LTC1595/LTC1596/LTC1596-1
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
V
DD
to AGND .............................................. 0.5V to 7V
V
DD
to DGND .............................................. 0.5V to 7V
AGND to DGND ............................................ V
DD
+ 0.5V
DGND to AGND ............................................. V
DD
+ 0.5V
V
REF
to AGND, DGND.............................................
±
25V
R
FB
to AGND, DGND ..............................................
±
25V
Digital Inputs to DGND ................ 0.5V to (V
DD
+ 0.5V)
W
U
U
PACKAGE/ORDER I FOR ATIO
V
OUT1
, V
OUT2
to AGND ................. 0.5V to (V
DD
+ 0.5V)
Maximum Junction Temperature .......................... 150
°
C
Operating Temperature Range
LTC1595C/LTC1596C/LTC1596-1C ........ 0
°
C to 70
°
C
LTC1595I/LTC1596I/LTC1596-1I ...... 40
°
C to 85
°
C
Storage Temperature Range ................ 65
°
C to 150
°
C
Lead Temperature (Soldering, 10 sec)................. 300
°
C
1
2
3
4
5
6
7
8
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC SO WIDE
N PACKAGE
16-LEAD PDIP
16
15
14
13
12
11
10
9
OUT1
OUT2
AGND
STB1
LD1
SRO
SRI
STB2
R
FB
V
REF
V
DD
CLR
DGND
STB4
STB3
LD2
T
JMAX
= 150
°
C,
JA
= 100
°
C/W (N)
T
JMAX
= 150
°
C,
JA
= 130
°
C/W (SW)
ORDER PART NUMBER
LTC1596-1AIN
LTC1596-1AISW
LTC1596-1BIN
LTC1596-1BISW
LTC1596-1CIN
LTC1596-1CISW
LTC1596-1ACN
LTC1596-1ACSW
LTC1596-1BCN
LTC1596-1BCSW
LTC1596-1CCN
LTC1596-1CCSW
LTC1596AIN
LTC1596AISW
LTC1596BIN
LTC1596BISW
LTC1596CIN
LTC1596CISW
LTC1596ACN
LTC1596ACSW
LTC1596BCN
LTC1596BCSW
LTC1596CCN
LTC1596CCSW
1
2
3
4
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
N8 PACKAGE
8-LEAD PDIP
8
7
6
5
V
REF
R
FB
OUT1
GND
V
DD
CLK
SRI
LD
T
JMAX
= 150
°
C,
JA
= 130
°
C/W (N)
T
JMAX
= 150
°
C,
JA
= 190
°
C/W (S)
ELECTRICAL CHARACTERISTICS
V
DD
= 5V
±
10%, V
REF
= 10V, V
OUT1
= V
OUT2
= AGND = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
LTC1595AIN8
LTC1595AIS8
LTC1595BIN8
LTC1595BIS8
LTC1595CIN8
LTC1595CIS8
LTC1595ACN8
LTC1595ACS8
LTC1595BCN8
LTC1595BCS8
LTC1595CCN8
LTC1595CCS8
ORDER PART NUMBER
S8 PART MARKING
1595A
1595B
1595C
1595AI
1595BI
1595CI
Consult factory for Military grade parts.
LTC1595C/96C/96-1C
LTC1595B/96B/96-1B
LTC1595A/96A/96-1A
(Note 1)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Accuracy
Resolution
q
16
16
16
Bits
Monotonicity
q
16
16
15
Bits
INL
Integral Nonlinearity
(Note 2) T
A
= 25
°
C
±
0.25
±
1
±
2
±
4
LSB
T
MIN
to T
MAX
q
±
0.35
±
1
±
2
±
4
LSB
3
LTC1595/LTC1596/LTC1596-1
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
DD
= 5V
±
10%, V
REF
= 10V, V
OUT1
= V
OUT2
= AGND = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gain Temperature Coefficient
(Note 4)
Gain/
Temperature
q
1
2
ppm/
°
C
I
LEAKAGE
OUT1 Leakage Current
(Note 5) T
A
= 25
°
C
±
3
nA
T
MIN
to T
MAX
q
±
15
nA
Zero-Scale Error
T
A
= 25
°
C
±
0.2
LSB
T
MIN
to T
MAX
q
±
1
LSB
PSRR
Power Supply Rejection
V
DD
= 5V
±
10%
q
±
1
±
2
LSB/V
Reference Input
R
REF
V
REF
Input Resistance
(Note 6)
q
5
7
10
k
AC Performance
Output Current Settling Time
(Notes 7, 8)
1
µ
s
Mid-Scale Glitch Impulse
Using LT1122 Op Amp, C
FEEDBACK
= 33pF
1
nV-s
Digital-to-Analog Glitch Impulse
Full-Scale Transition, V
REF
= 0V,
2
nV-s
Using LT1122 Op Amp, C
FEEDBACK
= 33pF
Multiplying Feedthrough Error
V
REF
=
±
10V, 10kHz Sine Wave
1
mV
P-P
THD
Total Harmonic Distortion
(Note 9)
108
dB
Equivalent DAC Thermal Noise
(Note 10) f = 1kHz
11
nV/
Hz
Voltage Density
Analog Outputs (Note 4)
C
OUT
Output Capacitance (Note 4)
DAC Register Loaded to All 1s
C
OUT1
q
115
130
pF
DAC Register Loaded to All 0s
C
OUT1
q
70
80
pF
Digital Inputs
V
IH
Digital Input High Voltage
q
2.4
V
V
IL
Digital Input Low Voltage
q
0.8
V
I
IN
Digital Input Current
q
0.001
±
1
µ
A
C
IN
Digital Input Capacitance
(Note 4) V
IN
= 0V
q
8
pF
Digital Outputs: SRO (LTC1596/LTC1596-1)
V
OH
Digital Output High Voltage
I
OH
= 200
µ
A
q
4
V
V
OL
Digital Output Low Voltage
I
OL
= 1.6mA
q
0.4
V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1595)
t
DS
Serial Input to CLK Setup Time
q
30
5
ns
t
DH
Serial Input to CLK Hold Time
q
30
5
ns
DNL
Differential
T
A
= 25
°
C
±
0.2
±
1
±
1
±
2
LSB
Nonlinearity
T
MIN
to T
MAX
q
±
0.2
±
1
±
1
±
2
LSB
GE
Gain Error
(Note 3) T
A
= 25
°
C
2
±
16
±
16
±
32
LSB
T
MIN
to T
MAX
q
3
±
16
±
32
±
32
LSB
LTC1595C/96C/96-1C
LTC1595B/96B/96-1B
LTC1595A/96A/96-1A
V
DD
= 5V
±
10%, V
REF
= 10V, V
OUT1
= V
OUT2
= AGND = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
V
DD
= 5V
±
10%, V
REF
= 10V, V
OUT1
= GND = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
4
LTC1595/LTC1596/LTC1596-1
ELECTRICAL CHARACTERISTICS
V
DD
= 5V
±
10%, V
REF
= 10V, V
OUT1
= V
OUT2
= AGND = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
±
1LSB =
±
0.0015% of full scale =
±
15.3ppm of full scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: I
OUT1
with DAC register loaded with all 0s.
Note 6: Typical temperature coefficient is 100ppm/C.
Note 7: OUT1 load = 100
in parallel with 13pF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
SRI
Serial Input Data Pulse Width
q
60
ns
t
CH
Clock Pulse Width High
q
60
ns
t
CL
Clock Pulse Width Low
q
60
ns
t
LD
Load Pulse Width
q
60
ns
t
ASB
LSB Clocked into Input Register
q
0
ns
to DAC Register Load Time
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1596/LTC1596-1)
t
DS1
Serial Input to Strobe Setup Time
STB1 Used as the Strobe
q
30
5
ns
t
DS2
STB2 Used as the Strobe
q
20
5
ns
t
DS3
STB3 Used as the Strobe
q
25
0
ns
t
DS4
STB4 Used as the Strobe
q
20
5
ns
t
DH1
Serial Input to Strobe Hold Time
STB1 Used as the Strobe
q
30
5
ns
t
DH2
STB2 Used as the Strobe
q
40
15
ns
t
DH3
STB3 Used as the Strobe
q
35
10
ns
t
DH4
STB4 Used as the Strobe
q
40
15
ns
t
SRI
Serial Input Data Pulse Width
q
60
ns
t
STB1
to
Strobe Pulse Width
(Note 11)
q
60
ns
t
STB4
t
STB1
to
Strobe Pulse Width
(Note 12)
q
60
ns
t
STB4
t
LD1,
t
LD2
LD Pulse Width
q
60
ns
t
ASB
LSB Strobed into Input Register
q
0
ns
to Load DAC Register Time
t
CLR
Clear Pulse Width
q
100
ns
t
PD1
STB1 to SRO Propagation Delay
C
L
= 50pF
q
30
150
ns
t
PD
STB2, STB3, STB4 to SRO
C
L
= 50pF
q
30
200
ns
Propagation Delay
Power Supply
V
DD
Supply Voltage
q
4.5
5
5.5
V
I
DD
Supply Current
Digital Inputs = 0V or V
DD
q
1.5
10
µ
A
Note 8: To 0.0015% for a full-scale change, measured from the falling
edge of LD1, LD2 or LD.
Note 9: V
REF
= 6V
RMS
at 1kHz. DAC register loaded with all 1s;
op amp = LT1007.
Note 10: Calculation from e
n
=
4kTRB where: k = Boltzmann constant
(J/
°
K); R = resistance (
); T = temperature (
°
K); B = bandwidth (Hz).
Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time
for STB3.
Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time
for STB3.
5
LTC1595/LTC1596/LTC1596-1
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
TIME (
µ
s)
0
1
2
3
4
OUTPUT VOLTAGE (mV)
0
1595/96 G01
10
+10
1nV-s TYP
USING LT1122 OP AMP
C
FEEDBACK
= 33pF
V
REF
= 10V
LD FALLING EDGE
Mid-Scale Glitch Inpulse
DIGITAL INPUT CODE
0
1.0
DIFFERENTIAL NONLINEARITY (LSB) 0.8
0.4
0.2
0
1.0
0.4
16384
32768
1595/96 G03
0.6
0.6
0.8
0.2
49152
65535
Integral Nonlinearity (INL)
Differential Nonlinearity (INL)
Differential Nonlinearity
vs Reference Voltage
Full-Scale Settling Waveform
DAC
OUTPUT
5V/DIV
GATED
SETTLING
WAVEFORM
500
µ
V/DIV
1
µ
s/DIV
1595/96 G04
REFERENCE VOLTAGE (V)
10
DIFFERENTIAL NONLINEARITY (LSB)
0.5
6
1595/96 G06
0
6
2
0
10
1.0
2
8
4
8
4
Integral Nonlinearity
vs Reference Voltage
REFERENCE VOLTAGE (V)
10
INTEGRAL NONLINEARITY (LSB)
0.5
6
1595/96 G05
0
6
2
0
10
1.0
2
8
4
8
4
Differential Nonlinearity
vs Supply Voltage
Multiplying Mode Frequency
Response vs Digital Code
FREQUENCY (Hz)
100
ATTENUATION (dB)
60
40
20
0
1M
1595/96 G07
80
100
120
1k
10k
100k
10M
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALL
BITS OFF
ALL
BITS
ON
USING LT1122 OP AMP
C
FEEDBACK
= 33pF
Integral Nonlinearity
vs Supply Voltage
SUPPLY VOLTAGE (V)
2
0
INTEGRAL NONLINEARITY (LSB)
1
2
4
6
7
1595/96 G08
3
5
8
9
10
V
REF
= 10V
V
REF
= 2.5V
SUPPLY VOLTAGE (V)
2
0
DIFFERENTIAL NONLINEARITY (LSB)
0.5
1.0
4
6
7
1595/96 G09
3
5
8
9
10
USING LT1122 OP AMP
C
FEEDBACK
= 33pF
DIGITAL INPUT CODE
0
1.0
INTEGRAL NONLINEARITY (LSB)
0.6
0.8
0.4
0.4
0.6
0.8
1.0
0.2
0.2
0
16384
32768
1595/96 TA02
49152
65535
6
LTC1595/LTC1596/LTC1596-1
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
PI
N
FU
N
CTIO
N
S
U
U
U
LTC1595
V
REF
(Pin 1): Reference Input.
R
FB
(Pin 2): Feedback Resistor. Normally tied to the output
of the current to voltage converter op amp.
OUT1 (Pin 3): Current Output Pin. Tie to inverting input of
current to voltage converter op amp.
GND (Pin 4): Ground Pin.
LD (Pin 5): The Serial Interface Load Control Input. When
LD is pulled low, data is loaded from the shift register into
the DAC register, updating the DAC output.
SRI (Pin 6): The Serial Data Input. Data on the SRI pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded MSB first.
CLK (Pin 7): The Serial Interface Clock Input.
V
DD
(Pin 8): The Positive Supply Input. 4.5V
V
DD
5.5V.
Requires a bypass capacitor to ground.
LTC1596/LTC1596-1
OUT1 (Pin 1): True Current Output Pin. Tie to inverting
input of current to voltage converter op amp.
OUT2 (Pin 2): Complement Current Output Pin. Tie to
analog ground.
AGND (Pin 3): Analog Ground Pin.
STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial
Interface Clock Inputs. STB1, STB2 and STB4 are rising
edge triggered inputs. STB3 is a falling edge triggered
input (see Truth Tables).
LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs.
When LD1 and LD2 are pulled low, data is loaded from the
shift register into the DAC register, updating the DAC
output (see Truth Tables).
SRO (Pin 6): The Output of the Shift Register. Becomes
valid on the active edge of the serial clock.
SRI (Pin 7): The Serial Data Input. Data on the SRI pin is
latched into the shift register on the active edge of the
serial clock. Data is loaded MSB first.
DGND (Pin 12): Digital Ground Pin.
CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to zero
scale when pulled low on LTC1596. Clears DAC to midscale
when pulled low on LTC1596-1. This pin should be tied to
V
DD
for normal operation.
V
DD
(Pin 14): The Positive Supply Input. 4.5V
V
DD
5.5V. Requires a bypass capacitor to ground.
V
REF
(Pin 15): Reference Input.
R
FB
(Pin 16): Feedback Resistor. Normally tied to the
output of the current to voltage converter op amp.
Supply Current
vs Logic Input Voltage
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
0.6
0.8
1.0
4
1595/96 G10
0.4
0.2
0.5
0.7
0.9
0.3
0.1
0
1
2
3
5
V
DD
= 5V
Logic Threshold
vs Supply Voltage
SUPPLY VOLTAGE (V)
0
LOGIC THRESHOLD (V)
1.0
2.0
3.0
0.5
1.5
2.5
1595/96 G11
10
0
5
1
6
2
7
3
8
4
9
7
LTC1595/LTC1596/LTC1596-1
SRI
LD
PREVIOUS
WORD
D15
MSB
D14
D1
1595 TD
D0
LSB
t
DS
t
DH
t
CH
t
SRI
t
ASB
t
CL
t
LD
CLK INPUT
TRUTH TABLES
Table 1. LTC1596/LTC1596-1 Input Register
CONTROL INPUTS
STB1 STB2 STB3 STB4
Input Register and SRO Operation
0
1
0
Serial Data Bit on SRI Loaded into Input
0
1
0
Register, MSB First
0
0
0
Data Bit or SRI Appears on SRO Pin
0
0
1
After 16 Clocked Bits
1
X
X
X
No Input Register Operation
X
1
X
X
No SRO Operation
X
X
0
X
X
X
X
1
Table 2. LTC1596/LTC1596-1 DAC Register
CONTROL INPUTS
CLR
LD1
LD2
DAC Register Operation
0
X
X
Reset DAC Register and Input Register to
All 0s (LTC1596) or to Midscale (LTC1596-1)
(Asynchronous Operation)
1
1
X
No DAC Register Operation
1
X
1
1
0
0
Load DAC Register with the Contents of Input
Register
TI I G DIAGRA
U
W
W
(LTC1595)
112k
7k
112k
56k
112k
56k
112k
56k
56k
56k
DECODER
D15
(MSB)
D13
D14
D12
D11
D0
(LSB)
CLK
IN
LOAD
V
DD
V
REF
R
FB
OUT1
GND
SRI
6
1595 BD
DAC REGISTER
56k
56k
56k
56k
INPUT 16-BIT SHIFT REGISTER
5
8
1
LD
7
CLK
4
3
2
· · ·
BLOCK DIAGRA
W
(LTC1595)
8
LTC1595/LTC1596/LTC1596-1
BLOCK DIAGRA
W
(LTC1596/LTC1596-1)
112k
7k
112k
56k
112k
56k
112k
56k
56k
56k
DECODER
D15
(MSB)
D13
D14
D12
D11
D0
(LSB)
CLR
CLK
OUT
CLR
SRO
IN
LOAD
DGND
V
DD
V
REF
R
FB
OUT1
OUT2
SRI
7
AGND
1596 BD
DAC REGISTER
56k
56k
56k
56k
INPUT 16-BIT SHIFT REGISTER
9
8
10
12
11
4
6
5
13
14
15
STB1
STB2
STB3
STB4
LD1
CLR
LD2
3
2
1
16
· · ·
TI I G DIAGRA
U
W
W
(LTC1596/LTC1596-1)
D15
MSB
D14
D13
D1
t
DS1
t
DS2
t
DS3
t
DS4
t
DH1
t
DH2
t
DH3
t
DH4
t
STB1
t
STB2
t
STB3
t
STB4
t
STB1
t
STB2
t
STB3
t
STB4
t
ASB
t
LD1
t
LD2
t
SRI
D0
LSB
t
PD
t
PD1
STROBE INPUT
STB1, STB2, STB4
(INVERT FOR STB3)
SRI
SRO
LD1, LD2
1596 TD
D15 (MSB)
PREVIOUS WORD
D14
PREVIOUS WORD
D0 (LSB)
PREVIOUS WORD
D15 (MSB)
CURRENT WORD
D13
PREVIOUS WORD
9
LTC1595/LTC1596/LTC1596-1
Description
The LTC1595/LTC1596 are 16-bit multiplying DACs which
have serial inputs and current outputs. They use precision
R/2R technology to provide exceptional linearity and
stability. The devices operate from a single 5V supply and
provide
±
10V reference input and voltage output ranges
when used with an external op amp. These devices have
a proprietary deglitcher that reduces glitch impulse to
1nV-s over a 0V to 10V output range.
Serial I/O
The LTC1595/LTC1596 have SPI/MICROWIRE compat-
ible serial ports that accept 16-bit serial words. Data is
accepted MSB first and loaded with a load pin.
The 8-pin LTC1595 has a 3-wire interface. Data is shifted
into the SRI data input on the rising edge of the CLK pin.
At the end of the data transfer, data is loaded into the DAC
register by pulling the LD pin low (see LTC1595 Timing
Diagram).
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
The 16-pin LTC1596 can operate in identical fashion to the
LTC1595 but offers additional pins for flexibility. Four
clock pins are available STB1, STB2, STB3 and STB4.
STB1, STB2 and STB4 operate like the CLK pin of the
LTC1595, capturing data on their rising edges. STB3
captures data on its falling edge (see Truth Table 1).
The LTC1596 has two load pins, LD1 and LD2. To load
data, both pins must be taken low. If one of the pins is
grounded, the other pin will operate identically to LTC1595's
LD pin. An asynchronous clear input (CLR) resets the
LTC1596 to zero scale (and the LTC1596-1 to midscale)
when pulled low (see Truth Table 2).
The LTC1596 also has a data output pin SRO that can be
connected to the SRI input of another DAC to daisy-chain
multiple DACs on one 3-wire interface (see LTC1596
Timing Diagram).
Unipolar (2-Quadrant Multiplying) Mode
(V
OUT
= 0V to V
REF
)
The LTC1595/LTC1596 can be used with a single op amp
to provide 2-quadrant multiplying operation as shown in
Figure 1. With a fixed 10V reference, the circuits shown
give a precision unipolar 0V to 10V output swing.
Figure 1. Unipolar Operation (2-Quadrant Multiplication) V
OUT
= 0V to V
REF
Table 1. Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
V
REF
(65,535/65,536)
V
REF
(32,768/65,536) = V
REF
/ 2
V
REF
(1/65,536)
0V
LSB
1111 1111 1111
0000 0000 0000
0000 0000 0001
0000 0000 0000
ANALOG OUTPUT
V
OUT
MSB
1111
1000
0000
0000
(b)
V
DD
V
REF
LTC1595
R
FB
GND
4
7
6
5
8
5V
V
REF
10V TO 10V
CLK
SRI
LD
1
2
3
OUT1
33pF
V
OUT
0V TO V
REF
1595/96 F01b
+
LT1001
µ
P
0.1
µ
F
(a)
V
DD
V
REF
LTC1596
R
FB
AGND
DGND
3
12
10
4
7
5
6
9
8
11
2
14
13
5V
V
REF
10V TO 10V
TO NEXT DAC
FOR DAISY-CHAINING
15
16
1
OUT1
33pF
0.1
µ
F
V
OUT
0V TO V
REF
1595/96 F01a
OUT2
+
LT1001
CLR
STB3
STB1
SRI
LD1
SRO
LD2
STB2
STB4
µ
P
10
LTC1595/LTC1596/LTC1596-1
Bipolar (4-Quadrant Multiplying) Mode
(V
OUT
= V
REF
to V
REF
)
The LTC1595/LTC1596 can be used with a dual op amp
and three external resistors to provide 4-quadrant multi-
plying operation as shown in Figure 2 (last page). With a
fixed 10V reference, the circuits shown give a precision
bipolar 10V to 10V output swing. Using the LTC1596-1
will cause the power-on reset and clear pin to reset the DAC
to midscale (bipolar zero).
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1595/LTC1596, thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Op amp offset will contribute mostly to output offset and
gain and will have minimal effect on INL and DNL. For
example, a 500
µ
V op amp offset will cause about 0.55LSB
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range. The main effects of op amp offset will be
a degradation of zero-scale error equal to the op amp
offset, and a degradation of full-scale error equal to twice
the op amp offset. For example, the same 500
µ
V op amp
offset will cause a 3.3LSB zero-scale error and a 6.5LSB
full-scale error with a 10V full-scale range.
Op amp input bias current (I
BIAS
) contributes only a zero-
scale error equal to I
BIAS
(R
FB
) = I
BIAS
(R
REF
) = I
BIAS
(7k).
Table 2 shows a selection of LTC op amps which are
suitable for use with the LTC1595/LTC1596. For a thor-
ough discussion of 16-bit DAC settling time and op amp
selection, refer to Application Note 74, "
Component and
Measurement Advances Ensure 16-Bit DAC Settling Time."
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding should be used. I
OUT2
(LTC1596) and GND
(LTC1595) must be tied to the star ground with as low a
resistance as possible.
Table 2. 16-Bit Settling Time for Various Amplifiers Driven by the LT1595 DAC. LT1468 (Shaded) Offers Fastest Settling Time While
Maintaining Accuracy Over Temperature
CONSERVATIVE SETTLING TIME
AMPLIFIER
AND COMPENSATION VALUE
COMMENTS
LT1001
120
µ
s
100pF
Good Low Speed Choice
LT1007
19
µ
s
100pF
I
B
Gives
1LSB Error at 25
°
C
LT1013
75
µ
s
150pF
1LSB Error Due to V
OS
over Temperature
LT1077
200
µ
s
100pF
LT1097
120
µ
s
75pF
Good Low Speed Choice
LT1112
120
µ
s
100pF
Good Low Speed Choice Dual
LT1178
450
µ
s
100pF
Low Power Dual
LT1468
2.5
µ
s
30pF
Fastest Settling with 16-Bit Performance
11
LTC1595/LTC1596/LTC1596-1
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
N8 1197
0.100
±
0.010
(2.540
±
0.254)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.130
±
0.005
(3.302
±
0.127)
0.020
(0.508)
MIN
0.018
±
0.003
(0.457
±
0.076)
0.125
(3.175)
MIN
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
1
2
3
4
8
7
6
5
0.255
±
0.015*
(6.477
±
0.381)
0.400*
(10.160)
MAX
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
1
2
3
4
0.150 0.157**
(3.810 3.988)
8
7
6
5
0.189 0.197*
(4.801 5.004)
0.228 0.244
(5.791 6.197)
0.016 0.050
0.406 1.270
0.010 0.020
(0.254 0.508)
×
45
°
0
°
8
°
TYP
0.008 0.010
(0.203 0.254)
SO8 0996
0.053 0.069
(1.346 1.752)
0.014 0.019
(0.355 0.483)
0.004 0.010
(0.101 0.254)
0.050
(1.270)
TYP
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
SW Package 16-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
N Package 16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
N16 1197
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
0.255
±
0.015*
(6.477
±
0.381)
0.770*
(19.558)
MAX
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.130
±
0.005
(3.302
±
0.127)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.018
±
0.003
(0.457
±
0.076)
0.100
±
0.010
(2.540
±
0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S16 (WIDE) 0396
NOTE 1
0.398 0.413*
(10.109 10.490)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.394 0.419
(10.007 10.643)
0.037 0.045
(0.940 1.143)
0.004 0.012
(0.102 0.305)
0.093 0.104
(2.362 2.642)
0.050
(1.270)
TYP
0.014 0.019
(0.356 0.482)
TYP
0
°
8
°
TYP
NOTE 1
0.009 0.013
(0.229 0.330)
0.016 0.050
(0.406 1.270)
0.291 0.299**
(7.391 7.595)
×
45
°
0.010 0.029
(0.254 0.737)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
12
LTC1595/LTC1596/LTC1596-1
©
LINEAR TECHNOLOGY CORPORATION 1997
159561fa LT/TP 0299 2K REV A · PRINTED IN USA
TYPICAL APPLICATIO
N
S
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
RELATED PARTS
Figure 2. Bipolar Operation (4-Quadrant Multiplication) V
OUT
= V
REF
to V
REF
V
DD
V
REF
LTC1596-1
R
FB
AGND
DGND
3
12
10
4
7
5
6
9
8
11
2
14
13
5V
V
REF
10V TO 10V
TO NEXT DAC
FOR DAISY-CHAINING
15
16
1
OUT1
33pF
R1
10k
(20k
÷
2)
R2
20k
R3
20k
0.1
µ
F
V
OUT
V
REF
TO V
REF
RESISTORS: CADDOCK T914-20K-010-02
(OR EQUIVALENT) 20k, 0.01%, TC TRACK = 2ppm/
°
C
1595/96 F02a
OUT2
+
1/2 LT1112
CLR
STB3
STB1
SRI
LD1
SRO
LD2
STB2
STB4
µ
P
+
1/2 LT1112
(a)
7
6
5
5V
µ
P
0.1
µ
F
V
DD
V
REF
LTC1595
R
FB
GND
4
8
V
REF
10V TO 10V
CLK
SRI
LD
1
2
3
OUT1
V
OUT
V
REF
TO
V
REF
1595/96 F02b
+
1/2 LT1112
R3
20k
R1
10k
(20k
÷
2)
R2
20k
+
1/2 LT1112
33pF
(b)
Table 3. Bipolar Offset Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
V
REF
(32,767/32,768)
V
REF
(1/32,768)
0V
V
REF
(1/32,768)
V
REF
LSB
1111 1111 1111
0000 0000 0001
0000 0000 0000
1111 1111 1111
0000 0000 0000
ANALOG OUTPUT
V
OUT
MSB
1111
1000
1000
0111
0000
PART NUMBER
DESCRIPTION
COMMENTS
DACs
LTC1590
Dual Serial I/O Multiplying I
OUT
12-Bit DAC
16-Pin SO and PDIP, SPI Interface
LTC1597
Parallel 16-Bit Current Output DAC
Low Glitch,
±
1LSB Maximum INL, DNL
LTC1650
Serial 16-Bit Voltage Output DAC
Low Noise and Glitch Rail-to-Rail V
OUT
LTC1658
Serial 14-Bit Voltage Output DAC
Low Power, 8-Lead MSOP Rail-to-Rail V
OUT
LTC7543/LTC8143/LTC8043
Serial I/O Multiplying I
OUT
12-Bit DACs
Clear Pin and Serial Data Output (LTC8143)
ADCs
LTC1418
14-Bit, 200ksps 5V Sampling ADC
16mW Dissipation, Serial and Parallel Outputs
LTC1604
16-Bit, 333ksps Sampling ADC
±
2.5V Input, SINAD = 90dB, THD = 100dB
LTC1605
Single 5V, 16-Bit 100ksps ADC
Low Power,
±
10V Inputs
LTC2400
24-Bit,
ADC in SO-8
1ppm (4ppm) Offset (Full Scale), Internal 50Hz/60Hz Notches
Op Amps
LT1001
Precision Operational Amplifier
Low Offset, Low Drift
LT1112
Dual Low Power, Precision Picoamp Input Op Amp
Low Offset, Low Drift
LT1468
90MHz, 22V/
µ
s, 16-Bit Accurate Op Amp
Precise, 1
µ
s Settling to 0.0015%
References
LT1236
Precision Reference
Ultralow Drift, 5ppm/
°
C, High Accuracy 0.05%
LT1634
Micropower Reference
Ultralow Drift, 10ppm/
°
C, High Accuracy 0.05%
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