LTC1555/LTC1556

SIM Power Supply

and Level Translator

FEATURES

Step-Up/Step-Down Charge Pump Generates 5V

Input Voltage Range: 2.7V to 10V

Output Current: 10mA (V

2.7V)

20mA (V

3V)

3V to 5V Signal Level Translators

> 10kV ESD on All SIM Contact Pins

Short-Circuit and Overtemperature Protected

Very Low Operating Current: 60

Very Low Shutdown Current: < 1

Soft Start Limits Inrush Current at Turn-On

Programmable 3V or 5V Output Voltage

650kHz Switching Frequency

Auxiliary 4.3V LDO/Power Switch (LTC1556 Only)

Available in a 16- and 20-Pin Narrow SSOP

DESCRIPTIO

The LTC

1555/LTC1556 provide power conversion and

level shifting needed for 3V GSM cellular telephones to
interface with either 3V or 5V Subscriber Identity Mod-
ules (SIMs). These parts contain a charge pump DC/DC
converter that delivers a regulated 5V to the SIM card.
Input voltage may range from 2.7V to 10V, allowing
direct connection to the battery. Output voltage may be
programmed to 3V, 5V or direct connection to the V

pin.

A soft start feature limits inrush current at turn-on,
mitigating start-up problems that may result when the
input is supplied by another low power DC/DC converter.
The LTC1556 also includes an auxiliary LDO regulator/
power switch that may be used to power the frequency
synthesizer or other low power circuitry.

Battery life is maximized by 60

A operating current and

A shutdown current. Board area is minimized by minia-

ture 16- and 20-pin narrow SSOP packages and the need
for only three small external capacitors.

TYPICAL APPLICATIO

GSM Cellular Telephone SIM Interface

CIN

RIN

DATA

DDRV

CLK

RST

I/O

VCC

10mA

GND

CLK

RST

I/O

GND

0.1

LTC1555

3V GSM

CONTROLLER

SIM

2.7V TO 10V

1555/56 TA01

, LTC and LT are registered trademarks of Linear Technology Corporation.

SIM Interface in GSM Cellular Telephones

Smart Card Readers

APPLICATIO

LTC1555/LTC1556

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Voltage

2.7

Operating Voltage

1.8

5.5

Operating Current

2.7V

5V, V

= 5V, I

VCC

= 0

100

5V < V

10V, V

= 5V, I

VCC

= 0

135

Shutdown Current

M0, M1 = 0V, 2.7V

M0, M1 = 0V, 5V < V

10V

Operating Current

M0, M1 = DV

, C

= 1MHz

Shutdown Current

M0, M1 = 0V

Output Voltage

VCC

10mA, 2.7V

10V

VCC

20mA, 3V

10V

M0, M1 = DV

4.75

5.00

5.25

M0 = DV

, M1 = 0

2.80

3.00

3.20

M0 = 0, M1 = DV

0.3

Output Ripple

= 3.6V, I

VCC

= 10mA, V

= 5V

P-P

ABSOLUTE

AXI

RATINGS

(Note 1)

, DV

to GND ..................................... 0.3V to 12V

to GND ............................................... 0.3V to 12V

Digital Inputs to GND ................................ 0.3V to 12V
LDO, CLK, RST, I/O to GND ........ 0.3V to (V

+ 0.3V)

, LDO Short-Circuit Duration ..................... Indefinite

Storage Temperature Range ................. 65

C to 150

Temperature Range

LTC1555C/LTC1556C .............................. 0

C to 70

LTC1555I/LTC1556I ........................... 40

C to 85

Extended Commercial Operating Temperature Range

(Note 2) ............................................. 40

C to 85

Lead Temperature (Soldering, 10 sec) .................. 300

PACKAGE/ORDER I

FOR

ATIO

Consult factory for Military grade parts.

ORDER PART

NUMBER

LTC1556CGN
LTC1556IGN

ORDER PART

NUMBER

LTC1555CGN
LTC1555IGN

JMAX

= 150

= 135

C/ W

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

CIN

RIN

DATA

DDRV

CLK

RST

I/O

GND

TOP VIEW

GN PACKAGE

20-LEAD PLASTIC SSOP

CIN

RIN

DATA

DDRV

CLK

RST

I/O

LDO

GND

JMAX

= 150

= 95

C/ W

ELECTRICAL CHARACTERISTICS

= 2.7V to 10V, DV

= 1.8V to 5.5V, controller digital pins tied to DV

, SIM digital pins floating, EN, FB pins tied to GND

(LTC1556), C1 = 0.1

F, C

OUT

= 10

F unless otherwise specified.

LTC1555/LTC1556

= 2.7V to 10V, DV

= 1.8V to 5.5V, controller digital pins tied to DV

, SIM digital pins floating, EN, FB pins tied to GND

(LTC1556), C1 = 0.1

F, C

OUT

= 10

F unless otherwise specified.

ELECTRICAL CHARACTERISTICS

over the 40

C to 85

C temperature range by design or correlation, but

are not production tested.

Note 3: The DATA and I/O pull-down drivers must also sink current
sourced by the internal pull-up resistors.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Short-Circuit Current

Shorted to GND

12.5

Auxiliary LDO V

OUT

LDO

)

EN = High, V

= 5V, FB = LDO, I

LDO

= 5mA (LTC1556)

4.00

4.3

4.55

Auxiliary Switch Resistance

EN = High, V

= 5V, FB = GND (LTC1556)

FB Input Resistance

(LTC1556)

200

Charge Pump f

OSC

500

650

800

kHz

Controller Inputs/Outputs, DV

= 3V

Input Current (I

, I

)

M0, M1, SS, RIN, CIN

DDRV, EN

High Level Input Current (I

)

DATA

Low Level Input Current (I

)

DATA

High Input Voltage Threshold (V

)

M0, M1, RIN, CIN, DDRV, EN

0.7

DATA

0.6

Low Input Voltage Threshold (V

)

M0, M1, RIN, CIN, DDRV, EN

0.2

DATA

0.4

High Level Output Voltage (V

)

DATA Source Current = 20

A, I/O = V

0.7

Low Level Output Voltage (V

)

DATA Sink Current = 200

A, I/O = 0V (Note 3)

0.4

DATA Pull-up Resistance

Between DATA and DV

DATA Output Rise/Fall Time

DATA Loaded with 30pF

1.3

SIM Inputs/Outputs, DV

= 3V, V

= 3V or 5V

I/O High Input Voltage Threshold (V

)

IH(MAX)

0.5

0.7

I/O Low Input Voltage Threshold (V

)

IL(MAX)

= 1mA

0.4

High Level Output Voltage (V

)

I/O, Source Current = 20

A, DATA or DDRV = DV

0.8

RST, CLK, Source Current = 20

0.9

Low Level Output Voltage (V

)

I/O, Sink Current = 1mA, DATA or DDRV = 0V (Note 3)

0.4

RST, CLK, Sink Current = 200

0.4

I/O Pull-Up Resistance

Between I/O and V

6.5

SIM Timing Parameters, DV

= 3V, V

= 5V

CLK Rise/Fall Time

CLK Loaded with 30pF

RST, I/O Rise/Fall Time

RST, I/O Loaded with 30pF

CLK Frequency

CLK Loaded with 30pF

MHz

Turn-On Time

SS = DV

, C

OUT

= 10

F, I

VCC

= 0

SS = 0V, C

OUT

= 10

F, I

VCC

= 0

Discharge Time to 1V

VCC

= 0, V

= 5V, C

OUT

= 10

The

denotes specifications which apply over the specified temperature

range.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: C grade device specifications are guaranteed over the 0

C to 70

temperature range. In addition, C grade device specifications are assured

LTC1555/LTC1556

TYPICAL PERFOR

CE CHARACTERISTICS

INPUT VOLTAGE (V)

OPERATING CURRENT (

100

1555/56 G01

120

NO EXTERNAL LOAD

Operating Current
vs Input Voltage

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

5.0

5.1

1555/56 G03

4.9

4.8

5.2

VCC

= 10mA

M0 = DV

M1 = DV

OUT

= 10

= 25

INPUT VOLTAGE (V)

SHUTDOWN CURRENT (

1555/56 G02

Shutdown Current
vs Input Voltage

Output Voltage

vs Input Voltage (5V Mode)

Output Voltage

vs Input Voltage (3V Mode)

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

3.0

3.1

1555/56 G04

2.9

2.8

3.2

VCC

= 10mA

M0 = DV

M1 = 0V
C

OUT

= 10

= 25

1V/DIV

1ms/DIV

1555/56 G05

= 3V

SS = 0V

1V/DIV

1ms/DIV

= 3V

SS = DV

1555/56 G06

Output Voltage Turn-On Time,

SS Enabled

Output Voltage Turn-On Time,

SS Disabled

5V V

Efficiency vs Input Voltage

INPUT VOLTAGE (V)

EFFICIENCY (%)

100

1555/56 G08

= 5V

VCC

= 10mA

= 25

3V V

Efficiency vs Input Voltage

INPUT VOLTAGE (V)

EFFICIENCY (%)

100

1555/56 G07

= 3V

VCC

= 10mA

= 25

LTC1555/LTC1556

LTC1555/LTC1556

CIN (Pin 1): Clock Input Pin from Controller.

RIN (Pin 2): Reset Input Pin from Controller.

DATA (Pin 3): Controller Side Data Input/Output Pin. Can
be used for single pin bidirectional data transfer between
the controller and the SIM card as long as the controller
data pin is open drain. The controller output must be able
to sink 1mA max when driving the DATA pin low due to
the internal pull-up resistors on the DATA and I/O pins. If
the controller data output is not open drain, then the
DDRV pin should be used for sending data to the SIM
card and the DATA pin used for receiving data from the
SIM card (see Figure 1).

DDRV (Pin 4): Optional Data Input Pin for Sending Data
to the SIM card. When not needed, the DDRV pin should
be left floating or tied to DV

(an internal 1

A current

source will pull the DDRV pin up to DV

if left floating).

(Pins 5/7): Supply Voltage for Controller Side Digital

I/O Pins. May be between 1.8V and 5.5V (typically 3V).

SS (Pins 6/8): Soft Start Enable Pin. A logic low will
enable the charge pump inrush current limiting feature.
A logic high will disable the soft start feature and allow
V

to be ramped as quickly as possible upon start-up

and coming out of shutdown.

M1 (Pins 7/9): Mode Control Bit 1 (see Truth Table).

M0 (Pins 8/10): Mode Control Bit 0 (see Truth Table).

This table defines the various operating modes that may
be obtained via the M0 and M1 mode control pins.

Truth Table

MODE

Shutdown (V

= 0V)

= V

= 3V

= 5V

GND (Pins 9/11, 12): Ground for Both the SIM and the
Controller. Should be connected to the SIM GND contact
as well as to the V

/Controller GND. Proper grounding

and supply bypassing is required to meet 10kV ESD
specifications.

(Pins 10/12): Charge Pump Flying Capacitor Nega-

tive Input.

(Pins 11/13): Charge Pump Flying Capacitor Positive

Input.

(Pins 12/14): Charge Pump Input Voltage Pin. Input

voltage range is 2.7V to 10V. Connect a 10

F low ESR

input bypass capacitor close to the V

pin.

(Pins 13/15): SIM Card V

Output. This pin should

be connected to the SIM V

contact. The V

output

voltage is determined by the M0 and M1 pins (see Truth
Table). V

is discharged to GND during shutdown

(M0, M1 = 0V). A 10

F low ESR output capacitor should

connect close to the V

pin.

I/O (Pins 14/18): SIM Side I/O Pin. The pin is an open
drain output with a nominal pull-up resistance of 10k and
should be connected to the SIM I/O contact. The SIM card
must sink up to 1mA max when driving the I/O pin low
due to the internal pull-up resistors on the I/O and DATA
pins. The I/O pin is held active low when the part is in
shutdown.

RST (Pins 15/19): Level Shifted Reset Output Pin. Should
be connected to the SIM RST contact.

CLK (Pins 16/20): Level Shifted Clock Output Pin. Should
be connected to the SIM CLK contact. Careful trace
routing is recommended due to fast rise and fall edge
speeds.

CTIO

LTC1555/LTC1556

CTIO

LTC1556 Only

EN (Pin 5): Auxiliary LDO/Power Switch Enable Pin. A
logic high on this pin from the controller will enable the
auxiliary LDO output. When the LDO is disabled, the LDO
output will float or be pulled to ground by the load. If left
floating, the EN pin will be pulled down to GND by an
internal 1

A current source.

FB (Pin 6): Auxiliary LDO Feedback Pin. When FB is
connected to the LDO pin (Pin 17), the LDO output is
regulated to 4.3V (typ). If the FB pin is left open or tied to

BLOCK DIAGRA

ground, the regulator acts as a

switch between V

and LDO.

LDO (Pin 17): LDO Output Pin. This pin should be tied to
the FB pin for 4.3V LDO operation. The 4.3V LDO output
is usable only when V

is 5V (or greater). It is not

available when V

= 3V. The LDO output may also be

used as a

power switch if the FB pin is grounded

or left floating. When used as a regulator, LDO must be
bypassed to GND with a

3.3

F capacitor. The LDO

output current will subtract from available V

current.

1.23V

61k

153k

1555/56 BD

DDRV

OPTIONAL

LDO

I/O

FREQUENCY
SYNTHESIZER
POWER

LTC1555/LTC1556

LTC1556 ONLY

4.3V

DATA

20k

10k

CLK

CIN

RST

RIN

GND

BATT

I/O

CLK

RST

GND

0.1

GND

STEP-UP/

STEP-DOWN

CHARGE PUMP

DC/DC

CONVERTER

SIM

CONTROLLER

OUT

LDO

LTC1555/LTC1556

The LTC1555/LTC1556 perform the two primary func-
tions necessary for 3V controllers (e.g., GSM cellular
telephone controllers, smart card readers, etc.) to com-
municate with 5V SIMs or smart cards. They produce a
regulated 5V V

supply for the SIM and provide level

translators for communication between the SIM and the
controller.

Voltage Regulator

The regulator section of the LTC1555/LTC1556 (refer to
the Block Diagram) consists of a step-up/step-down charge
pump DC/DC converter. The charge pump can operate
over a wide input voltage range (2.7V to 10V) while
maintaining a regulated V

output. The wide V

range

enables the parts to be powered directly from a battery (if
desired) rather than from a 3V DC/DC converter output.
When V

is less than the desired V

the parts operate as

switched capacitor voltage doublers. When V

is greater

than V

the parts operate as gated switch step-down

converters. In either case, voltage conversion requires
only one small flying capacitor and output capacitor.

The V

output can be programmed to either 5V or 3V via

the M0 and M1 mode pins. This feature is useful in
applications where either a 5V or 3V SIM may be used. The
charge pump V

output may also be connected directly to

if desired. When the charge pump is put into shutdown

(M0, M1 = 0), V

is pulled to GND via an internal switch

to aid in proper system supply sequencing.

The soft start feature limits inrush currents upon start-up
or coming out of shutdown mode. When the SS pin is tied
to GND, the soft start feature is enabled. This limits the ef-
fective inrush current out of V

to approximately 25mA

OUT

= 10

F). Inrush current limiting is especially useful

when powering the LTC1555/LTC1556 from a 3V DC/DC
output since the unlimited inrush current may approach
200mA and cause voltage transients on the 3V supply. How-
ever, in cases where fast turn-on time is desired, the soft
start feature may be overridden by tying the SS pin to DV

APPLICATIO

S I

FOR

ATIO

Capacitor Selection

For best performance, it is recommended that low ESR
(< 0.5

) capacitors be used for both C

and C

OUT

to reduce

noise and ripple. The C

and C

OUT

capacitors should be

either ceramic or tantalum and should be 10

F or greater

(ceramic capacitors will produce the smallest output ripple).
If the input source impedance is very low (< 0.5

), C

may

not be needed. Increasing the size of C

OUT

to 22

F or greater

will reduce output voltage ripple--particularly with high V

voltages (8V or greater). A ceramic capacitor is recom-
mended for the flying capacitor C1 with a value of 0.1

F or

0.22

Output Ripple

Normal LTC1555/LTC1556 operation produces voltage
ripple on the V

pin. Output voltage ripple is required for

the parts to regulate. Low frequency ripple exists due to
the hysteresis in the sense comparator and propagation
delays in the charge pump enable/disable circuits. High
frequency ripple is also present mainly from the ESR
(equivalent series resistance) in the output capacitor.
Typical output ripple (V

< 8V) under maximum load is

75mV peak-to-peak with a low ESR, 10

F output capaci-

tor. For applications requiring V

to exceed 8V, a 22

F or

larger C

OUT

capacitor is recommended to maintain maxi-

mum ripple in the 75mV range.

The magnitude of the ripple voltage depends on several
factors. High input voltages increase the output ripple
since more charge is delivered to C

OUT

per charging cycle.

A large C1 flying capacitor (> 0.22

F) also increases ripple

in step-up mode for the same reason. Large output current
load and/or a small output capacitor (< 10

F) results in

higher ripple due to higher output voltage dV/dt. High ESR
capacitors (ESR > 0.5

) on the output pin cause high

frequency voltage spikes on V

OUT

with every clock cycle.

A 10

F ceramic capacitor on the V

pin should produce

acceptable levels of output voltage ripple in nearly all
applications. However, there are several ways to further

LTC1555/LTC1556

APPLICATIO

S I

FOR

ATIO

reduce the ripple. A larger C

OUT

capacitor (22

F or greater)

will reduce both the low and high frequency ripple due to
the lower C

OUT

charging and discharging dV/dt and the

lower ESR typically found with higher value (larger case
size) capacitors. A low ESR ceramic output capacitor will
minimize the high frequency ripple, but will not reduce the
low frequency ripple unless a high capacitance value is
chosen (10

F or greater). A reasonable compromise is to

use a 10

F to 22

F tantalum capacitor in parallel with a 1

to 3.3

F ceramic capacitor on V

OUT

to reduce both the low

and high frequency ripple. An RC filter may also be used
to reduce high frequency voltage spikes (see Figure 1).

hundred milliseconds to completely shut down. To ensure
prompt and proper V

shutdown, always force the M0

and M1 pins to a logic low state before shutting down the
DV

supply (see Figure 2). Similarly, bring the DV

supply to a valid level before allowing the M0 and M1 pins
to go high when coming out of shutdown. This can be
achieved with pull-down resistors from M0 and M1 to
GND if necessary. (Note: shutting down the DV

supply

with V

active is not recommended with early date code

material. Consult factory for valid date code starting point
for shutting down the DV

supply.)

Level Translators

All SIMs and smart cards contain a clock input, reset input
and a bidirectional data input/output. The LTC1555/
LTC1556 provide level translators to allow controllers to
communicate with the SIM (see Figures 3a and 3b). The
CLK and RST inputs to the SIM are level shifted from the
controller supply rails (DV

and GND) to the SIM supply

rails (V

and GND). The data input to the SIM may be

provided two different ways. The first method is to use the
DATA pin as a bidirectional level translator. This configu-
ration is only allowed if the controller data output pin is
open drain (all SIM I/O pins are open drain). Internal pull-
up resistors are provided for both the DATA pin and the

Figure 3b. Level Translator Connections for
One-Directional Controller Side DATA Flow

CIN

RIN

DATA

DDRV

CLK

RST

I/O

CLK TO SIM

RST TO SIM

DATA FROM SIM

DATA TO SIM

LTC1555/LTC1556

CONTROLLER

SIDE

SIM SIDE

1555/56 F3b

Figure 3a. Level Translator Connections for
Bidirectional Controller DATA Pin

CIN

RIN

DATA

DDRV

CLK

RST

I/O

CLK TO SIM

RST TO SIM

DATA TO/FROM SIM

LTC1555/LTC1556

CONTROLLER

SIDE

SIM SIDE

1555/56 F3a

Figure 2. Recommended DV

Shutdown and Start-Up Timing

1555/56 F02

Shutting Down the DV

Supply

To conserve power, the DV

supply may be shut down

while the V

supply is still active. When the DV

supply

is brought to 0V, weak internal currents will force the
LTC1555/LTC1556 into shutdown mode regardless of the
voltages present on the M0 and M1 pins. However, if the
M0 and M1 pins are floating or left connected to DV

the supply is shut down, the parts may take several

Figure 1. V

Output Ripple Reduction Techniques

TANTALUM

LT1555/56 F01

SIM
V

CERAMIC

LTC1555/

LTC1556

LTC1555/LTC1556

I/O pin on the SIM side. The second method is to use the
DDRV pin to send data to the SIM and use the DATA pin to
receive data from the SIM. When the DDRV pin is not used,
it should either be left floating or tied to DV

Level Translation with DV

> V

It is assumed that most applications for these parts will
use controller supply voltages (DV

) less than or equal

to V

. In cases where DV

is greater than V

by more

than 0.6V or so, the parts' operation will be affected in the
following ways: 1) A small DC current (up to 100

A) will

flow from DV

to V

through the DATA pull-up resistor,

N-channel pass device and the I/O pull-up resistor
(except when the part is in shutdown at which time DV

is disconnected from V

by turning off the pass device).

If the V

load current is less than the DV

current, the

output may be pulled out of regulation until sufficient

load current pulls V

back into regulation. 2) When the

SIM is sending data back to the controller, a logic high on
the I/O pin will result in the DATA pin being pulled up to
[V

+ 1/3(DV

)], not all the way up to DV

. For

example, if DV

is 5V and V

is 3V, the DATA pin will

only swing from

0.1V to 3.67V when receiving data

from the SIM side.

Optional LDO Output

The LTC1556 also contains an internal LDO regulator for
providing a low noise boosted supply voltage for low power
external circuitry (e.g., frequency synthesizers, etc.) Tying
the FB pin to the LDO pin provides a regulated 4.3V at the
LDO output (see Figure 4). A 3.3

F (minimum) capacitor is

APPLICATIO

S I

FOR

ATIO

required to ensure output stability. A 10

F low ESR capaci-

tor is recommended, however, to minimize LDO output
noise. The LDO output may also be used as an auxiliary
switch to V

. If the FB pin is left floating or is tied to GND,

the LDO pin will be internally connected to the V

output

through the P-channel pass device. The LDO may be dis-
abled at any time by switching the EN pin from DV

to GND.

The 4.3V LDO output is usable only when V

is 5V (or

greater). It is not available when V

= 3V.

Figure 4. Auxiliary LDO Connections (LTC1556 Only)

REF

61k

= 5V

LDO

OFF ON

TANT

4.3V

1555/56 F04

LDO

0mA to
10mA

FB 153k

10kV ESD Protection

All pins that connect to the SIM (CLK, RST, I/O, V

, GND)

withstand over 10kV of human body model (100pF/1.5k

)

ESD. In order to ensure proper ESD protection, careful
board layout is required. The GND pins should be tied
directly to a GND plane. The V

capacitor should be

located very close to the V

pin and tied immediately to

the GND plane.

LTC1555/LTC1556

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

20-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.337 0.344*

(8.560 8.737)

GN20 (SSOP) 1197

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

9 10

0.229 0.244

(5.817 6.198)

0.150 0.157**

(3.810 3.988)

15 14 13 12 11

0.016 0.050

(0.406 1.270)

0.015

0.004

(0.38

0.10)

TYP

0.007 0.0098

(0.178 0.249)

0.053 0.068

(1.351 1.727)

0.008 0.012

(0.203 0.305)

0.004 0.0098

(0.102 0.249)

0.025

(0.635)

BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1555/LTC1556

15556f LT/TP 0398 4K ˇ PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1997

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

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RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1514-3.3/LTC1514-5

Regulated Step-Up/Step-Down Charge Pumps with Low Bat Comparator 3.3V and 5V Output Versions

LTC1515 Series

Regulated Step-Up/Step-Down Charge Pumps with Reset Output

Adjustable, 3V/5V, 3.3V/5V Versions

LTC1516

Micropower, Regulated 5V Charge Pump DC/DC Converter

OUT

= 20mA (V

2V), I

OUT

= 50mA (V

3V)

LTC1517-5

Micropower, Regulated 5V Charge Pump DC/DC Converter

LTC1522 Without Shutdown and
Packaged in SOT-23

LTC1522

Micropower, Regulated 5V Charge Pump DC/DC Converter

OUT

= 20mA (V

3V), I

= 6

LTC1550-4.1

Low Noise, Charge Pump Voltage Inverter

1mV

P-P

Ripple at 900kHz

LTC660

100mA Charge Pump DC/DC Converter

5V to 5V at 100mA

CIN

RIN

DATA

DDRV

CLK

RST

I/O

VCC

10mA

CLK

RST

I/O

LDO

GND

0.1

LTC1556

3V GSM

CONTROLLER

SIM

2.7V TO 10V

1555/56 TA02

GND

4.3V
50mA
AUXILIARY LDO/POWER SWITCH
(FREQUENCY SYNTHESIZER)

TYPICAL APPLICATIO

SIM Interface with Auxilary Power

Part Number LTC1556