1
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail
Micropower DACs
DESCRIPTIO
N
U
Daisy-Chained Control Outputs
FEATURES
The LTC
®
1458/LTC1458L are complete single supply,
quad rail-to-rail voltage output, 12-bit digital-to-analog
converters (DACs) in SO-28 and SSOP-28 packages. They
include an output buffer amplifier with variable gain (
×
1 or
×
2) and an easy-to-use 3-wire cascadable serial interface.
The LTC1458 has an onboard reference of 2.048V and a
full-scale output of 4.095V in a
×
2 gain configuration. It
operates from a single 4.5V to 5.5V supply dissipating
only 5.5mW (I
CC
= 1.1mA typ).
The LTC1458L has an onboard 1.22V reference and a full-
scale output of 2.5V in a
×
2 gain configuration. It operates
from a single supply of 2.7V to 5.5V dissipating 2.4mW.
Excellent DNL, low supply current and a wide range of
built-in functions allow these parts to be used in a host of
applications when flexibility, power and single supply
operation are important.
TYPICAL APPLICATIO
N
U
s
12-Bit Resolution
s
Buffered True Rail-to-Rail Voltage Output
s
5V Operation, I
CC
: 1.1mA Typ (LTC1458)
s
3V Operation, I
CC
: 800
µ
A Typ (LTC1458L)
s
Built-In Reference: 2.048V (LTC1458)
1.220V (LTC1458L)
s
CLR Pin
s
Power-On Reset
s
SSOP-28 Package
s
3-Wire Cascadable Serial Interface
s
Maximum DNL Error: 0.5LSB
s
Low Cost
Functional Block Diagram: Quad 12-Bit Rail-to-Rail DAC
Differential Nonlinearity
vs Input Code
s
Digital Calibration
s
Industrial Process Control
s
Automatic Test Equipment
s
Low Power Systems
APPLICATIO
N
S
U
1458 BD01
48-BIT
SHIFT REGISTER
AND
DAC REGISTER
CLK
D
IN
5V (LTC1458)
3V TO 5V (LTC1458L)
2.048V (LTC1458)
1.22V (LTC1458L)
REFHI C
REFOUT
V
OUT C
V
CC
REFLO C
X1/X2 C
X1/X2 D
X1/X2 A
X1/X2 B
REFHI D
V
OUT D
REFLO D
REFHI B
FROM
µ
P
V
OUT B
REFLO B
REFHI A
V
OUT A
REFLO A
D
OUT
CS/LD
CLR
DAC D
DAC C
DAC B
DAC A
CODE
0
DNL (LSB)
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
1024
2048 2560
1458 G09
512
1536
3072 3584 4095
, LTC and LT are registered trademarks of Linear Technology Corporation.
2
LTC1458/LTC1458L
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
W
U
U
PACKAGE/ORDER I FOR ATIO
V
CC
to GND .............................................. 0.5V to 7.5V
Logic Inputs to GND ................................ 0.5V to 7.5V
V
OUT A
, V
OUT B
, V
OUT C
, V
OUT D
,
X1/X2 A , X1/X2 B, X1/X2 C,
X1/X2 D ......................................... 0.5V to V
CC
+ 0.5V
REFHI A , REFHI B, REFHI C, REFHI D,
REFLO A , REFLO B, REFLO C,
REFLO D ........................................ 0.5V to V
CC
+ 0.5V
Maximum Junction Temperature ......................... 125
°
C
Operating Temperature Range
LTC1458C/LTC1458LC .......................... 0
°
C to 70
°
C
LTC1458I/LTC1458LI ...................... 40
°
C to 85
°
C
Storage Temperature Range ................ 65
°
C to 150
°
C
Lead Temperature (Soldering, 10 sec) ................. 300
°
C
ELECTRICAL CHARACTERISTICS
ORDER PART
NUMBER
V
CC
= 4.5V to 5.5V (LTC1458), 2.7V to 5.5V (LTC1458L), X1/X2 = REFLO = GND, REFHI = REFOUT, V
OUT
unloaded, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
X1/X2 B
V
OUT B
CLR
REFHI B
GND
REFLO B
REFLO A
REFHI A
REFOUT
NC
V
OUT A
X1/X2 A
V
CC
X1/X2 C
V
OUT C
CS/LD
D
IN
REFHI C
GND
REFLO C
REFLO D
REFHI D
D
OUT
CLK
NC
V
OUT D
X1/X2 D
SW PACKAGE
28-LEAD PLASTIC SO WIDE
T
JMAX
= 125
°
C,
JA
= 100
°
C/W (G)
T
JMAX
= 125
°
C,
JA
= 150
°
C/W (SW)
LTC1458CG
LTC1458CSW
LTC1458LCG
LTC1458LCSW
Consult factory for Military grade parts.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
q
12
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 1)
q
±
0.5
LSB
INL
Integral Nonlinearity
T
A
= 25
°
C
±
1.75
±
4.0
LSB
(Note 1)
q
±
2.25
±
4.5
LSB
V
OS
Offset Error
T
A
= 25
°
C
±
3.0
±
12
mV
q
±
6.0
±
18
mV
V
OS
TC
Offset Error Temperature
±
15
µ
V/
°
C
Coefficient
V
FS
Full-Scale Voltage
When Using Internal Reference, LTC1458, T
A
= 25
°
C
4.065
4.095
4.125
V
LTC1458
q
4.045
4.095
4.145
V
When Using Internal Reference, LTC1458L, T
A
= 25
°
C
2.470
2.500
2.530
V
LTC1458L
q
2.460
2.500
2.540
V
V
FS
TC
Full-Scale Voltage
When Using Internal Reference
±
24
ppm/
°
C
Temperature Coefficient
Reference
Reference Output Voltage
LTC1458
q
2.008
2.048
2.088
V
LTC1458L
q
1.195
1.220
1.245
V
Reference Output
±
20
ppm/
°
C
Temperature Coefficient
Reference Line Regulation
q
0.7
±
2.0
LSB/V
Reference Load Regulation
0
I
OUT
100
µ
A, LTC1458
q
0.2
1.5
LSB
LTC1458L
q
0.6
3.0
LSB
Reference Input Range
V
REFHI
V
CC
1.5V
V
CC
/2
V
Reference Input Resistance
q
15
24
40
k
3
LTC1458/LTC1458L
ELECTRICAL CHARACTERISTICS
V
CC
= 5V (LTC1458), 3V (LTC1458L), T
A
= T
MIN
to T
MAX
LTC1458
LTC1458L
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Digital I/O
V
IH
Digital Input High Voltage
q
2.4
2.0
V
V
IL
Digital Input Low Voltage
q
0.8
0.6
V
V
OH
Digital Output High Voltage
I
OUT
= 1mA
q
V
CC
1.0
V
CC
0.7
V
V
OL
Digital Output Low Voltage
I
OUT
= 1mA
q
0.4
0.4
V
I
LEAK
Digital Input Leakage
V
IN
= GND to V
CC
q
±
10
±
10
µ
A
C
IN
Digital Input Capacitance
Guaranteed by Design,
q
10
10
pF
Not Subject to Test
Switching
t
1
D
IN
Valid to CLK Setup
q
40
60
ns
t
2
D
IN
Valid to CLK Hold
q
0
0
ns
t
3
CLK High Time
q
40
60
ns
t
4
CLK Low Time
q
40
60
ns
t
5
CS/LD Pulse Width
q
50
80
ns
t
6
LSB CLK to CS/LD
q
40
60
ns
t
7
CS/LD Low to CLK
q
20
30
ns
t
8
D
OUT
Output Delay
C
LOAD
= 15pF
q
150
220
ns
t
9
CLK Low to CS/LD Low
q
20
30
ns
V
CC
= 4.5V to 5.5V (LTC1458), 2.7V to 5.5V (LTC1458L), X1/X2 = REFLO = GND, REFHI = REFOUT, V
OUT
unloaded, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input Capacitance
15
pF
Short-Circuit Current
REFOUT Shorted to GND
q
45
120
mA
Power Supply
V
CC
Positive Supply Voltage
For Specified Performance, LTC1458
q
4.5
5.5
V
LTC1458L
q
2.7
5.5
V
I
CC
Supply Current
4.5V
V
CC
5.5V (Note 4) , LTC1458
q
1100
2400
µ
A
2.7V
V
CC
5.5V (Note 4), LTC1458L
q
800
2000
µ
A
Op Amp DC Performance
Short-Circuit Current Low
V
OUT
Shorted to GND
q
60
120
mA
Short-Circuit Current High
V
OUT
Shorted to V
CC
q
70
120
mA
Output Impedance to GND
Input Code = 0
q
40
120
AC Performance
Voltage Output Slew Rate
(Note 2)
q
0.5
1.0
V/
µ
s
Voltage Output Settling Time
(Notes 2, 3) to
±
0.5LSB
14
µ
s
Digital Feedthrough
0.3
nV · s
AC Feedthrough
REFHI = 1kHz, 2V
P-P
, (Code: All 0s)
95
dB
SINAD
Signal-to-Noise + Distortion
REFHI = 1kHz, 2V
P-P
, (Code: All 1s)
85
dB
4
LTC1458/LTC1458L
ELECTRICAL CHARACTERISTICS
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to code 4095 (full scale).
Note 2: Load is 5k
in parallel with 100pF.
Note 3: DAC switched between all 1s and the code corresponding to V
OS
for the part.
Note 4: Digital inputs at 0V or V
CC
.
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
LTC1458
Integral Nonlinearity (INL)
LTC1458
Differential Nonlinearity (DNL)
CODE
0
DNL (LSB)
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
1024
2048 2560
1458 G09
512
1536
3072 3584 4095
CODE
0
INL ERROR (LSB)
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
2.0
1024
2048 2560
1458 G08
512
1536
3072 3584 4095
Minimum Supply Headroom for
Full Output Swing vs Load Current
LOAD CURRENT (mA)
V
CC
V
OUT
(V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1458 G03
0
V
OUT
< 1LSB
REFLO = GND
X1/X2 = GND
CODE: ALL 1's
V
OUT
= 4.095V
5
10
15
20
25
30
Minimum Output Voltage vs
Output Sink Current
Output Swing vs Load Resistance
LOAD RESISTANCE (
)
10
OUTPUT SWING (V)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
1k
10k
1458 G05A
R
L
REFLO = GND
X1/X2 = GND
LOAD RESISTANCE (
)
10
OUTPUT SWING (V)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
1k
10k
1458 G06A
REFLO = GND
X1/X2 = GND
R
L
V
CC
OUTPUT SINK CURRENT (mA)
OUTPUT PULL-DOWN VOLTAGE (mV)
1000
900
800
700
600
500
400
300
200
100
0.1
1458 G04
0
REFLO = GND
X1/X2 = GND
125
°
C
55
°
C
25
°
C
5
10
15
20
25
30
Output Swing vs Load Resistance
5
LTC1458/LTC1458L
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
TEMPERATURE (
°
C)
55
SFULL-SCALE VOLTAGE (V)
25
5
1458 G06
95
125
4.110
4.105
4.100
4.095
4.090
4.085
4.080
35
65
LTC1458 Full-Scale Voltage vs
Temperature
TEMPERATURE (
°
C)
55
OFFSET VOLTAGE (mV)
25
5
1458 G07
95
125
5
4
3
2
1
0
1
2
3
4
5
35
65
LTC1458
Offset Voltage vs Temperature
TEMPERATURE (
°
C)
55
SUPPLY CURRENT (
µ
A)
25
5
1458 G05
95
125
950
940
930
920
910
900
890
880
870
860
850
35
65
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
LTC1458
Supply Current vs Temperature
PI
N
FU
N
CTIO
N
S
U
U
U
X1/X2 C, X1/X2 D,X1/X2 A, X1/X2 B (Pins 1, 14, 16, 27):
The Input Pin that Sets the Gain for DAC C/D/A/B. When
grounded the gain will be 2, i.e., output full-scale will be
2 · REFHI. When connected to V
OUT
the gain will be 1, i.e.,
output full-scale will be equal to REFHI.
V
OUT C
,
V
OUT D
,
V
OUT A
,
V
OUT B
(Pins 2, 13, 17, 26): The
Buffered DAC Outputs.
CS/LD (Pin 3): The Serial Interface Enable and Load
Control Input.
D
IN
(Pin 4): The Serial Data Input.
REFHI C, REFHI D, REFHI A, REFHI B,(Pins 5, 9, 20, 24):
The Inputs to the DAC Resistor Ladder for DAC C/D/A/B.
GND (Pins 6, 23): Ground.
REFLO C, REFLO D, REFLO A, REFLO B, (Pins 7, 8, 21,
22): The Bottom of the DAC Resistor Ladders for the
DACs. These can be used to offset zero-scale above
ground. REFLO should be connected to ground when no
offset is required.
D
OUT
(Pin 10): The Output of the Shift Register which
Becomes Valid on the Rising Edge of the Serial Clock.
CLK (Pin 11): The Serial Interface Clock Input.
V
CC
(Pins 15, 28): The Positive Supply Input. 4.5V
V
CC
5.5V (LTC1458), 2.7V
V
CC
5.5V (LTC1458L). Re-
quires a bypass capacitor to ground.
REFOUT (Pin 19): The Output of the Internal Reference.
CLR (Pin 25): The Clear Pin. Clears all DACs to zero-scale
when pulled low.
6
LTC1458/LTC1458L
W
I
D AGRA
BLOCK
12-BIT
DAC C
REGISTER
12-BIT
DAC B
REGISTER
48-BIT SHIFT REGISTER
3
4
5
6
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC B
DAC C
12-BIT
DAC D
REGISTER
LD
12-BIT
DAC A
REGISTER
DAC A
DAC D
LTC1458: 2.048V
LTC1458L: 1.22V
POWER-ON
RESET
X1/X2 C
V
OUT C
CS/LD
D
IN
REFHI C
GND
REFLO C
REFLO D
REFHI D
D
OUT
CLK
NC
V
OUT D
X1/X2 D
V
CC
X1/X2 B
V
OUT B
CLR
REFHI B
GND
REFLO B
REFLO A
REFHI A
REFOUT
NC
V
OUT A
X1/X2 A
V
CC
1
2
7
8
9
10
11
12
13
14
28
REFHI
REFLO
V
OUT
X1/X2
+
1458 BD
LD
LD
LD
7
LTC1458/LTC1458L
B11 A
MSB
B11 C
MSB
B0 B
LSB
t
1
t
6
B0 D
LSB
B11 A
CURRENT WORD
t
7
t
2
t
9
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1458 TD
B0 D
PREVIOUS WORD
B11 A
PREVIOUS WORD
B10 A
PREVIOUS WORD
B0 B
PREVIOUS WORD
B11 C
PREVIOUS WORD
B0 D
PREVIOUS WORD
TI I G DIAGRA
W U
W
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2
n
) that divide the full-scale range. The resolution
does not imply linearity.
Full-Scale Voltage (V
FS
): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
): The theoretical voltage at the
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
DEFI ITIO S
U
U
DAC CODE
1458 F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
V
OS
= V
OUT
[(Code)(V
FS
)/(2
n
1)]
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
LSB = (V
FS
V
OS
)/(2
n
1) = (V
FS
V
OS
)/4095
Nominal LSBs:
LTC1458
LSB = 4.095V/4095 = 1mV
LTC1458L
LSB = 2.5V/4095 = 0.610mV
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end-points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
INL
= [V
OUT
V
OS
(V
FS
V
OS
)(code/4095)]/LSB
V
OUT
= The output voltage of the DAC measured at
the given input code
8
LTC1458/LTC1458L
OPERATIO
U
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 48-bit
word, DAC A first, then DAC B, DAC C and DAC D. The MSB
is loaded first for each DAC. The DAC registers load the
data from the shift register when CS/LD is pulled high. The
CLK is disabled internally when CS/LD is high. Note: CLK
must be low before CS/LD is pulled low to avoid an extra
internal clock pulse.
The buffered output of the 48-bit shift register is available
on the D
OUT
pin which swings from ground to V
CC
.
Multiple LTC1458/LTC1458Ls may be daisy-chained to-
gether by connecting the D
OUT
pin to the D
IN
pin of the next
chip, while the CLK and CS/LD signals remain common to
all chips in the daisy-chain. The serial data is clocked to all
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously.
Reference
The LTC1458L has an internal reference of 1.22V with a
full scale of 2.5V (gain of 2 configuration). The LTC1458
includes an internal 2.048V reference, making 1LSB equal
to 1mV (gain of 2 configuration). When the buffer gain is
2, the external reference must be less than V
CC
/ 2 and be
capable of driving the 15k minimum DAC resistor ladder.
The external reference must always be less than
V
CC
1.5V.
Voltage Output
The rail-to-rail buffered output of the LTC1458 family can
source or sink 5mA when operating with a 5V supply over
the entire operating temperature range while pulling to
within 300mV of the positive supply voltage or ground.
The output swings to within a few millivolts of either
supply rail when unloaded and has an equivalent output
resistance of 40
when driving a load to the rails. The
output can drive 1000pF without going into oscillation.
DEFI ITIO S
U
U
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:
DNL
= (
V
OUT
LSB)/LSB
V
OUT
= The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
9
LTC1458/LTC1458L
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Using Two DACs to Digitally Program the Full Scale
and Offset of a Third
Figure 2 shows how to use one LTC1458 to make a 12-bit
DAC with a digitally programmable full scale and offset.
DAC A and DAC B are used to control the offset and full
scale of DAC C. DAC A is connected in a
×
1 configuration
and controls the offset of DAC C by moving REFLO C above
ground. The minimum value to which this offset can be
programmed is 10mV. DAC B is connected in a
×
2
configuration and controls the full scale of DAC C by
driving REFHI C. Note that the voltage at REFHI C must be
less than or equal to V
CC
/2, corresponding to DAC B's code
2,500 for V
CC
= 5V, since DAC C is being operated in
×
2
mode for full rail-to-rail output swing.
The transfer characteristic is:
V
OUTC
= 2 · [D
C
· (2 · D
B
D
A
) + D
A
] · REFOUT
where REFOUT = The Reference Output
D
A
= (DAC A Digital Code)/4096
This sets the offset.
D
B
= (DAC B Digital Code)/4096
This sets the full scale.
D
C
= (DAC C Digital Code)/4096
V
CC
X1/X2 B
V
OUT B
CLR
REFHI B
GND
REFLO B
REFLO A
REFHI A
REFOUT
NC
V
OUT A
X1/X2 A
V
CC
X1/X2 C
V
OUT C
CS/LD
D
IN
REFHI C
GND
REFLO C
REFLO D
REFHI D
D
OUT
CLK
NC
V
OUT D
X1/X2 D
LTC1458
LTC1458L
0.1
µ
F
V
OUT
5V
1458 F02
500
Figure 2
10
LTC1458/LTC1458L
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
G28 SSOP 0694
0.005 0.009
(0.13 0.22)
0
°
8
°
0.022 0.037
(0.55 0.95)
0.205 0.212**
(5.20 5.38)
0.301 0.311
(7.65 7.90)
1
2 3
4
5
6 7 8
9 10 11 12
14
13
0.397 0.407*
(10.07 10.33)
25
26
22 21 20 19 18 17 16 15
23
24
27
28
0.068 0.078
(1.73 1.99)
0.002 0.008
(0.05 0.21)
0.0256
(0.65)
BSC
0.010 0.015
(0.25 0.38)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
11
LTC1458/LTC1458L
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
S28 (WIDE) 0996
0
°
8
°
TYP
NOTE 1
0.009 0.013
(0.229 0.330)
0.016 0.050
(0.406 1.270)
0.291 0.299**
(7.391 7.595)
×
45
°
0.010 0.029
(0.254 0.737)
0.037 0.045
(0.940 1.143)
0.004 0.012
(0.102 0.305)
0.093 0.104
(2.362 2.642)
0.050
(1.270)
TYP
0.014 0.019
(0.356 0.482)
TYP
NOTE 1
0.697 0.712*
(17.70 18.08)
1
2
3
4
5
6
7
8
0.394 0.419
(10.007 10.643)
9
10
25
26
11
12
22
21
20
19
18
17
16
15
23
24
14
13
27
28
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
12
LTC1458/LTC1458L
©
LINEAR TECHNOLOGY CORPORATION 1996
14588lf LT/TP 0397 7K · PRINTED IN USA
TYPICAL APPLICATIO
N
U
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-Bit V
OUT
DAC, Full Scale: 2.048V, V
CC
: 4.75V to 15.75V,
5V to 15V Single Supply, Complete V
OUT
DAC in
Reference Can Be Overdriven up to 12V, i.e., FS
MAX
= 12V
SO-8 Package
LTC1446/LTC1446L
Dual 12-Bit Rail-to-Rail Output DACs in SO-8 Package
LTC1446: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1446L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1450/LTC1450L
Single 12-Bit Rail-to-Rail Output DACs with Parallel Interface
LTC1450: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1450L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1451
Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, V
CC
: 4.5V to 5.5V
Low Power, Complete V
OUT
DAC in SO-8 Package
LTC1452
Single Rail-to-Rail 12-Bit V
OUT
Multiplying DAC, V
CC
: 2.7V to 5.5V
Low Power, Multiplying V
OUT
DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
LTC1453
Single Rail-to-Rail 12-Bit V
OUT
DAC, Full Scale: 2.5V, V
CC
: 2.7V to 5.5V
3V, Low Power, Complete V
OUT
DAC in SO-8 Package
LTC1454/LTC1454L
Dual 12-Bit V
OUT
DACs in SO-16 Package with Added Functionality
LTC1454: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1454L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Low Power, Complete V
OUT
DAC in SO-8 Package
Full Scale: 4.095V, V
CC
: 4.5V to 5.5V
with Clear Pin
V
CC
X1/X2 B
V
OUT B
CLR
REFHI B
GND
REFLO B
REFLO A
REFHI A
REFOUT
NC
V
OUT A
X1/X2 A
V
CC
X1/X2 C
V
OUT C
CS/LD
D
IN
REFHI C
GND
REFLO C
REFLO D
REFHI D
D
OUT
CLK
NC
V
OUT D
X1/X2 D
LTC1458
LTC1458L
0.1
µ
F
1458 TA03
LTC1458: 0V TO 4.095V
LTC1458L: 0V TO 2.5V
LTC1458: 0V TO 4.095V
LTC1458L: 0V TO 2.5V
LTC1458: 2.048V
LTC1458L: 1.22V
LTC1458: 0V TO 4.095V
LTC1458L: 0V TO 2.5V
LTC1458: 0V TO 4.095V
LTC1458L: 0V TO 2.5V
LTC1458: 4.5V TO 5.5V
LTC1458L: 2.7V TO 5.5V
µ
P
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
q
(408) 432-1900
FAX: (408) 434-0507
q
TELEX: 499-3977
q
www.linear-tech.com
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