1
LTC1454/LTC1454L
Dual 12-Bit Rail-to-Rail
Micropower DACs
Daisy-Chained Control Outputs
Functional Block Diagram: Dual 12-Bit Rail-to-Rail DAC
X1/X2 B
X1/X2 A
D
IN
CLK
D
OUT
V
CC
POWER-ON
RESET
+
12-BIT
DAC A
12-BIT
DAC B
REFOUT
CS/LD
V
OUT B
REFHI B
REFHI A
REFLO
GND
14
16
1
11
8
7
12
2
6
5
3
4
9, 15
LTC1454: 5V
LTC1454L: 3V TO 5V
LTC1454: 2.048V
LTC1454L: 1.22V
10
13
V
OUT A
+
CLR
1454 BD02
24-BIT
SHIFT
REG
AND
DAC
LATCH
µ
P
Differential Nonlinearity
vs Input Code
CODE
0
DNL ERROR (LSB)
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
1024
2048 2560
1454 G08
512
1536
3072 3584 4095
FEATURES
s
12-Bit Resolution
s
Buffered True Rail-to-Rail Voltage Output
s
5V Operation, I
CC
: 700
µ
A Typ (LTC1454)
s
3V Operation, I
CC
: 450
µ
A Typ (LTC1454L)
s
Built-In Reference: 2.048V (LTC1454)
1.220V (LTC1454L)
s
CLR Pin
s
Power-On Reset
s
16-Lead SO Package
s
3-Wire Cascadable Serial Interface
s
Maximum DNL Error: 0.5LSB
s
Low Cost
The LTC
®
1454/LTC1454L are complete single supply,
dual rail-to-rail voltage output, 12-bit digital-to-analog
converters (DACs) in a 16-lead SO package. They include
an output buffer amplifier with variable gain (
×
1 or
×
2)
and an easy-to-use 3-wire cascadable serial interface.
The LTC1454 has an onboard reference of 2.048V and a
full-scale output of 4.095V in a
×
2 gain configuration. It
operates from a single 4.5V to 5.5V supply.
The LTC1454L has an onboard 1.22V reference and a full-
scale output of 2.5V in a
×
2 gain configuration. It operates
from a single 2.7V to 5.5V supply.
Low power supply current, excellent DNL and small size
allow these parts to be used in a host of applications where
size, DNL and single supply operation are important.
DESCRIPTIO
N
U
APPLICATIO
N
S
U
s
Digital Calibration
s
Industrial Process Control
s
Automatic Test Equipment
s
Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
N
U
2
LTC1454/LTC1454L
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
W
U
U
PACKAGE/ORDER I FOR ATIO
V
CC
to GND .............................................. 0.5V to 7.5V
Logic Inputs to GND ................................ 0.5V to 7.5V
V
OUT A
, V
OUT B
, X1/X2 A ,
X1/X2 B ..................................... 0.5V to V
CC
+ 0.5V
REFHI A , REFHI B, REFLO ............. 0.5V to V
CC
+ 0.5V
Maximum Junction Temperature .......................... 125
°
C
Operating Temperature Range
LTC1454C/LTC1454LC ............................ 0
°
C to 70
°
C
LTC1454I/LTC1454LI ........................ 40
°
C to 85
°
C
Storage Temperature Range ................ 65
°
C to 150
°
C
Lead Temperature (Soldering, 10 sec) ................. 300
°
C
LTC1454CN
LTC1454IN
LTC1454CS
LTC1454IS
LTC1454LCN
LTC1454LIN
LTC1454LCS
LTC1454LIS
ORDER PART
NUMBER
T
JMAX
= 125
°
C,
JA
= 100
°
C/W (N)
T
JMAX
= 125
°
C,
JA
= 150
°
C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V
CC
= 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, V
OUT
and REFOUT unloaded,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
q
12
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 1)
q
±
0.5
LSB
INL
Integral Nonlinearity
T
A
= 25
°
C
±
2.0
±
4.0
LSB
(Note 1)
q
±
2.5
±
4.5
LSB
V
OS
Offset Error
T
A
= 25
°
C
±
2.0
±
12
mV
q
±
4.0
±
18
mV
V
OS
TC
Offset Error Temperature
±
15
µ
V/
°
C
Coefficient
V
FS
Full-Scale Voltage
When Using Internal Reference, LTC1454, T
A
= 25
°
C
4.065
4.095
4.125
V
LTC1454
q
4.045
4.095
4.145
V
When Using Internal Reference, LTC1454L, T
A
= 25
°
C
2.470
2.500
2.530
V
LTC1454L
q
2.460
2.500
2.540
V
V
FS
TC
Full-Scale Voltage
When Using Internal Reference
±
24
ppm/
°
C
Temperature Coefficient
Reference
Reference Output Voltage
LTC1454
q
2.008
2.048
2.088
V
LTC1454L
q
1.195
1.220
1.245
V
Reference Output
±
20
ppm/
°
C
Temperature Coefficient
Reference Line Regulation
q
0.7
±
2.0
LSB/V
Reference Load Regulation
0
I
OUT
100
µ
A, LTC1454
q
0.2
1.5
LSB
LTC1454L
q
0.6
3.0
LSB
Reference Input Range
V
REFHI
V
CC
1.5V
V
CC
/ 2
V
Reference Input Resistance
q
15
24
40
k
Reference Input Capacitance
15
pF
Short-Circuit Current
REFOUT Shorted to GND
q
40
120
mA
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
N PACKAGE
16-LEAD PDIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X1/X2 B
CLR
CLK
D
IN
CS/LD
D
OUT
X1/X2 A
V
OUT A
V
OUT B
V
CC
REFHI B
GND
REFLO
REFHI A
REFOUT
V
CC
3
LTC1454/LTC1454L
ELECTRICAL CHARACTERISTICS
V
CC
= 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, V
OUT
and REFOUT unloaded,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
V
CC
Positive Supply Voltage
For Specified Performance, LTC1454
q
4.5
5.5
V
LTC1454L
q
2.7
5.5
V
I
CC
Supply Current
4.5V
V
CC
5.5V (Note 4), LTC1454
q
700
1250
µ
A
2.7V
V
CC
5.5V (Note 4), LTC1454L
q
450
1100
µ
A
Op Amp DC Performance
Short-Circuit Current Low
V
OUT
Shorted to GND
q
70
120
mA
Short-Circuit Current High
V
OUT
Shorted to V
CC
q
80
120
mA
Output Impedance to GND
Input Code = 0
q
40
AC Performance
Voltage Output Slew Rate
(Note 2)
q
0.5
1.0
V/
µ
s
Voltage Output Settling Time
(Notes 2, 3) to
±
0.5LSB
14
µ
s
Digital Feedthrough
0.3
nV · s
AC Feedthrough
REFHI = 1kHz, 2V
P-P
, (Code: All 0s)
95
dB
SINAD
Signal-to-Noise + Distortion
REFHI = 1kHz, 2V
P-P
, (Code: All 1s)
85
dB
V
CC
= 5V (LTC1454), 3V (LTC1454L), T
A
= T
MIN
to T
MAX
, unless otherwise noted.
LTC1454
LTC1454L
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Digital I/O
V
IH
Digital Input High Voltage
q
2.4
2.0
V
V
IL
Digital Input Low Voltage
q
0.8
0.6
V
V
OH
Digital Output High Voltage
I
OUT
= 1mA
q
V
CC
1.0
V
CC
0.7
V
V
OL
Digital Output Low Voltage
I
OUT
= 1mA
q
0.4
0.4
V
I
LEAK
Digital Input Leakage
V
IN
= GND to V
CC
q
±
10
±
10
µ
A
C
IN
Digital Input Capacitance
Guaranteed by Design
q
10
10
pF
Switching
t
1
D
IN
Valid to CLK Setup
q
40
60
ns
t
2
D
IN
Valid to CLK Hold
q
0
0
ns
t
3
CLK High Time
q
40
60
ns
t
4
CLK Low Time
q
40
60
ns
t
5
CS/LD Pulse Width
q
50
80
ns
t
6
LSB CLK to CS/LD
q
40
60
ns
t7
CS/LD Low to CLK
q
20
30
ns
t
8
D
OUT
Output Delay
C
LOAD
= 15pF
q
150
220
ns
t
9
CLK Low to CS/LD Low
q
20
30
ns
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to code 4095 (full scale).
Note 2: Load is 5k
in parallel with 100pF.
Note 3: DAC switched between all 1s and the code corresponding to V
OS
for the part.
Note 4: Digital inputs at 0V or V
CC
.
4
LTC1454/LTC1454L
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
Minimum Supply Headroom for
Full Output Swing vs Load Current
LTC1454 Output Swing vs
Load Resistance
CODE
0
DNL ERROR (LSB)
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
1024
2048 2560
1454 G08
512
1536
3072 3584 4095
CODE
0
INL ERROR (LSB)
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
2.0
1024
2048 2560
1454 G07
512
1536
3072 3584 4095
LOAD CURRENT (mA)
V
CC
V
OUT
(V)
1.0
0.8
0.6
0.4
0.2
0
1454 G03
0
V
OUT
< 1LSB
REFLO = GND
X1/X2 = GND
CODE: ALL 1's
V
OUT
= 4.095V
5
10
15
20
25
30
LTC1454 Minimum Output
Voltage vs Output Sink Current
LTC1454 Output Swing vs
Load Resistance
OUTPUT SINK CURRENT (mA)
OUTPUT PULL-DOWN VOLTAGE (mV)
1000
900
800
700
600
500
400
300
200
100
0.1
1454 G04
0
125
°
C
REFLO = GND
X1/X2 = GND
55
°
C
25
°
C
5
10
15
20
25
30
LOAD RESISTANCE (
)
10
OUTPUT SWING (V)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
1k
10k
1454 G05
R
L
REFLO = GND
X1/X2 = GND
LOAD RESISTANCE (
)
10
OUTPUT SWING (V)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
1k
10k
1458 G06
REFLO = GND
X1/X2 = GND
R
L
V
CC
LTC1454 Full-Scale Voltage vs
Temperature
TEMPERATURE (
°
C)
55
SFULL-SCALE VOLTAGE (V)
25
5
1454 G02
95
125
4.110
4.105
4.100
4.095
4.090
4.085
4.080
35
65
TEMPERATURE (
°
C)
55
SUPPLY CURRENT (
µ
A)
25
5
1454 G01
95
125
760
750
740
730
720
710
700
690
35
65
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
LTC1454
Supply Current vs Temperature
LOGIC INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
2.6
2.1
1.6
1.1
0.6
1.0
2.0 2.5
4.5 5.0
1454 G09
0.5
1.5
3.0 3.5 4.0
LTC1454 Supply Current vs
Logic Input Voltage
LTC1454
Differential Nonlinearity
LTC1454
Integral Nonlinearity
5
LTC1454/LTC1454L
X1/X2 B, X1/ X2 A (Pins 1, 7): The Input Pin that Sets the
Gain for DAC A/B. When grounded the gain will be 2, i.e.,
output full scale will be
×
2 REFHI. When connected to
V
OUT
the gain will be 1, i.e., output full scale will be equal
to REFHI.
CLR (Pin 2): The Clear Pin for the DAC. Clears both DACs
to zero scale when pulled low. This pin should be tied to
V
CC
for normal operation.
CLK (Pin 3): The Serial Interface Clock Input.
D
IN
(Pin 4): The Serial Data Input. Data on the D
IN
pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded as one 24-bit word. The first 12 bits
are for DAC A, MSB-first and the second 12 bits are for
DAC B, MSB-first.
CS/LD (Pin 5): The Serial Interface Enable and Load
Control Input. When CS/LD is low the CLK signal is
enabled so the data can be clocked in. When CS/LD is
PI
N
FU
N
CTIO
N
S
U
U
U
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
D
OUT
(Pin 6): The Output of the Shift Register which
Becomes Valid on the Rising Edge of the Serial Clock.
V
OUT A,
V
OUT B
(Pins 8, 16): The Buffered DAC Outputs.
V
CC
(Pins 9, 15): The Positive Supply Input. 4.5
V
CC
5.5V (LTC1454), 2.7V
V
CC
5.5V (LTC1454L). Re-
quires a bypass capacitor to ground.
REFOUT (Pin 10): The Output of the Internal Reference.
REFHI A , REFHI B (Pins 11,14): The Inputs to the DAC
Resistor Ladder for DAC A/B.
REFLO (Pin 12): The Bottom of the DAC Resistor Ladder
for Both DACs. This can be used to offset zero-scale above
ground. REFLO should be connected to ground when no
offset is required.
GND (Pin 13): Ground.
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