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LTC1426

Micropower

Dual 6-Bit PWM DAC

FEATURES

DESCRIPTIO

Wide Supply Range: 2.7V

5.5V

Wide Reference Voltage Range: 0V to 5.5V

Two Interface Modes:

Pulse Mode (Increment Only)
Pushbutton Mode (Increment/Decrement)

Low Supply Current: 50

0.2

A Supply Current in Shutdown

Available in 8-Pin MSOP and SO Packages

DAC Contents Are Retained in Shutdown

DACs Power-Up at Midrange

Low Output Impedance: < 100

Output Frequency: 5kHz Typ

The LTC

1426 is a dual micropower 6-bit PWM DAC

featuring versatile PWM outputs and a flexible pushbutton
compatible digital interface. The DAC outputs provide a
PWM signal that swings from 0V to V

REF

, allowing the full-

scale output to be varied by adjusting the voltage at V

REF

The PWM output frequency is typically 5kHz, easing
output filtering requirements. V

supply current is typi-

cally 50

A and drops to 0.2

A in shutdown.

The LTC1426 can be controlled using one of two interface
modes: pushbutton and pulse. The LTC1426 automati-
cally configures itself into the appropriate mode at start-
up by monitoring the state of the CLK pins. In pushbutton
mode, the CLK pins can be directly connected to external
pushbuttons to control the DAC output. In pulse mode,
the CLK pins can be connected to CMOS compatible
logic. The DAC outputs initially power up at half scale and
the contents of the internal DAC registers are retained in
shutdown.

The LTC1426 is available in 8-pin MSOP and SO packages.

, LTC and LT are registered trademarks of Linear Technology Corporation.

LCD Contrast and Backlight Brightness Control

Power Supply Voltage Adjustment

Battery Charger Voltage and Current Adjustment

GaAs FET Bias Adjustment

Trimmer Pot Elimination

APPLICATIO

TYPICAL APPLICATIO

Pushbutton Adjustable CCFL/LCD Contrast Generator

CLK1

CLK2

GND

PWM1

SHDN

REF

PWM2

LTC1426

CCFL PGND

CCFL

DIO

CCFL V

AGND

SHDN

LCD V

LCD PGND

CCFL V

BULB

BAT

ROYER

FBP

FBN

LCD V

LT1182

1426 TA01

C4
0.1

DOWN

CONTRAST

UP/DOWN

CCFL UP/DOWN

DOWN

47k

SHDN

R5
20k
1%

40k

4.99k

5.1k

44.2k

UP TO 6mA

CCFL

= 0

A TO 50

C3
10

C9
2.2

CONSULT THE LT1182 DATA SHEET FOR
DETAILS ON THE HIGH VOLTAGE ROYER
AND LCD CONTRAST CONVERTER SECTIONS

C2
1

C10
2.2

35V

8V TO
28V

C1
0.1

0.68

C7 1

10k

HIGH VOLTAGE

ROYER

LAMP

LCD

CONTRAST

CONVERTER

OUT

NEGATIVE
LCD CONTRAST
V

OUT

= 10V TO 30V

C11
2.2

35V

LTC1426

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I

FOR

ATIO

(Note 1)

Total Supply Voltage (V

) ........................................ 7V

Reference Voltage (V

REF

) ............................... 0.3 to 7V

Input Voltage (All Inputs) .............. 0.3 to (V

+ 0.3V)

DAC Output Short-Circuit Duration .................. Indefinite
I

PWM(MAX)

.......................................................... 100mA

Operating Temperature Range

LTC1426C................................................ 0

C to 70

LTC1426I ........................................... 40

C to 85

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

ORDER PART

NUMBER

MS8 PART MARKING

LTC1426CMS8
LTC1426CS8
LTC1426IS8

S8 PART MARKING

1426
1426I

LTBQ

TOP VIEW

S8 PACKAGE

8-LEAD PLASTIC SO

MS8 PACKAGE

8-LEAD PLASTIC MSOP

CLK1

CLK2

GND

PWM1

SHDN

REF

PWM2

JMAX

= 100

= 200

C/ W (MS8)

JMAX

= 100

= 130

C/ W (S8)

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

= 25

C, (Note 2) unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.7

5.5

REF

Reference Voltage

5.5

Supply Current

Pulse Mode: V

SHDN

= V

, V

CLK1

= V

CLK2

= 0V, PWM1 = PWM2 = NC

100

Pushbutton Mode: V

SHDN

= V

, V

CLK1

= V

CLK2

= PWM1 = PWM2 = NC

100

SHDN = 0 (Note 3)

0.2

REF

Reference Current

Pulse Mode: V

SHDN

= V

, V

CLK1

= V

CLK2

= 0V, PWM1 = PWM2 = NC

150

Pushbutton Mode: V

SHDN

= V

, V

CLK1

= V

CLK2

= PWM1 = PWM2 = NC

150

SHDN = 0 (Note 3)

0.2

DAC Resolution

bits

DAC Frequency

kHz

DAC Output Impedance

= 2.7V, V

REF

= 0.5V

100

DAC Full-Scale Duty Cycle

98.44

DAC Zero-Scale Duty Cycle

DNL

DAC Differential Nonlinearity

Monotonicity Guaranteed (Note 4)

0.05

LSB

INL

DAC Integral Nonlinearity

(Note 4)

0.05

LSB

FS Error

DAC Full-Scale Error

0.50

LSB

Logic Input Current

Pulse Mode: 0V

SHDN

CLK1, CLK2

Pushbutton Mode: 0V

SHDN

CLK1, CLK2

CLK High Level

= 5.5V

SHDN

2.0

Input Voltage (Note 5)

CLK1, CLK2

4.4

= 3.6V

SHDN

1.9

CLK1, CLK2

2.9

LTC1426

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CLK Low Level

= 4.5V

SHDN

0.8

Input Voltage (Note 5)

CLK1, CLK2

0.8

= 2.7V

SHDN

0.45

CLK1, CLK2

0.45

Three-State Output Leakage

SHDN = 0

CLK Input Resistance

Pushbutton Mode, CLK1/CLK2

2.5

CLK

Clock Frequency

Pulse Mode, V

= 3.3V

MHz

Pulse Mode, V

= 2.7V

750

kHz

CKHI

Clock High Time

Pulse Mode, V

= 3.3V

450

Pulse Mode, V

= 2.7V

600

CKLO

Clock Low Time

Pulse Mode, V

= 3.3V

450

Pulse Mode, V

= 2.7V

600

Pulse Width

Pushbutton Mode

670

DEB

Debounce Time

Pushbutton Mode

10.7

12.8

21.3

DELAY

Repeat Rate Delay

Pushbutton Mode

340

410

680

REPEAT

Repeat Frequency

Pushbutton Mode

11.7

19.5

23.4

ELECTRICAL CHARACTERISTICS

= 25

C, (Note 2) unless otherwise specified.

Note 3: Shutdown current can be negative due to leakage currents if V

REF

or V

REF

> V

Note 4: Guaranteed by Design. Decouple the V

and V

REF

pins to GND

using high quality, low ESR, low ESL 0.1

F capacitors to eliminate PWM

switching noise that may otherwise get coupled into the CLK1/CLK2 high
impedance input buffers. The decoupling capacitors should be located in
close proximity to these pins and the ground line to have maximum effect.

Note 5: Input thresholds apply for both pushbutton and pulse modes.

The

denotes the specifications which apply over the full operating

temperature range.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground, unless otherwise
specified. All typicals are given for V

= V

REF

= 5V, T

= 25

C and

PWM1/PWM2 output to GND, C

PWM

= 10pF.

TYPICAL PERFOR

CE CHARACTERISTICS

CODE

0.05

DNL ERROR (LSB)

0.04

0.02

0.01

0.05

0.02

1426 G01

0.03

0.04

0.01

= V

REF

= 5V

= 25

CODE

0.05

ERROR (LSB)

0.04

0.02

0.01

0.05

0.02

1426 G02

0.03

0.04

0.01

= V

REF

= 5V

= 25

OUTPUT CURRENT SINK CAPABILITY (mA)

OUTPUT PULL-DOWN VOLTAGE (mV)

100

1000

0.1

100

1426 G03

0.1

= 5V

Output Pull-Down Voltage
vs Output Current Sink Capability

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

LTC1426

TYPICAL PERFOR

CE CHARACTERISTICS

TEMPERATURE (

CLOCK HIGH TIME (ns)

100

200

300

400

500

600

1426 G04

= 3V

= 5V

TEMPERATURE (

SUPPLY CURRENT (

1426 G06

PUSHBUTTON

MODE

PULSE

MODE

= 5V

Supply Current vs Temperature

LOGIC INPUT VOLTAGE (V)

SUPPLY CURRENT (

38.5

36.5

34.5

32.5

30.5

28.5

26.5

24.5

22.5

1426 F05

PULSE

MODE

PUSHBUTTON

MODE

= 25

CLK1 AND CLK2
TIED TOGETHER

Supply Current
vs Logic Input Voltage

CTIO

span. Bypass V

REF

to GND with an external capacitor to

minimize output errors. V

REF

can be tied to V

if desired.

(Pin 7): Voltage Supply. This supply must be kept free

from noise and ripple by bypassing directly to the ground
plane.

SHDN (Pin 8): Shutdown. A logic low puts the chip into
shutdown mode with the PWM outputs in high imped-
ance. The digital settings for the DACs are retained in
shutdown.

CLK1 (Pin 1): Channel 1 Clock/Pushbutton Input.

CLK2 (Pin 2): Channel 2 Clock/Pushbutton Input.

GND (Pin 3): Ground. It is recommended that GND be tied
to a ground plane.

PWM1 (Pin 4): Channel 1 PWM Output.

PWM2 (Pin 5): Channel 2 PWM Output.

REF

(Pin 6): Voltage Reference Input. V

REF

powers the

DAC output buffers and can be used to control the output

CLK1
CLK2

CKL0

1426 TC01

CKHI

1426 TC02

CLK1
CLK2

Pushbutton Mode Timing

Pulse Mode Timing

TI I G DIAGRA S

Minimum Clock High Time
vs Temperature

LTC1426

BLOCK DIAGRA

APPLICATIO

S I

FOR

ATIO

PWM1

REF

PWM2

1426 F01

COMPARATOR

DRIVER

6-BIT

UP/DOWN

COUNTER

DEBOUNCE

CIRCUIT

6-BIT

COUNTER

LATCH

AND

LOGIC

CONTROL

LOGIC

MODE SELECT
0 = PUSHBUTTON MODE
1 = PULSE MODE

6-BIT

UP/DOWN

COUNTER

POWER-ON

RESET

OSCILLATOR

SHDN

INPUT

CONDITIONING

CLK1
CLK2

Figure 1. LTC1426 Block Diagram

DEFI ITIO S

LSB: The least significant bit or the ideal duty cycle
difference between two successive codes.

LSB = DC

MAX

/64

MAX

= The DAC output maximum duty cycle

Resolution: The resolution is the number of DAC output
states (64) that divide the full-scale output duty cycle
range. The resolution does not necessarily imply linearity.

INL: End point integral nonlinearity is the maximum devia-
tion from a straight line passing through the end points of
the DAC transfer curve. The INL error at a given code is
calculated as follows:

INL = (DC

OUT

IDEAL

)/LSB

IDEAL

= (Code)(LSB)

OUT

= the DAC output duty cycle measured at the

given number of clocked in pulses.

DNL: Differential nonlinearity is the difference between the
measured duty cycle change and the ideal 1LSB duty cycle
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:

DNL = (

OUT

LSB)/LSB

OUT

= The measured duty cycle difference between

two adjacent codes.

Full-Scale Error: Full-scale error is the difference between
the ideal and measured DAC output duty cycles with all bits
set to one (Code = 63). The full-scale error is calculated as
follows:

FSE = (DC

OUT

IDEAL

)/LSB

IDEAL

= DC

MAX

Dual 6-Bit PWM DAC

Figure 1 shows a block diagram of the LTC1426. Each
6-bit PWM DAC is guaranteed monotonic and is digitally
adjustable in 64 equal steps, which corresponds from 0%
to 98.5% duty cycle full scale. At power-up, the counters
reset to 100000B and both DAC outputs assume midscale
duty cycle. The PWM outputs have an output impedance

of less than 100

. The DAC outputs swing from 0V to the

reference voltage, V

REF

, which can be biased from 0V to

5.5V. The frequency of the DAC outputs is above 3kHz,
easing output filtering.

In the case of a pure resistive load, the voltage measured
across load RL is given by:

V = (V

PWM

/(R

+ R

OUT

)

Part Number LTC1426