1
LTC1293/LTC1294/LTC1296
Single Chip 12-Bit
Data Acquisition System
The LTC1293/4/6 is a family of data acquisition systems
which contain a serial I/O successive approximation A/D
converter. It uses LTCMOS
TM
switched capacitor technol-
ogy to perform either 12-bit unipolar, or 11-bit plus sign
bipolar A/D conversions. The input multiplexer can be
configured for either single ended or differential inputs (or
combinations thereof). An on-chip sample and hold is
included for all single ended input channels. When the
LTC1293/4/6 is idle it can be powered down in applica-
tions where low power consumption is desired. The
LTC1296 includes a System Shutdown Output pin which
can be used to power down external circuitry, such as
signal conditioning circuitry prior to the input mux.
The serial I/O is designed to communicate without external
hardware to most MPU serial ports and all MPU parallel
I/O ports allowing up to eight channels of data to be
transmitted over as few as three wires.
D
U
ESCRIPTIO
S
FEATURE
s
Software Programmable Features
Unipolar/Bipolar Conversion
Differential/Single Ended Inputs
MSB-First or MSB/LSB Data Sequence
Power Shutdown
s
Built-In Sample and Hold
s
Single Supply 5V or
±
5V Operation
s
Direct 4-Wire Interface to Most MPU Serial
Ports and All MPU Parallel Ports
s
46.5kHz Maximum Throughput Rate
s
System Shutdown Output (LTC1296)
s
Resolution ..................................................... 12 Bits
s
Fast Conversion Time ............ 12
µ
s Max Over Temp.
s
Low Supply Current ........................................ 6.0mA
KEY SPECIFICATIO S
U
U
A
O
PPLICATI
TYPICAL
12-Bit Data Acquisition System with Power Shutdown
LTCMOS
TM
is a trademark of Linear Technology Corporation
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
+
R
B
5.1k
R2
1.2M
R1
10k
1/4 LT1014
R2
1.2M
C2
1
µ
F
350
STRAIN
GAUGE BRIDGE
+5V
47
µ
F
1N4148
MPU
LTC1296
V
CC
SSO
CLK
CS
D
OUT
D
IN
REF
+
REF
AGND
V
THREE ADDITIONAL STRAIN GAUGE INPUTS
CAN BE ACCOMMODATED USING THE OTHER
AMPLIFIERS IN THE LT1014
LTC1293 TA01
2N3906
74HC04
2
LTC1293/LTC1294/LTC1296
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
Supply Voltage (V
CC
) to GND or V
...................................................
12V
Negative Supply Voltage (V
) ..................... 6V to GND
Voltage
Analog and Reference
Inputs ............................ (V
) 0.3V to V
CC
+ 0.3V
Digital Inputs ......................................... 0.3V to 12V
Digital Outputs........................... 0.3V to V
CC
+ 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1293/4/6BC, LTC1293/4/6CC,
LTC1293/4/6DC ....................................... 0
°
C to 70
°
C
LTC1293/4/6BI, LTC1293/4/6CI,
LTC1293/4/6DI .................................... 40
°
C to 85
°
C
LTC1293/4/6BM, LTC1293/4/6CM,
LTC1293/4/6DM ............................... 55
°
C to 125
°
C
Storage Temperature Range .................. 65
°
C to 150
°
C
Lead Temperature (Soldering, 10 sec.) ................ 300
°
C
(Note 1 and 2)
W
U
U
PACKAGE/ORDER I FOR ATIO
LTC1293BCS
LTC1293CCS
LTC1293DCS
ORDER PART
NUMBER
ORDER PART
NUMBER
LTC1293BMJ
LTC1293CMJ
LTC1293DMJ
LTC1293BIJ
LTC1293CIJ
LTC1293DIJ
LTC1293BIN
LTC1293CIN
LTC1293DIN
LTC1293BCN
LTC1293CCN
LTC1293DCN
LTC1294BCS
LTC1294CCS
LTC1294DCS
LTC1296BCS
LTC1296CCS
LTC1296DCS
LTC1294BIN
LTC1294CIN
LTC1294DIN
LTC1294BCN
LTC1294CCN
LTC1294DCN
LTC1294BMJ
LTC1294CMJ
LTC1294DMJ
LTC1294BIJ
LTC1294CIJ
LTC1294DIJ
LTC1296BIN
LTC1296CIN
LTC1296DIN
LTC1296BCN
LTC1296CCN
LTC1296DCN
LTC1296BMJ
LTC1296CMJ
LTC1296DMJ
LTC1296BIJ
LTC1296CIJ
LTC1296DIJ
1
2
3
4
5
6
7
8
9
10
TOP VIEW
S PACKAGE
20-LEAD PLASTIC SO
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DV
CC
AV
CC
CLK
CS
D
OUT
D
IN
REF
+
REF
AGND
V
1
2
3
4
5
6
7
8
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SOL
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
COM
DGND
V
CC
CLK
CS
D
OUT
D
IN
V
REF
AGND
V
1
2
3
4
5
6
7
8
TOP VIEW
J PACKAGE
16-LEAD CERAMIC DIP
N PACKAGE
16-LEAD PLASTIC DIP
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
COM
DGND
V
CC
CLK
CS
D
OUT
D
IN
V
REF
AGND
V
1
2
3
4
5
6
7
8
9
10
TOP VIEW
J PACKAGE
20-LEAD CERAMIC DIP
N PACKAGE
20-LEAD PLASTIC DIP
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
V
CC
SSO
CLK
CS
D
OUT
D
IN
REF
+
REF
AGND
V
1
2
3
4
5
6
7
8
9
10
TOP VIEW
S PACKAGE
20-LEAD PLASTIC SO
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
V
CC
SSO
CLK
CS
D
OUT
D
IN
REF
+
REF
AGND
V
1
2
3
4
5
6
7
8
9
10
TOP VIEW
J PACKAGE
20-LEAD CERAMIC DIP
N PACKAGE
20-LEAD PLASTIC DIP
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
DV
CC
AV
CC
CLK
CS
D
OUT
D
IN
REF
+
REF
AGND
V
3
LTC1293/LTC1294/LTC1296
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Offset Error
(Note 4)
q
±
3.0
±
3.0
±
3.0
LSB
Linearity Error (INL)
(Notes 4, 5)
q
±
0.5
±
0.5
±
0.75
LSB
Gain Error
(Note 4)
q
±
0.5
±
1.0
±
4.0
LSB
Minimum Resolution for which No
q
12
12
12
Bits
Missing Codes are Guaranteed
Analog and REF Input Range
(Note 7)
(V
)0.05V to V
CC
+ 0.05V
V
On Channel Leakage Current (Note 8)
On Channel = 5V
q
±
1
±
1
±
1
µ
A
Off Channel = 0V
On Channel = 0V
q
±
1
±
1
±
1
µ
A
Off Channel = 5V
Off Channel Lekage Current (Note 8)
On Channel = 5V
q
±
1
±
1
±
1
µ
A
Off Channel = 0V
On Channel = 0V
q
±
1
±
1
±
1
µ
A
Off Channel = 5V
(Note 3)
CO VERTER A D ULTIPLEXER CHARACTERISTICS
U
U W
LTC1293/4/6C
LTC1293/4/6D
LTC1293/4/6B
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
CLK
Clock Frequency
V
CC
= 5V (Note 6)
0.1
1.0
MHz
t
SMPL
Analog Input Sample Time
See Operating Sequence
2.5
CLK Cycles
t
CONV
Conversion Time
See Operating Sequence
12
CLK Cycles
t
CYC
Total Cycle Time
See Operating Sequence (Note 6)
21 CLK
Cycles
+500ns
t
dDO
Delay Time, CLK
to D
OUT
Data Valid
See Test Circuits
q
160
300
ns
t
dis
Delay Time, CS
to D
OUT
Hi-Z
See Test Circuits
q
80
150
ns
t
en
Delay Time, CLK
to D
OUT
Enabled
See Test Circuits
q
80
200
ns
t
hDI
Hold Time, D
IN
after CLK
V
CC
= 5V (Note 6)
50
ns
t
hDO
Time Output Data Remains Valid After CLK
130
ns
t
f
D
OUT
Fall Time
See Test Circuits
q
65
130
ns
t
r
D
OUT
Rise Time
See Test Circuits
q
25
50
ns
t
WHCLK
CLK High Time
V
CC
= 5V (Note 6)
300
ns
t
WLCLK
CLK Low Time
V
CC
= 5V (Note 6)
400
ns
t
suDI
Set-up Time, D
IN
Stable Before CLK
V
CC
= 5V (Note 6)
50
ns
t
suCS
Set-up Time, CS
before CLK
V
CC
= 5V (Note 6)
50
ns
t
wHCS
CS High Time During Conversion
V
CC
= 5V (Note 6)
500
ns
t
wLCS
CS Low Time During Data Transfer
V
CC
= 5V (Note 6)
21
CLK Cycles
t
enSSO
Delay Time, CLK
to SSO
See Test Circuits
q
750
1500
ns
t
disSSO
Delay Time, CS
to SSO
See Test Circuits
q
250
500
ns
C
IN
Input Capacitance
Analog Inputs On Channel
100
pF
Analog Inputs Off Channel
5
Digital Inputs
5
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
AC CHARACTERISTICS
(Note 3)
4
LTC1293/LTC1294/LTC1296
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
CC
= 5.25V
q
2.0
V
V
IL
Low Level Input Voltage
V
CC
= 4.75V
q
0.8
V
I
IH
High Level Input Current
V
IN
= V
CC
q
2.5
µ
A
I
IL
Low Level Input Current
V
IN
= 0V
q
2.5
µ
A
V
OH
High Level Output Voltage
V
CC
= 4.75V, I
O
= 10mA
4.7
V
I
O
= 360
µ
A
q
2.4
4.0
V
OL
Low Level Output Voltage
V
CC
= 4.75V, I
O
= 1.6mA
q
0.4
V
I
OZ
High Z Output Leakage
V
OUT =
V
CC
,
CS High
q
3
µ
A
V
OUT
= 0V, CS High
q
3
I
SOURCE
Output Source Current
V
OUT
= 0V
20
mA
I
SINK
Output Sink Current
V
OUT
= V
CC
20
mA
I
CC
Positive Supply Current
CS High
q
6
12
mA
I
CC
Positive Supply Current
CS High,
LTC1294BC, LTC1294CC,
q
5
10
µ
A
Power
LTC1294DC, LTC1294BI,
Shutdown
LTC1294CI, LTC1294DI,
CLK Off
LTC1294BM, LTC1294CM,
q
5
15
µ
A
LTC1294DM
I
REF
Reference Current
CS High
q
10
50
µ
A
I
Negative Supply Current
CS High
q
1
50
µ
A
I
SOURCEs
SSO Source Current
V
SSO
= 0V
q
0.8
1.5
mA
I
SINKs
SSO Sink Current
V
SSO
= V
CC
q
0.5
1.0
mA
ELECTRICAL C
C
HARA TER STICS
DIGITAL A D
U
I
DC
(Note 3)
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to DGND, AGND and REF
wired
together (unless otherwise noted).
Note 3: V
CC
= 5V, V
REF+
= 5V, V
REF
= 0V, V
= 0V for unipolar mode and
5V for bipolar mode, CLK = 1.0MHz unless otherwise specified. The
q
denotes specifications which apply over the full operating temperature
range; all other limits and typicals T
A
= 25
°
C.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
mode, one LSB is equal to the bipolar input span (2V
REF
) divided by 4096.
For example, when V
REF
= 5V, 1LSB (bipolar) = 2 (5V)/4096 = 2.44mV.
Note 5: Linearity error is specified between the actual end points of the
A/D transfer curve. The deviation is measured from the center of the
quantization band.
Note 6: Recommended operating conditions.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below V
or one diode drop above V
CC
. Be careful during testing at low
V
CC
levels (4.5V), as high level reference or analog inputs (5V) can cause
this input diode to conduct, especially at elevated temperatures, and cause
errors for inputs near full scale. This spec allows 50mV forward bias of
either diode. This means that as long as the reference or analog input
does not exceed the supply voltage by more than 50mV, the output code
will be correct. To achieve an absolute 0V to 5V input voltage range will
therefore require a minimum supply voltage of 4.950V over initial
tolerance, temperature variations and loading.
Note 8: Channel leakage current is measured after the channel selection.
5
LTC1293/LTC1294/LTC1296
Supply Current vs Temperature
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
Supply Current vs Supply Voltage
SUPPLY VOLTAGE (V)
4
SUPPLY CURRENT (mA)
4
6
6
LTC1293 G01
2
0
5
10
8
CLK = 1MHz
T
A
= 25°C
AMBIENT TEMPERATURE (°C)
50
SUPPLY CURRENT (mA)
7
8
9
30
70
LTC1293 G02
6
5
30 10
50
90 110
4
3
10
10
130
CLK = 1MHz
V
CC
= 5V
REFERENCE VOLTAGE (V)
1
0.5
0.6
5
LTC1293 G03
0.4
0.3
0.1
2
3
4
0.2
0.9
0.8
OFFSET (LSB = 1/4096
×
V
REF
)
0.7
V
OS
= 0.125mV
V
CC
= 5V
V
OS
= 0.250mV
Unadjusted Offset Voltage vs
Reference Voltage
Change in Linearity vs Reference
Voltage
REFERENCE VOLTAGE (V)
0
CHANGE IN LINEARITY (LSB = 1/4096
×
V
REF
)
0.75
1.00
1.25
4
LTC1293 G04
0.50
0.25
0
1
2
3
5
Change in Gain vs Reference
Voltage
REFERENCE VOLTAGE (V)
0
1.2
CHANGE IN GAIN (LSB = 1/4096
×
V
REF
)
1.0
0.8
0.6
0.4
0.2
0
1
2
3
4
LTC1293 G05
5
V
CC
= 5V
LTC1294/6
LTC1293
Change in Offset vs Temperature
AMBIENT TEMPERATURE (°C)
50
MAGNITUDE OF OFFSET CHANGE (LSB)
0.3
0.4
0.5
50
LTC1293 G06
0.2
0.1
0
25
0
25
75
125
100
V
CC
= 5V
V
REF
= 5V
CLK = 1MHz
Change in Linearity vs
Temperature
Change in Gain vs Temperature
Minimum Clock Rate for 0.1LSB
Error
* AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (
ERROR
0.1LSB) REPRESENTS
THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED.
AMBIENT TEMPERATURE (°C)
50
MAGNITUDE OF LINEARITY CHANGE (LSB)
0.3
0.4
0.5
50
LTC1293 G07
0.2
0.1
0
25
0
25
75
125
100
V
CC
= 5V
V
REF
= 5V
CLK = 1MHz
AMBIENT TEMPERATURE (°C)
50
MAGNITUDE OF GAIN CHANGE (LSB)
0.3
0.4
0.5
50
LTC1293 G08
0.2
0.1
0
25
0
25
75
125
100
V
CC
= 5V
V
REF
= 5V
CLK = 1MHz
AMBIENT TEMPERATURE (°C)
50
MINIMUM CLK FREQUENCY* (MHz)
0.15
0.20
0.25
50
LTC1293 G09
0.10
0.05
25
0
25
75
125
100
V
CC
= 5V
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