ChipFind - Datasheet

Part Number IS71V08F32DS08

Download:  PDF   ZIP
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
PRELIMINARY INFORMATION
Rev. 00B
05/23/02
IS71V08F32
X
S08
IS71V16F32
X
S08
ISSI
®
ISSI reserves the right to make changes this specification herein and it products at any time without notice. ISSI assumes no responsibility or liability arising out of the application or use of any information,
product or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
© Copyright 2002, Integrated Silicon Solution, Inc.
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip
Package (MCP) -- 32 Mbit Simultaneous Operation Flash
Memory and 8 Mbit Static RAM
PRELIMINARY INFORMATION
MAY 2002
MCP FEATURES
·
Power supply voltage 2.7V to 3.3V
·
High performance:
Flash: 70ns maximum access time
SRAM: 70ns maximum access time
·
Package:
73-ball BGA - 32 Mbit Flash/8 Mbit SRAM
·
Operating Temperature: -40C to +85C
FLASH FEATURES
·
Power Dissipation:
Read Current at 1 Mhz: 7 mA maximum
Read Current at 5 Mhz: 18 mA maximum
Sleep Mode: 5
µ
A maximum
·
Simultaneous Read and Write Operations:
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
·
Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
·
Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
·
Sector Erase Architecture:
8 words of 4k size and 63 words of 32K size (32 Mbit)
Any combination of sectors, or the entire flash can
be simultaneously erased
·
Erase Algorithms:
Automatically preprograms/erases the flash
memory entirely, or by sector
·
Program Algorithms:
Automatically writes and verifies data at specified
address
·
Hidden ROM Region:
64KB with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
·
Data Polling and Toggle Bit:
Allow for detection of program or erase cycle
completion
·
Ready-Busy output (RY/
BY
):
Detection
of program or erase cycle completion
·
Over 100,000 write/erase cycles
·
Low supply voltage (Vccf
2.5V) inhibits writes
·
WP
/ACC input pin:
If V
IL
, allows protection of boot sectors
If V
IH
, allows removal of boot sector protection
If Vacc, program time is reduced by 40%
·
Boot sector: Top or Bottom
SRAM FEATURES (8 Mb density)
·
Power Dissipation:
Operating: 25 mA maximum
Standby: 15 µA maximum
·
Chip Selects:
CE1
s, CE2s
·
Power down feature using
CE1s
, or CE2s or
LB
s &
UB
s
·
Data retention supply voltage: 1.0 to 3.3 volt
·
Byte data control:
LB
s (DQ0­DQ7),
UB
s
(DQ8­DQ15) -- on x16 version
GENERAL DESCRIPTION
The flash and SRAM MCP is available in 32 Mbit Flash/8
Mbit SRAM having a data bus of either x8 or x16. The 32
Mbit flash is composed of 2,097,152 words of 16 bits or
4,194,304 bytes of 8 bits. Data lines DQ0-DQ7 handle the
x8 format, while lines DQ0-DQ15 handle the x16 format.
The package uses a 3.0V power supply for all operations.
No other source is required for program and erase
operations. The flash can be programmed in system
using this 3.0V supply, or can be programmed in a
standard EPROM programmer.
The 32 Mbit flash/8 Mbit SRAM is offered in a 73-pin BGA
package. The flash is compatible with the JEDEC Flash
command set standard . The flash access time is 70 ns
and the SRAM access time is 70ns.
The Flash architecture is composed of two banks which
allows simultaneous operation on each. Optimized
performance can be achieved by first initializing a program
or erase function in one bank, then immediately starting a
read from the other bank. Both operations would then be
operating simultaneously, with zero latency.
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00B
05/23/02
IS71V08F32
X
S08, IS71V16F32
X
S08
ISSI
®
LOGIC SYMBOL
GND
GND
V
CCf
RY/
BY
8Mb
Static RAM
32Mb
Flash Memory
DQ0-DQ15/A-1
A0-A20
A-1
WP
/ACC
RESET
CE
f
I/Of
SA
LB
s
UB
s
WE
OE
CE1
s
CE2s
DQ0-DQ15
A0-A18
V
CCS
MCP BLOCK DIAGRAM
A0-A20, A-1
SA
CE
f
CE1
s
CE2s
OE
WE
WP
/ACC
RESET
UB
s
LB
s
I/Of
DQ0-DQ15
22
16 or 8
RY/
BY
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
PRELIMINARY INFORMATION
Rev. 00B
05/23/02
IS71V08F32
X
S08, IS71V16F32
X
S08
ISSI
®
STATE CONTROL
&
COMMAND REGISTER
RESET
WE
CE
BYTE
WP
/ACC
DQ0-DQ15
A0-A20
A0-A20
A0-A20
A0-A20
A0-A20
Lower Bank Address
Upper Bank Address
Y -Decoder
Latches and
Control Logic
Lower
Bank
Upper
Bank
X-Decoder
Y -Decoder
Latches and
Control Logic
X-Decoder
Status
Control
DQ0-DQ15
DQ0-DQ15
DQ0-DQ15
OE
BYTE
OE
BYTE
V
CC
GND
RY/
BY
FLASH MEMORY BLOCK DIAGRAM
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00B
05/23/02
IS71V08F32
X
S08, IS71V16F32
X
S08
ISSI
®
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
PIN DESCRIPTIONS
A0-A18
Address Inputs, Common
A19-A20, A-1
Address Inputs, Flash
DQ0-DQ15/A-1
Data Inputs/Outputs
RESET
Reset
CE1
s, CE2s
Chip Selects, SRAM
I/Of
I/O Configuration, Flash
CE
f
Chip Enable Input, Flash
OE
Output Enable Input
WE
Write Enable Input
LB
s
Lower-byte Control(DQ0-DQ7), SRAM
UB
s
Upper-byte Control (DQ8-DQ15), SRAM
WP
/ACC
Write Protect/Acceleration Pin, Flash
RY/
BY
Ready/Busy Output
SA
High Order Address Pin, SRAM (x8)
NC
No Connection
Vccf
Power, Flash
Vccs
Power, SRAM
GND
Ground
123456789012345
123456789012345
123456789012345
123456789012345
123456789012345
123456789012345
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
123456789012345
123456789012345
123456789012345
123456789012345
123456789012345
123456789012345
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
PIN CONFIGURATION (32 Mb Flash and 8 Mb SRAM)
73 BALL FBGA (Top View)
1
2
3
4
5
6
7
8
9
10
A
NC
NC
B
NC
NC
NC
NC
C
NC
A7
LB
WP
/ACC
WE
A8
A11
D
A3
A6
UB
RESET
CE2s
A19
A12
A15
E
A2
A5
A18
RY/
BY
A20
A9
A13
NC
F
NC
A1
A4
A17
A10
A14
NC
NC
G
NC
A0
GND
DQ1
DQ6
SA
A16
NC
H
CE
f
OE
DQ9
DQ3
DQ4
DQ13
DQ15/A-1
I/Of
J
CE1
s
DQ0
DQ10
V
CC
f
V
CC
s
DQ12
DQ7
GND
K
DQ8
DQ2
DQ11
NC
DQ5
DQ14
L
NC
NC
NC
NC
M
NC
NC
1234
1234
1234
1234
Shared
Flash only
SRAM only
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
PRELIMINARY INFORMATION
Rev. 00B
05/23/02
IS71V08F32
X
S08, IS71V16F32
X
S08
ISSI
®
OPERATION
(1,3)
CE
f
CE
1s CE2s
OE
WE
SA
(6)
LB
s
UB
s
DQ
0-
DQ
7
DQ
8
-DQ
15
RESET WP
/ACC
(5)
Full Standby
H
H
X
X
X
X
X
X
High-Z
High-Z
H
X
H
X
L
X
X
X
X
X
High-Z
High-Z
H
X
Output Disable
H
L
H
H
H
X
X
X
High-Z
High-Z
H
X
H
L
H
X
X
X
H
H
High-Z
High-Z
H
X
L
H
X
H
H
X
X
X
High-Z
High-Z
H
X
L
X
L
H
H
X
X
X
High-Z
High-Z
H
X
Read from Flash
(2)
L
H
X
L
H
X
X
X
D
OUT
D
OUT
H
X
L
X
L
L
H
X
X
X
D
OUT
D
OUT
H
X
Write to Flash
L
H
X
H
L
X
X
X
D
IN
D
IN
H
X
L
X
L
H
L
X
X
X
D
IN
D
IN
H
X
Read from SRAM
H
L
H
L
H
X
L
L
D
OUT
D
OUT
H
X
H
L
H
L
H
X
H
L
High-Z
D
OUT
H
X
H
L
H
L
H
X
L
H
D
OUT
High-Z
H
X
Write to SRAM
H
L
H
X
L
X
L
L
D
IN
D
IN
H
X
H
L
H
X
L
X
H
L
High-Z
D
IN
H
X
H
L
H
X
L
X
L
H
D
IN
High-Z
H
X
Temporary Sector
X
X
X
X
X
X
X
X
X
X
V
ID
X
Group Unprotection
(4)
Flash Hardware
X
H
X
X
X
X
X
X
High-Z
High-Z
L
X
Re-
set
X
X
L
X
X
X
X
X
High-Z
High-Z
L
X
Boot Block Sector
X
X
X
X
X
X
X
X
X
X
X
L
Write Protection
Notes:
1. Any operations not indicated this column are inhibited.
2.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
3. Do not apply
CE
f = VIL,
CE
1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5.
WP
/ACC = VIL: protection of boot sectors.
WP
/ACC = VIH: removal of boot sectors protection.
WP
/ACC = VACC (9V): Program time will reduce by 40%.
6. SA: Don't care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
DEVICE BUS OPERATIONS
User Bus Operations (Flash=Word mode: I/Of = Vccf, SRAM= x16 version)