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Part Number IS63LV1024

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errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
IS63LV1024
ISSI
®
Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. H
10/02/00
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
· High-speed access times:
8, 10, 12 and 15 ns
· High-performance, low-power CMOS process
· Multiple center power and ground pins for
greater noise immunity
· Easy memory expansion with
CE and OE
options
·
CE power-down
· Fully static operation: no clock or refresh
required
· TTL compatible inputs and outputs
· Single 3.3V power supply
· Packages available:
­ 32-pin 300-mil SOJ
­ 32-pin 400-mil SOJ
­ 32-pin TSOP (Type II)
DESCRIPTION
The
ISSI
IS63LV1024 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024 is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When
CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
SEPTEMBER 2000
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. H
10/02/00
IS63LV1024
ISSI
®
PIN CONFIGURATION
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Bidirectional Ports
Vcc
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
­0.5 to Vcc + 0.5
V
T
BIAS
Temperature Under Bias
­55 to +125
°C
T
STG
Storage Temperature
­65 to +150
°C
P
T
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
TRUTH TABLE
Mode
WE
CE
OE
I/O Operation Vcc Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled H
L
H
High-Z
I
CC
1
, I
CC
2
Read
H
L
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
X
D
IN
I
CC
1
, I
CC
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/o7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. H
10/02/00
IS63LV1024
ISSI
®
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= ­4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
(1)
­0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
­1
1
µA
Ind.
­5
5
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
Com.
­1
1
µA
Ind.
­5
5
Notes:
1. V
IL
= ­3.0V for pulse width less than 10 ns.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.3V.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
1
Vcc Operating
V
CC
= Max.,
CE = V
IL
Com.
--
160
--
150
--
130
--
120
mA
Supply Current
I
OUT
= 0 mA, f = Max.
Ind.
--
170
--
160
--
140
--
130
I
SB
TTL Standby
V
CC
= Max.,
Com.
--
55
--
45
--
40
--
35
mA
Current
V
IN
= V
IH
or V
IL
Ind.
--
55
--
45
--
40
--
35
(TTL Inputs)
CE
V
IH
, f = Max
I
SB
1
TTL Standby
V
CC
= Max.,
Com.
--
25
--
25
--
25
--
25
mA
Current
V
IN
= V
IH
or V
IL
Ind.
--
30
--
30
--
30
--
30
(TTL Inputs)
CE
V
IH
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
5
--
5
--
5
--
5
mA
Current
CE
V
CC
­ 0.2V,
Ind.
--
10
--
10
--
10
--
10
(CMOS Inputs)
V
IN
V
CC
­ 0.2V, or
V
IN
0.2V, f = 0
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0°C to +70°C
3.3V ± 0.3V
Industrial
­40°C to +85°C
3.3V ± 0.15V
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. H
10/02/00
IS63LV1024
ISSI
®
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1a and 1b
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
8
--
10
--
12
--
15
--
ns
t
AA
Address Access Time
--
8
--
10
--
12
--
15
ns
t
OHA
Output Hold Time
2
--
2
--
3
--
3
--
ns
t
ACE
CE Access Time
--
8
--
10
--
12
--
15
ns
t
DOE
OE Access Time
--
4
--
5
--
6
--
7
ns
t
LZOE
(2)
OE to Low-Z Output
0
--
0
--
0
--
0
--
ns
t
HZOE
(2)
OE to High-Z Output
0
4
0
5
0
6
0
7
ns
t
LZCE
(2)
CE to Low-Z Output
3
--
3
--
3
--
3
--
ns
t
HZCE
(2)
CE to High-Z Output
0
4
0
5
0
6
0
7
ns
t
PU
CE to Power Up Time
0
--
0
--
0
--
0
--
ns
t
PD
CE to Power Down Time
--
8
--
10
--
12
--
15
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1
output loading specified in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Figure 1
OUTPUT
V
T
= 1.5V
Z
OUT
= 50
50
317
5 pF
Including
jig and
scope
351
OUTPUT
3.3V
Figure 2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. H
10/02/00
IS63LV1024
ISSI
®
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2
(1,3)
Notes:
1.
WE is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE = V
IL
.
3. Address is valid prior to or coincident with
CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)