1
TM
File Number
8017.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
P RE L I M I N A RY
ISL3874A
Wireless LAN Integrated Medium Access
Controller with Baseband Processor with
Mini-PCI
The Intersil ISL3874A Wireless LAN
Integrated Medium Access Controller
with Integrated Baseband Processor
is part of the PRISM® 2.4GHz radio
chip set. The ISL3874A directly interfaces with the Intersil's
IF QMODEM (HFA3783). Adding Intersil's RF/IF Converter
(ISL3685) and Intersil's Power Amp (HFA3983/4/5) offers
the designer a complete end-to-end WLAN Chip Set
solution. Protocol and PHY support are implemented in
firmware.
Firmware implements the full IEEE 802.11B Wireless LAN
MAC protocol. It supports BSS and IBSS operation under
DCF, and operation under the optional Point Coordination
Function (PCF). Low level protocol functions such as
RTS/CTS generation and acknowledgment, fragmentation
and de-fragmentation, and automatic beacon monitoring are
handed without host intervention. Active scanning is
performed autonomously once initiated by host command.
Host interface command and status handshakes allow
concurrent operations from multi-threaded I/O drivers.
Additional firmware functions specific to access point
applications are also available.
The ISL3874A has on-board A/Ds and D/A for analog I and
Q inputs and outputs, for which the HFA3783 IF QMODEM is
recommended. Differential phase shift keying modulation
schemes DBPSK and DQPSK, with data scrambling
capability, are available along with Complementary Code
Keying to provide a variety of data rates. Both Receive and
Transmit AGC functions with 7-bit AGC control obtain
maximum performance in the analog portions of the
transceiver.
Built-in flexibility allows the ISL3874A to be configured
through a general purpose control bus, for a range of
applications. The ISL3874A is housed in a thin plastic BGA
package suitable for mini PCI board applications.
The ISL3874A is designed to provide maximum
performance with minimum power consumption. External pin
layout is organized to provide optimal PC board layout to all
user interfaces including mini PCI.
Features
· Start up modes allow the PCI and mini PCI Card
Information Structure to be initialized from a serial
EEPROM. This Allows Firmware to be Downloaded from
the Host, Eliminating the Parallel Flash Memory Device
· Firmware Can Be Loaded from Serial Flash Memory
· Zero Glue Connection to 16-Bit Wide SRAM Devices
· Low Frequency Crystal Oscillator to Maintain Time and
Allow Baseband Clock Source to Power Off During Sleep
Mode
· High Performance Internal WEP Engine supporting upto
128 bit WEP
· Debug Mode Support Tracing Execution from On-Chip
Memory
· Programmable MBUS Cycle Extension Allows Accessing
of Slow Memory Devices without Slowing the Clock
· Complete DSSS Baseband Processor
· RAKE Receiver with Decision Feedback Equalizer
· Processing Gain . . . . . . . . . . . . . . . . . . . . .FCC Compliant
· Programmable Data Rate . . . . . . . .1, 2, 5.5, and 11Mbps
· Ultra Small Package. . . . . . . . . . . . . . . . . . 14mm x 14mm
· Single Supply Operation . . . . . . . . . . . . . . . . 2.7V to 3.6V
· Modulation Methods. . . . . . . . DBPSK, DQPSK, and CCK
· Supports Full or Half Duplex Operations
· On-Chip A/ D and D/A Converters for I/Q Data (6-Bit,
22MSPS), AGC, and Adaptive Power Control (7-Bit)
· Targeted for Multipath Delay Spreads 125ns at 11Mbps,
250ns at 5.5Mbps
· Supports Short Preamble and Antenna Diversity
· Designed to meet the Specification for PCI V2.2 and mini
PCI V1.2
Applications
· Enterprise WLAN Systems
· PCI Card Wireless LAN Adapters
· PCN / Wireless PBX / Wireless Local Loop
· High Data Rate Wireless LAN Systems Targeting IEEE
802.11b Standard
· Wireless LAN Access Points and Bridge Products
· Spread Spectrum WLAN RF Modems
· TDMA or CSMA Packet Protocol Radios
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PART
NUMBER
ISL3874AIK
-40 to 85
192 BGA
V192.14x14
ISL3874AIK-TK
-40 to 85
Tape and Reel 1000 Units /Reel
Data Sheet
August 2001
PRISM® is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc.
2
Simplified Block Diagram
PHY
SERIAL
CONTROL
(MMI)
PRISM RADIO
RADIO AND SYNTH
MICRO-
PROGRAMMED
MAC ENGINE
MEMORY
WEP
ENGINE
PCI/CARD BUS 32
ON-CHIP
RAM
44MHz CLOCK
DATA
ADDRESS
SELECT
EXTERNAL
SRAM AND
FLASH
MEMORY
HOST
COMPUTER
DATA
ADDRESS
CONTROL
ON-CHIP
ROM
RF SECTION
SERIAL CONTROL
INTERFACE
(MDI)
CONTROLLER
HOST
INTERFACE
6
7
6
6
6
6
7
1
1
ANT_SEL
RX_RF_AGC
RX_IF_DET
THRESH.
IF
DAC
I ADC
Q ADC
BASEBAND PROCESSOR
TX
ALC
TX
ADC
I DAC
Q DAC
MOD
I/O
DEMOD
AGC
V
REF
RX_Q
±
RX_I
±
RX_IF_AGC
TX_Q
±
TX_I
±
TX_IF_AGC
TX_AGC_IN
DATA I/O
DETECT
CTL
TX
DAC
MEDIUM ACCESS
ISL3874A
.
SOURCE
CONTROLLER
ISL3874A
3
ISL3874A Signal Descriptions
TABLE 1. HOST INTERFACE PINS
PIN NAME
PIN
NUMBER
PIN I/O TYPE
DESCRIPTION
HAD31
A8
5V Tol, CMOS, BiDir PCI address/data bus bit 31. These signals make up the multiplexed PCI address and data bus on
the primary interface. During the address phase of a primary bus PCI cycle, HAD31-HAD0 contain a
32-bit address or other destination information. During the data phase, HAD31-HAD0 contain data.
HAD30
A9
5V Tol, CMOS, BiDir
PCI address/data bus bit 30.
HAD29
C8
5V Tol, CMOS, BiDir PCI address/data bus bit 29.
HAD28
A10
5V Tol, CMOS, BiDir PCI address/data bus bit 28.
HAD27
B9
5V Tol, CMOS, BiDir PCI address/data bus bit 27.
HAD26
B10
5V Tol, CMOS, BiDir PCI address/data bus bit 26.
HAD25
C9
5V Tol, CMOS, BiDir PCI address/data bus bit 25.
HAD24
A11
5V Tol, CMOS, BiDir PCI address/data bus bit 24.
HAD23
B11
5V Tol, CMOS, BiDir PCI address/data bus bit 23.
HAD22
B12
5V Tol, CMOS, BiDir PCI address/data bus bit 22.
HAD21
A12
5V Tol, CMOS, BiDir PCI address/data bus bit 21.
HAD20
A13
5V Tol, CMOS, BiDir PCI address/data bus bit 20.
HAD19
C12
5V Tol, CMOS, BiDir PCI address/data bus bit 19.
HAD18
A14
5V Tol, CMOS, BiDir PCI address/data bus bit 18.
HAD17
C13
5V Tol, CMOS, BiDir PCI address/data bus bit 17.
HAD16
C14
5V Tol, CMOS, BiDir PCI address/data bus bit 16.
HAD15
E14
5V Tol, CMOS, BiDir PCI address/data bus bit 15.
HAD14
E15
5V Tol, CMOS, BiDir PCI address/data bus bit 14.
HAD13
F16
5V Tol, CMOS, BiDir PCI address/data bus bit 13.
HAD12
F15
5V Tol, CMOS, BiDir PCI address/data bus bit 12.
HAD11
F14
5V Tol, CMOS, BiDir PCI address/data bus bit 11.
HAD10
G16
5V Tol, CMOS, BiDir PCI address/data bus bit 10.
HAD9
G15
5V Tol, CMOS, BiDir PCI address/data bus bit 9.
HAD8
G14
5V Tol, CMOS, BiDir PCI address/data bus bit 8.
HAD7
H15
5V Tol, CMOS, BiDir PCI address/data bus bit 7.
HAD6
G13
5V Tol, CMOS, BiDir PCI address/data bus bit 6.
HAD5
J15
5V Tol, CMOS, BiDir PCI address/data bus bit 5.
HAD4
J14
5V Tol, CMOS, BiDir PCI address/data bus bit 4.
HAD3
K14
5V Tol, CMOS, BiDir PCI address/data bus bit 3.
HAD2
K15
5V Tol, CMOS, BiDir PCI address/data bus bit 2.
HAD1
L14
5V Tol, CMOS, BiDir PCI address/data bus bit 1.
HAD0
L16
5V Tol, CMOS, BiDir PCI address/data bus bit 0.
HBE3
C10
5V Tol, CMOS, BiDir PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, HBE3-HBE0 define the bus command. During
the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths
of the full 32-bit data bus carry meaningful data. HBE3 applies to byte 3 (HAD31-HAD24).
HBE2
B14
5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE2 applies to byte 2 (HAD23-HAD16).
HBE1
E16
5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE1 applies to byte 1 (HAD15-HAD8).
ISL3874A
4
HBE0
H16
5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE0 applies to byte 0 (HAD7-HAD0).
HINTA
C6
CMOS, Output
PCI Bus Interrupt A
HRESET
D6
5V Tol, CMOS, Input
PCI reset.
HFRAME
B15
5V Tol, BiDir
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
FRAME is deasserted, the PCI bus transaction is in the final data phase.
HIRDY
A15
5V Tol, CMOS, BiDir PCI initiator ready. HIRDY indicates the PCI bus initiators ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK where both HIRDY and
HTRDY are asserted. Until HIRDY and HTRDY are both sampled asserted, wait states are inserted.
HTRDY
A16
5V Tol, CMOS, BiDir PCI target ready. HTRDY indicates the primary bus targets ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of PCLK when both HIRDY
and HTRDY are asserted. Until both HIRDY and HTRDY are asserted, wait states are inserted.
HREQ
B7
CMOS, Output
PCI bus request. HREQ is asserted by the ISL3874 to request access to the PCI bus as an initiator.
HSERR
B16
CMOS, Output
PCI system error. HSERR is an output that is pulsed from the ISL3874 when enabled through the
command register indicating a system error has occurred. The ISL3874 need not be the target of
the PCI cycle to assert this signal. When HSERR is enabled in the control register, this signal also
pulses, indicating that an address parity error has occurred on a CardBus interface.
HSTOP
C16
5V Tol, CMOS, BiDir PCI cycle stop signal. HSTOP is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. HSTOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
HDEVSEL
D15
5V Tol, CMOS, BiDir PCI device select. The ISL3874 asserts HDEVSEL to claim a PCI cycle as the target device. As a
PCI initiator on the bus, the ISL3874 monitors HDEVSEL until a target responds. If no target
responds before timeout occurs, the ISL3874 terminates the cycle with an initiator abort.
HPERR
D16
5V Tol, CMOS, BiDir PCI bus parity. In all PCI bus read and write cycles, the ISL3874 calculates even parity across the
HD31-HAD0 and BE3-BE0 buses. As an initiator during PCI cycles, the ISL3874 outputs this parity
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared
to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR).
HGNT
C7
5V Tol, CMOS, ST
Input
PCI bus grant. HGNT is driven by the PCI bus arbiter to grant the ISL3874 access to the PCI bus
after the current data transaction has completed. HGNT may or may not follow a PCI bus request,
depending on the PCI bus parking algorithm.
HPCLK
A7
5V Tol, CMOS,
Input
HPCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
HPAR
B13
5V Tol, CMOS, BiDir PCI bus parity.
HIDSEL
C11
5V Tol, CMOS,
Input
Initialization device select. HIDSEL selects the ISL3874 during configuration space accesses.
HIDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
HPME
B8
CMOS, Output
Power Management Event Output. HPME provides output for PME signals.
TABLE 1. HOST INTERFACE PINS (Continued)
PIN NAME
PIN
NUMBER
PIN I/O TYPE
DESCRIPTION
ISL3874A
5
TABLE 2. MEMORY INTERFACE PINS
PIN NAME
PIN NUMBER
PIN I/O TYPE
DESCRIPTION
PL4-MA19
A4
CMOS BiDir, 2mA
MBUS Address Bit 19, needed to address between 512KB and 1MB
of data store
MA18
A3
CMOS BiDir, 2mA
MBUS Address Bit 18
MA17
B4
CMOS BiDir, 2mA
MBUS Address Bit 17
MA16
C3
CMOS TS Output, 2mA
MBUS Address Bit 16
MA15
B3
CMOS TS Output, 2mA
MBUS Address Bit 15
MA14
A1
CMOS TS Output, 2mA
MBUS Address Bit 14
MA13
C2
CMOS TS Output, 2mA
MBUS Address Bit 13
MA12
E3
CMOS TS Output, 2mA
MBUS Address Bit 12
MA11
B1
CMOS TS Output, 2mA
MBUS Address Bit 11
MA10
D2
CMOS TS Output, 2mA
MBUS Address Bit 10
MA9
D3
CMOS TS Output, 2mA
MBUS Address Bit 9
MA8
C1
CMOS TS Output, 2mA
MBUS Address Bit 8
MA7
F4
CMOS TS Output, 2mA
MBUS Address Bit 7
MA6
E2
CMOS TS Output, 2mA
MBUS Address Bit 6
MA5
D1
CMOS TS Output, 2mA
MBUS Address Bit 5
MA4
F2
CMOS TS Output, 2mA
MBUS Address Bit 4
MA3
E1
CMOS TS Output, 2mA
MBUS Address Bit 3
MA2
F3
CMOS TS Output, 2mA
MBUS Address Bit 2
MA1
F1
CMOS TS Output, 2mA
MBUS Address Bit 1
MA0 / MWEH-
G2
CMOS TS Output, 2mA, 50K Pull Up
MBUS Write Enable, high byte. Asserted on writes to the high-order
byte of x16 memory devices that use the JEDEC 4-wire control
interface. Also asserted (as MA[0]) when accessing the odd (high-
order) byte of a word stored in a x8 memory device. During word
accesses of x8 memory, the odd byte is accessed first.
MD15
H4
CMOS, BiDir, 2mA, 50K Pull Up
MBUS Data Bit 15
MD14
G1
CMOS, BiDir, 2mA, 50K Pull Up
MBUS Data Bit 14
MD13
H3
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 13
MD12
H2
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 12
MD11
H1
CMOS, BiDir, 2mA, 50K Pull Up
MBUS Data Bit 11
MD10
J3
CMOS, BiDir, 2mA, 50K Pull Up
MBUS Data Bit 10
MD9
M1
CMOS, BiDir, 2mA, 50K Pull Up
MBUS Data Bit 9
MD8
M3
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 8
MD7
M2
CMOS, BiDir, 2mA 50K Pull Down
MBUS Data Bit 7
MD6
N1
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 6
MD5
N3
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 5
MD4
P1
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 4
MD3
N2
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 3
MD2
P3
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 2
MD1
R1
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 1
MD0
P2
CMOS, BiDir, 2mA, 50K Pull Down
MBUS Data Bit 0
ISL3874A
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