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Part Number ICL7126

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1
®
FN3084.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICL7126
3 1/2 Digit, Low Power, Single Chip A/D
Converter
The ICL7126 is a high performance, very low power
3
1
/
2
-digit, A/D converter. All the necessary active devices
are contained on a single CMOS IC, including seven
segment decoders, display drivers, reference, and clock. The
ICL7126 is designed to interface with a liquid crystal display
(LCD) and includes a backplane drive. The supply current of
100
µ
A is ideally suited for 9V battery operation.
The ICL7126 brings together an unprecedented combination
of high accuracy, versatility, and true economy. It features
auto-zero to less than 10
µ
V, zero drift of less than 1
µ
V/
o
C,
input bias current of 10pA maximum, and rollover error of
less than one count. The versatility of true differential input
and reference is useful in all systems, but gives the designer
an uncommon advantage when measuring load cells, strain
gauges and other bridge-type transducers. And finally the
true economy of single power operation allows a high
performance panel meter or multi-meter to be built with the
addition of only 10 passive components and a display.
The ICL7126 can be used as a plug-in replacement for the
ICL7106 in a wide variety of applications, changing only the
passive components.
Features
· 8,000 Hours Typical 9V Battery Life
· Guaranteed Zero Reading for 0V Input on All Scales
· True Polarity at Zero for Precise Null Detection
· 1pA Typical Input Current
· True Differential Input and Reference
· Direct LCD Display Drive - No External Components
Required
· Pin Compatible With the ICL7106
· Low Noise - Less Than 15
µ
V
P-P
· On-Chip Clock and Reference
· Low Power Dissipation Guaranteed Less Than 1mW
· No Additional Active Circuits Required
·
Pb-Free Available (RoHS Compliant)
Pinout
ICL7126 (PDIP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
ICL7126CPL
0 to 70
40 Ld PDIP
E40.6
ICL7126CPLZ
(Note 1)
0 to 70
40 Ld PDIP
(Pb-free) (Note 2)
E40.6
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020C.
2. Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2 (10s)
C3
A3
G3
BP/GND
(1s)
(10s)
(100s)
(MINUS)
(100s)
Data Sheet
October 25, 2004
2
FN3084.5
ICL7126
Absolute Maximum Ratings
Thermal Information
Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . .V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . .V+ to V-
Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
NOTE: Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to
±
100
µ
A.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V
REF
= 100mV, f
CLOCK
= 48kHz (Notes 1, 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Zero Input Reading
V
IN
= 0.0V, Full Scale = 200mV
-000.0
±
000.0
+000.0
Digital
Reading
Ratiometric Reading
V
lN
= V
REF
, V
REF
= 100mV
999
999/100
0
1000
Digital
Reading
Rollover Error
-V
IN
= +V
lN
200mV
Difference in Reading for Equal Positive and Negative
Inputs Near Full Scale
-
±
0.2
±
1
Counts
Linearity
Full Scale = 200mV or Full Scale = 2V Maximum Deviation
from Best Straight Line Fit (Note 5)
-
±
0.2
±
1
Counts
Common Mode Rejection Ratio
V
CM
=
±
1V, V
IN
= 0V, Full Scale = 200mV (Note 5)
-
50
-
µ
V/V
Noise
V
IN
= 0V, Full Scale = 200mV
(Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5)
-
15
-
µ
V
Leakage Current Input
V
lN
= 0V (Note 5)
-
1
10
pA
Zero Reading Drift
V
lN
= 0V, 0
o
C To
70
o
C (Note 5)
-
0.2
1
µ
V/
o
C
Scale Factor Temperature Coefficient
V
IN
= 199mV, 0
o
C To
70
o
C
,
(Ext. Ref. 0ppm/×
o
C) (Note 5)
-
1
5
ppm/
o
C
V+ Supply Current
V
IN
= 0V (Does Not Include COMMON Current)
-
70
100
µ
A
COMMON Pin Analog Common Voltage
25k
Between Common and Positive Supply
(With Respect to + Supply)
2.4
3.0
3.2
V
Temperature Coefficient of Analog Common
25k
Between Common and Positive Supply
(With Respect to + Supply) (Note 5)
-
80
-
ppm/
o
C
Peak-To-Peak Segment Drive Voltage
Peak-To-Peak Backplane Drive Voltage
V+ = to V- = 9V (Note 4)
4
5.5
6
V
Power Dissipation Capacitance
vs Clock Frequency
-
40
-
pF
NOTES:
3. Unless otherwise noted, specifications are tested using the circuit of Figure 1.
4. Back plane drive is in phase with segment drive for `off' segment, 180 degrees out of phase for `on' segment. Frequency is 20 times conversion
rate. Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
3
FN3084.5
Typical Application Schematics
FIGURE 1. ICL7126 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED
FOR 200mV FULL SCALE
FIGURE 2. ICL7126 CLOCK FREQUENCY 16kHz, 1 READING/S
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
PO
L
OSC 1
OSC 2
OSC 3
TES
T
REF HI
REF LO
C
RE
F
+
C
REF
-
COM
IN HI
IN LO
A-
Z
BU
F
F
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+
-
IN
R
5
R
2
ICL7126
240k
10k
18
0k
50pF
0.1
µ
F
1M
0.
01
0.22
µ
F
18
0k
0.04
7
µ
F
75
0
C
1
= 0.1
µ
F
C
2
= 0.22
µ
F
C
3
= 0.047
µ
F
C
4
= 50pF
C
5
= 0.01
µ
F
R
1
= 240k
R
2
= 180k
R
3
= 180k
R
4
= 10k
R
5
= 1M
9V
+
-
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TES
T
REF HI
REF LO
C
RE
F
+
C
REF
-
COM
IN HI
IN LO
A-Z
BU
F
F
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+
-
IN
R
5
R
2
9V
ICL7126
240k
10k
18
0k
50pF
0.1
µ
F
1M
0.
01
0.
3
3
µ
F
18
0k
0.15
µ
F
SET REF = 100.0mV
C
1
= 0.1
µ
F
C
2
= 0.33
µ
F
C
3
= 0.5
µ
F
C
4
= 50pF
C
5
= 0.01
µ
F
R
1
= 240k
R
2
= 180k
R
3
= 180k
R
4
= 10k
R
5
= 1M
+
-
ICL7126
4
FN3084.5
FIGURE 3. CLOCK FREQUENCY 48kHz, 3 READINGS/S
Typical Application Schematics
(Continued)
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
PO
L
OS
C
1
OS
C
2
OS
C
3
TEST
REF
HI
RE
F LO
C
REF
+
C
RE
F
-
COM
IN
H
I
IN LO
A-
Z
BU
F
F
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+
-
IN
R
5
R
2
9V
ICL7126
240k
10k
18
0k
50pF
0.1
µ
F
1M
0.
0
1
0.22
µ
F
1
80k
0.0
4
7
µ
F
75
0
C
1
= 0.1
µ
F
C
2
= 0.22
µ
F
C
3
= 0.047
µ
F
C
4
= 50pF
C
5
= 0.01
µ
F
R
1
= 240k
R
2
= 180k
R
3
= 180k
R
4
= 10k
R
5
= 1M
+
-
ICL7126
5
FN3084.5
Typical Integrator Amplifier Output Waveform (INT Pin)
Design Information Summary Sheet
· OSCILLATOR FREQUENCY
f
OSC
= 0.45/RC
C
OSC
> 50pF; R
OSC
> 50k
f
OSC
(Typ) = 48kHz
· OSCILLATOR PERIOD
t
OSC
= RC/0.45
· INTEGRATION CLOCK FREQUENCY
f
CLOCK
= f
OSC
/4
· INTEGRATION PERIOD
t
INT
= 1000 x (4/f
OSC
)
· 60/50Hz REJECTION CRITERION
t
INT
/t
60Hz
or t
lNT
/t
50Hz
= Integer
· OPTIMUM INTEGRATION CURRENT
I
INT
= 4
µ
A
· FULL-SCALE ANALOG INPUT VOLTAGE
V
lNFS
(Typ) = 200mV or 2V
· INTEGRATE RESISTOR
· INTEGRATE CAPACITOR
· INTEGRATOR OUTPUT VOLTAGE SWING
· V
INT
MAXIMUM SWING:
(V- + 0.5V) < V
INT
< (V+ - 0.5V), V
INT
(Typ) = 2V
· DISPLAY COUNT
· CONVERSION CYCLE
t
CYC
= t
CL0CK
x 4000
t
CYC
= t
OSC
x 16,000
when f
OSC
= 48KHz; t
CYC
= 333ms
· COMMON MODE INPUT VOLTAGE
(V- + 1V) < V
lN
< (V+ - 0.5V)
· AUTO-ZERO CAPACITOR
0.01
µ
F < C
AZ
< 1
µ
F
· REFERENCE CAPACITOR
0.1
µ
F < C
REF
< 1
µ
F
· V
COM
Biased between V+ and V-
· V
COM
V+ - 2.8V
Regulation lost when V+ to V- <
6.8V;
If V
COM
is externally pulled down to (V + to V -)/2,
the V
COM
circuit will turn off
· ICL7126 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
V
TEST
V+ - 4.5V
· ICL7126 DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude
R
INT
V
INFS
I
INT
-----------------
=
C
INT
t
INT
(
)
I
INT
(
)
V
INT
--------------------------------
=
V
INT
t
INT
(
)
I
INT
(
)
C
INT
--------------------------------
=
COUNT
1000
V
IN
V
REF
---------------
×
=
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x t
CLOCK
= 16,000 x t
OSC
ICL7126