2-252

HIP6019

Advanced Dual PWM and Dual Linear
Power Control

The HIP6019 provides the power control and protection for four
output voltages in high-performance microprocessor and
computer applications. The IC integrates two PWM controllers,
a linear regulator and a linear controller as well as the
monitoring and protection functions into a single 28 lead SOIC
package. One PWM controller regulates the microprocessor
core voltage with a synchronous-rectified buck converter, while
the second PWM controller supplies the computer's 3.3V power
with a standard buck converter. The linear controller regulates
power for the GTL bus and the linear regulator provides power
for the clock driver circuits.

The HIP6019 includes an Intel-compatible, TTL 5-input digital-
to-analog converter (DAC) that adjusts the core PWM output
voltage from 2.1V

to 3.5V

in 0.1V increments and from

1.8V

to 2.05V

in 0.05V steps. The precision reference

and voltage-mode control provide

1% static regulation. The

second PWM controller is user-adjustable for output levels
between 3.0V and 3.5V with

2% accuracy. The adjustable

linear regulator uses an internal pass device to provide 2.5V

2.5%. The adjustable linear controller drives an external N-

Channel MOSFET to provide 1.5V

2.5%.

The HIP6019 monitors all the output voltages. A single Power
Good signal is issued when the core is within

10% of the DAC

setting and the other levels are above their under- voltage
levels. Additional built-in over-voltage protection for the core
output uses the lower MOSFET to prevent output voltages
above 115% of the DAC setting. The PWM controller's over-
current functions monitor the output current by sensing the
voltage drop across the upper MOSFET's r

DS(ON)

, eliminating

the need for a current sensing resistor.

Pinout

HIP6019 (SOIC)

TOP VIEW

Features

ˇ Provides 4 Regulated Voltages

- Microprocessor Core, I/O, Clock Chip and GTL Bus

ˇ Drives N-Channel MOSFETs

ˇ Operates from +5V and +12V Inputs

ˇ Simple Single-Loop Control Designs

- Voltage-Mode PWM Control

ˇ Fast Transient Response

- High-Bandwidth Error Amplifiers

- Full 0% to 100% Duty Ratios

ˇ Excellent Output Voltage Regulation

- Core PWM Output:

1% Over Temperature

- I/O PWM Output:

2% Over Temperature

- Other Outputs:

2.5% Over Temperature

ˇ TTL-Compatible 5-Bit Digital-to-Analog Core Output

Voltage Selection

- Wide Range . . . . . . . . . . . . . . . . . . . 1.8V

to 3.5V

- 0.1V Steps . . . . . . . . . . . . . . . . . . . . 2.1V

to 3.5V

- 0.05V Steps . . . . . . . . . . . . . . . . . . 1.8V

to 2.05V

ˇ Power-Good Output Voltage Monitor

ˇ Microprocessor Core Voltage Protection Against Shorted

MOSFET

ˇ Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET's r

DS(ON)

ˇ Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator; Programmable from

50kHz to 1MHz

Applications

ˇ Full Motherboard Power Regulation for Computers

ˇ Low-Voltage Distributed Power Supplies

UGATE2

PHASE2

VID4

VID3

FB2

COMP2

FAULT/RT

FB4

PGND

LGATE1

PHASE1

GATE3

COMP1

GND

VOUT4

VSEN2

UGATE1

PGOOD

VID2

OCSET2

VSEN1

FB3

VID1

VID0

OCSET1

FB1

Ordering Information

PART NUMBER

TEMP. (

PACKAGE

PKG. NO.

HIP6019CB

0 to 70

28 Ld SOIC

M28.3

HIP6019EVAL1

Evaluation Board

Data Sheet

April 1998

File Number

4490.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

2-253

HIP6019

Block Diagram

0.25A

SOFT

115%

110%

90%

INHIBIT

PWM

COMP1

ERR

AMP1

VCC

PGOOD

PWM1

GND

VSEN1

OCSET1

VID0

VID1

VID2

VID3

FB1

COMP1

COUT

UGA

TE1

PHASE1

200

VID4

LGA

TE1

PGND

OUT4

TE3

FB3

FB2

COMP2

INHIBIT

PWM2

TE2

PHASE2

ERR

AMP2

PWM

COMP2

200

OCSET2

VSEN2

T / R

0.3V

CONTR

1.26V

WER-ON

RESET (POR)

TTL D/A

CONVER

TER

)

OSCILLA

CONTR

VCC

AND F

LOGIC

2.5V

WER

DRIVE

DRIVE1

DRIVE2

4.3V

VSEN2

1.26V

UNDER-

LTA

FB4

LINEAR

LUV

OC2

OC1

OC4

FIGURE 1.

2-255

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

PGOOD, RT/FAULT, and GATE Voltage. . . . GND - 0.3V to V

+ 0.3V

Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Operating Conditions

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V

10%

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0

C to 70

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0

C to 125

Thermal Resistance (Typical, Note 1)

(

C/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOIC Package (with 3 in

of copper) . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted.
Refer to Figures 1, 2 and 3

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply

UGATE1, GATE2, GATE3, LGATE1, and
VOUT4 Open

POWER-ON RESET

Rising VCC Threshold

OCSET

= 4.5V

8.6

10.4

Falling VCC Threshold

OCSET

= 4.5V

8.2

10.2

Rising V

OCSET1

Threshold

1.25

OSCILLATOR

Free Running Frequency

RT = OPEN

185

200

215

kHz

Total Variation

< RT to GND < 200k

-15

+15

Ramp Amplitude

OSC

RT = Open

1.9

P-P

REFERENCE AND DAC

DAC(VID0-VID4) Input Low Voltage

0.8

DAC(VID0-VID4) Input High Voltage

2.0

DACOUT Voltage Accuracy

-1.0

+1.0

Reference Voltage
(Pin FB2, FB3, and FB4)

1.240

1.265

1.290

LINEAR REGULATOR

Regulation

10mA < I

VOUT4

< 150mA

-2.5

2.5

Under-Voltage Level

FB4

FB4 Rising

Under-Voltage Hysteresis

Over-Current Protection

180

230

Over-Current Protection During Start-Up

Voltage < 4V

560

700

LINEAR CONTROLLER

Regulation

VSEN3 = GATE3

-2.5

2.5

Under-Voltage Level

FB3

FB3 Rising

Under-Voltage Hysteresis

HIP6019

2-256

PWM CONTROLLER ERROR AMPLIFIERS

DC Gain

Gain-Bandwidth Product

GBWP

MHz

Slew Rate

COMP = 10pF

PWM CONTROLLER GATE DRIVERS

Drive1 (and 2) Source

UGATE

VCC = 12V, V

UGATE1

(or V

GATE2

) = 6V

Drive1 (and 2) Sink

UGATE

GATE-PHASE

= 1V

1.7

3.5

Lower Gate Source

LGATE

VCC = 12V, V

LGATE

= 1V

Lower Gate Sink

LGATE

GATE

= 1V

1.4

3.0

PROTECTION

OUT1

Over-Voltage Trip

VSEN1 Rising

112

115

118

OUT2

Over-Voltage Trip

VSEN2 Rising

4.1

4.3

4.5

VSEN2 Input Resistance

FAULT Sourcing Current

OVP

FAULT/RT

= 10.0V

OCSET1(and 2) Current Source

OCSET

= 4.5V

170

200

230

Soft-Start Current

Chip Shutdown Soft-Start Threshold

1.0

POWER GOOD

OUT1

Upper Threshold

VSEN1 Rising

108

110

OUT1

Under-Voltage

VSEN1 Rising

OUT1

Hysteresis

Upper/Lower Threshold

OUT2

Under-Voltage

VSEN2 Rising

2.45

2.55

2.65

OUT2

Under-Voltage Hysteresis

100

PGOOD Voltage Low

PGOOD

= -4mA

0.5

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted.
Refer to Figures 1, 2 and 3 (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Typical Performance Curves

FIGURE 4. R

RESISTANCE vs FREQUENCY

FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY

100

1000

SWITCHING FREQUENCY (kHz)

RESIST

ANCE (k

)

100

1000

PULLUP

TO +12V

PULLDOWN TO V

GATE

= 660pF

GATE

= 1500pF

GATE

= 3600pF

GATE

= 4800pF

(mA)

SWITCHING FREQUENCY (kHz)

140

120

100

200

300

400

500

600

700

800

900

1000

UGATE1

= C

UGATE2

= C

LGATE1

= C

GATE

VCC

= 12V,V

= 5V

HIP6019

2-257

Functional Pin Description

VSEN1, VSEN2 (Pins 22 and 15)

These pins are connected to the PWM converters' output
voltages. The PGOOD and OVP comparator circuits use
these signals to report output voltage status and for over-
voltage protection. VSEN2 provides the input power to the
integrated linear regulator.

OCSET1, OCSET2 (Pins 23 and 9)

Connect a resistor (R

OCSET

) from this pin to the drain of the

respective upper MOSFET. R

OCSET

, an internal 200

current source (I

OCSET

), and the upper MOSFET on-

resistance (r

DS(ON)

) set the converter over-current (OC) trip

point according to the following equation:

An over-current trip cycles the soft-start function. Sustaining an
over-current for 2 soft-start intervals shuts down the controller.

Additionally, OCSET1 is an output for the inverted FAULT
signal (FAULT). If a fault condition causes FAULT to go high,
OCSET1 will be simultaneously pulled to ground though an
internal MOS device (typical r

DS(ON)

= 100

SS (Pin 12)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 11

A current source, sets the soft-

start interval of the converter.

Pulling this pin low (typically below 1.0V) with an open drain
signal will shutdown the IC.

VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)

VID0-4 are the input pins to the 5-bit DAC. The states of these
five pins program the internal voltage reference (DACOUT).
The level of DACOUT sets the core converter output voltage
(V

OUT1

). It also sets the core PGOOD and OVP thresholds.

COMP1, COMP2, and FB1, FB2
(Pins 20, 11, 21, and 10)

COMP1, 2 and FB1, 2 are the available external pins of the
PWM error amplifiers. Both the FB pins are the inverting
input of the error amplifiers. Similarly, the COMP pins are the
error amplifier outputs. These pins are used to compensate
the voltage-control feedback loops of the PWM converters.

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured with
respect to this pin.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate the
status of the PWM converter output voltages. This pin is
pulled low when the core output is not within

10% of the

DACOUT reference voltage, or when any of the other
outputs are below their under-voltage thresholds.

The PGOOD output is open for VID codes that inhibit
operation. See Table 1.

PHASE1, PHASE2 (Pins 26 and 2)

Connect the PHASE pins to the respective PWM
converter's upper MOSFET source. These pins are used to
monitor the voltage drop across the upper MOSFETs for
over-current protection.

UGATE1, UGATE2 (Pins 27 and 1)

Connect UGATE pins to the respective PWM converter's
upper MOSFET gate. These pins provide the gate drive for
the upper MOSFETs.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous
PWM converter's lower MOSFET source to this pin.

LGATE1 (Pin 25)

Connect LGATE1 to the synchronous PWM converter's lower
MOSFET gate. This pin provides the gate drive for the lower
MOSFET.

VCC (Pin 28)

Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC.

FAULT/RT (Pin 13)

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R

) from this pin to GND, the nominal

200kHz switching frequency is increased according to the
following equation:

Conversely, connecting a pull-up resistor (R

) from this pin

to VCC reduces the switching frequency according to the
following equation:

Nominally, this pin voltage is 1.26V, but is pulled to VCC in
the event of an over-voltage or over-current condition.

GATE3 (Pin 18)

Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the linear controller's pass transistor.

FB3 (Pin 19)

Connect this pin to a resistor divider to set the linear
controller output.

VOUT4 (Pin 16)

Output of the linear regulator. Supplies current up to 230mA.

PEAK

OCSET

DS ON

(

)

----------------------------------------------------

200kHz

(

)

---------------------

to GND)

200kHz

(

)

---------------------

to 12V)

HIP6019

2-258

FB4 (Pin 14)

Connect this pin to a resistor divider to set the linear
regulator output.

Description

Operation

The HIP6019 monitors and precisely controls 4 output
voltage levels (Refer to Figures 1, 2, and 3). It is designed for
microprocessor computer applications with 5V power and
12V bias input from a PS2 or ATX power supply. The IC has
2 PWM controllers, a linear controller, and a linear regulator.
The first PWM controller (PWM1) is designed to regulate the
microprocessor core voltage (V

OUT1

). PWM1 controller

drives 2 MOSFETs (Q1 and Q2) in a synchronous-rectified
buck converter configuration and regulates the core voltage
to a level programmed by the 5-bit digital-to-analog
converter (DAC). The second PWM controller (PWM2) is
designed to regulate the I/O voltage (V

OUT2

). PWM2

controller drives a MOSFET (Q3) in a standard buck
converter configuration and regulates the I/O voltage to a
resistor programmable level between 3.0 and 3.5V

. An

integrated linear regulator supplies the 2.5V clock generator
power (V

OUT4

). The linear controller drives an external

MOSFET (Q4) to supply the GTL bus power (V

OUT3

Initialization

The HIP6019 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12V

) at the VCC pin and the 5V input voltage

(+5V

) at the OCSET1 pin. The normal level on OCSET1 is

equal to +5V

less a fixed voltage drop (see over-current

protection). The POR function initiates soft-start operation
after both input supply voltages exceed their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
11

A current source charges an external capacitor (C

) on

the SS pin to 4V. The PWM error amplifier reference inputs
(+ terminal) and outputs (COMP1 and COMP2 pins) are
clamped to a level proportional to the SS pin voltage. As the
SS pin voltage ramps from 1V to 4V, the output clamp allows
generation of PHASE pulses of increasing width that charge
the output capacitor(s). After this initial stage, the reference
input clamp slows the output voltage rate-of-rise and
provides a smooth transition to the final set voltage.
Additionally, both linear regulator's reference inputs are
clamped to a voltage proportional to the SS pin voltage. This
method provides a rapid and controlled output voltage rise.

Figure 6 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier output

voltage reach the valley of the oscillator's triangle wave. The
oscillator's triangular waveform is compared to the clamped
error amplifier output voltage. As the SS pin voltage
increases, the pulse-width on the PHASE pin increases. The
interval of increasing pulse-width continues until each output
reaches sufficient voltage to transfer control to the input
reference clamp. If we consider the 3.3V output (V

OUT2

) in

Figure 6, this time occurs at T2. During the interval between
T2 and T3, the error amplifier reference ramps to the final
value and the converter regulates the output to a voltage
proportional to the SS pin voltage. At T3 the input clamp
voltage exceeds the reference voltage and the output voltage
is in regulation.

The remaining outputs are also programmed to follow the SS
pin voltage. Each linear output (V

OUT3

and V

OUT4

) initially

follows the 3.3V output (V

OUT2

). When each output reaches

sufficient voltage the input reference clamp slows the rate of
output voltage rise. The PGOOD signal toggles `high' when
all output voltage levels have exceeded their under-voltage
levels. See the Soft-Start Interval section under Applications
Guidelines for a procedure to determine the soft-start interval.

Fault Protection

All four outputs are monitored and protected against extreme
overload. A sustained overload on any linear regulator
output or an over-voltage on the PWM outputs disables all
converters and drives the FAULT/RT pin to VCC.

Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on either VSEN1 or VSEN2

FIGURE 6. SOFT-START INTERVAL

TIME

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

(0.5V/DIV)

VOLTAGES

OUT1

(DAC = 2V)

OUT2

(= 3.3V)

OUT4

(= 2.5V)

OUT3

( = 1.5V)

(2V/DIV)

HIP6019

2-259

immediately sets the fault latch. A sequence of three over-
current fault signals also sets the fault latch. A comparator
indicates when C

is fully charged (UP signal), such that an

under-voltage event on either linear output (FB3 or FB4) is
ignored until after the soft-start interval (approximately T3 in
Figure 6). At start-up, this allows V

OUT3

and V

OUT4

to slew

up over increased time intervals, without generating a fault.
Cycling the bias input voltage (+12V

on the VCC pin) off

then on resets the counter and the fault latch.

Over-Voltage Protection

During operation, a short on the upper MOSFET (Q1)
causes V

OUT1

to increase. When the output exceeds the

over-voltage threshold of 115% of DACOUT, the over-voltage
comparator trips to set the fault latch and turns Q2 on as
required in order to regulate V

OUT1

to 1.15 x DACOUT. This

blows the input fuse and reduces V

OUT1

. The fault latch

raises the FAULT/RT pin close to VCC potential.

A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V

OUT1

monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on, as
needed to regulate V

OUT1

to 1.26V.

Over-Current Protection

All outputs are protected against excessive over-currents.
Both PWM controllers use the upper MOSFET's
on-resistance, r

DS(ON)

to monitor the current for protection

against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an over-
current condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear
controller monitor FB3 and FB4 for under-voltage to protect
against excessive currents.

Figures 8 and 9 illustrate the over-current protection with an
overload on OUT2. The overload is applied at T0 and the
current increases through the output inductor (L

OUT2

). At time

T1, the OVER-CURRENT2 comparator trips when the voltage
across Q3 (I

DS(ON)

) exceeds the level programmed by

OCSET

. This inhibits all outputs, discharges the soft-start

capacitor (C

) with a 11

A current sink, and increments the

counter. C

recharges at T2 and initiates a soft-start cycle

with the error amplifiers clamped by soft-start. With OUT2 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments to
3. This sets the fault latch to disable the converter. The fault is
reported on the FAULT/RT pin.

The PWM1 controller and the linear regulator operate in the
same way as PWM2 to over-current faults. Additionally, the
linear regulator and linear controller monitor the feedback
pins for an under-voltage. Should excessive currents cause
FB3 or FB4 to fall below the linear under-voltage threshold,
the LUV signal sets the over-current latch if C

is fully

charged. Blanking the LUV signal during the C

charge

interval allows the linear outputs to build above the under-
voltage threshold during normal start-up. Cycling the bias
input power off then on resets the counter and the fault

latch

FAULT

LATCH

POR

COUNTER

OC1

OC2

LUV

0.15V

VCC

FAULT

FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC

OVER

CURRENT

LATCH

INHIBIT

INDUCT

OR CURRENT

SOFT

-ST

FIGURE 8. OVER-CURRENT OPERATION

TIME

T/R

10V

FAULT

REPORTED

COUNT

= 1

COUNT

= 2

COUNT

= 3

OVERLOAD
APPLIED

HIP6019

2-260

Resistors (R

OCSET1

and R

OCSET2

) program the over-

current trip levels for each PWM converter. As shown in
Figure 9, the internal 200

A current sink develops a voltage

across R

OCSET

SET

) that is referenced to V

. The DRIVE

signal enables the over-current comparator (OVER-
CURRENT1 or OVER-CURRENT2). When the voltage
across the upper MOSFET (V

) exceeds V

SET

, the over-

current comparator trips to set the over-current latch. Both
V

SET

and V

are referenced to V

and a small capacitor

across R

OCSET

helps V

OCSET

track the variations of V

due

to MOSFET switching. The over-current function will trip at a
peak inductor current (I

PEAK)

determined by:

The OC trip point varies with MOSFET's temperature. To avoid
over-current tripping in the normal operating load range,
determine the R

OCSET

resistor from the equation above with:

1. The maximum r

DS(ON)

at the highest junction temperature.

2. The minimum I

OCSET

from the specification table.

3. Determine I

PEAK

for I

PEAK

> I

OUT(MAX)

+ (

I)/2,

where

I is the output inductor ripple current.

For an equation for the output inductor ripple current see
the section under component guidelines titled `Output
Inductor Selection'.

OUT1 Voltage Program

The output voltage of the PWM1 converter is programmed to
discrete levels between 1.8V

and 3.5V

. This output is

designed to supply the microprocessor core voltage. The
voltage identification (VID) pins program an internal voltage
reference (DACOUT) through a TTL-compatible 5-bit digital-to-
analog converter. The level of DACOUT also sets the PGOOD
and OVP thresholds. Table 1 specifies the DACOUT voltage for
the different combinations of connections on the VID pins. The
VID pins can be left open for a logic 1 input, because they are
internally pulled up to +5V by a 10

A current source. Changing

the VID inputs during operation is not recommended. The

sudden change in the resulting reference voltage could toggle
the PGOOD signal and exercise the over-voltage protection. All
VID pin combinations resulting in an INHIBIT disable the IC and
the open-collector at the PGOOD pin.

Application Guidelines

Soft-Start Interval

Initially, the soft-start function clamps the error amplifiers'
output of the PWM converters. After the output voltage
increases to approximately 80% of the set value, the
reference input of the error amplifier is clamped to a voltage
proportional to the SS pin voltage. The resulting output
voltage sequence is shown in Figure 6.

The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval is
programmed by the soft-start capacitor, C

. Programming

a faster soft-start interval increases the peak surge current.
The peak surge current occurs during the initial output
voltage rise to 80% of the set value.

Shutdown

Neither PWM output switches until the soft-start voltage
(V

) exceeds the oscillator's valley voltage. Additionally, the

reference on each linear's amplifier is clamped to the soft-
start voltage. Holding the SS pin low (with an open drain or
collector signal) turns off all four regulators.

The VID codes resulting in an INHIBIT as shown in Table 1
also shut down the IC.

UGATE

OCSET

PHASE

OVER-

CURRENT2

GATE

CONTROL

VCC

OC2

200

SET

OCSET

= +5V

OVER-CURRENT TRIP: V

> V

SET

ˇ r

DS(ON)

> I

OCSET

ˇ R

OCSET

)

OCSET

FIGURE 9. OVER-CURRENT DETECTION

PWM

PHASE

= V

- V

OCSET

= V

- V

SET

DRIVE

HIP6019

PEAK

OCSET

DS ON

(

)

----------------------------------------------------

TABLE 1. V

OUT1

VOLTAGE PROGRAM

PIN NAME

NOMINAL

OUT1

VOLTAGE

DACOUT

VID4

VID3

VID2

VID1

VID0

INHIBIT

1.80

1.85

1.90

1.95

2.00

2.05

INHIBIT

2.1

2.2

2.3

2.4

2.5

2.6

HIP6019

2-261

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper MOSFET. Prior to turnoff, the upper
MOSFET was carrying the full load current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET or Schottky diode. Any
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide circuit traces minimize the magnitude of
voltage spikes. Contact Intersil for evaluation board drawings
of the component placement and printed circuit board.

There are two sets of critical components in a DC-DC
converter using a HIP6019 controller. The power
components are the most critical because they switch large
amounts of energy. The critical small signal components
connect to sensitive nodes or supply critical bypassing
current.

The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors and
the power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.

The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C

. Locate

these components close to their connecting pins on the

control IC. Minimize any leakage current paths from SS node
because the internal current source is only 11

A multi-layer printed circuit board is recommended. Figure
10 shows the connections of the critical components in the
converter. Note that capacitors C

and C

OUT

could each

represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. The power plane
should support the input power and output power nodes.
Use copper filled polygons on the top and bottom circuit
layers for the phase nodes. Use the remaining printed circuit
layers for small signal wiring. The wiring traces from the
control IC to the MOSFET gate and source should be sized
to carry 1A currents. The traces for OUT4 need only be sized
for 0.2A. Locate C

OUT4

close to the HIP6019 IC.

PWM Controller Feedback Compensation

Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller. Apply the methods and
considerations to both PWM controllers.

Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The reference
voltage level is the DAC output voltage for PWM1 and is
1.265V for PWM2. The error amplifier output (V

E/A

) is

compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated wave with an amplitude of
V

at the PHASE node. The PWM wave is smoothed by the

output filter (L

and C

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

NOTE: 0 = connected to GND or V

, 1 = open or connected to 5V

through pull-up resistors, X = don't care.

TABLE 1. V

OUT1

VOLTAGE PROGRAM (Continued)

PIN NAME

NOMINAL

OUT1

VOLTAGE

DACOUT

VID4

VID3

VID2

VID1

VID0

FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

OUT1

+12V

VCC

VIA CONNECTION TO GROUND PLANE

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

OUT1

CR1

HIP6019

OUT2

OUT3

+5V

PGND

LGATE1

UGATE1

PHASE1

GATE3

PHASE2

KEY

OUT2

GND

VCC

UGATE2

OCSET1

OCSET2

OCSET1

OCSET2

OCSET1

OCSET2

HIP6019

2-262

The modulator transfer function is the small-signal transfer
function of V

OUT

E/A

. This function is dominated by a DC

gain and the output filter, with a double pole break frequency
at F

and a zero at F

ESR

. The DC gain of the modulator is

simply the input voltage, V

, divided by the peak-to-peak

oscillator voltage,

OSC

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
internal to the HIP6019 and the impedance networks Z

and Z

. The goal of the compensation network is to

provide a closed loop transfer function with an acceptable
0dB crossing frequency (f

0dB

) and adequate phase margin.

Phase margin is the difference between the closed loop
phase at f

0dB

and 180 degrees

The equations below relate

the compensation network's poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth.

2. Place 1

Zero below filter's Double Pole (~75% F

3. Place 2

Zero at filter's Double Pole.

4. Place 1

Pole at the ESR Zero.

5. Place 2

Pole at half the switching frequency.

6. Check Gain against Error Amplifier's Open-Loop Gain.

7. Estimate Phase Margin - repeat if necessary.

Compensation Break Frequency Equations

Figure 12 shows an asymptotic plot of the DC-DC
converter's gain vs frequency. The actual modulator gain has
a peak due to the high Q factor of the output filter at F

which is not shown in Figure 12. Using the above guidelines
should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F

with the capabilities of the error amplifier. The closed loop
gain is constructed on the log-log graph of Figure 12 by
adding the modulator gain (in dB) to the compensation gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.

The compensation gain uses external impedance networks
Z

and Z

to provide a stable, high bandwidth loop. A

stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.

Oscillator Synchronization

The PWM controllers use a triangle wave for comparison with
the error amplifier output to provide a pulse-width modulated
wave. Should the output voltages of the two PWM converters
be programmed close to each other, then cross-talk could
cause nonuniform PHASE pulse-widths and increased output
voltage ripple. The HIP6019 avoids this problem by
synchronizing the two converters 180

out-of-phase for DAC

FIGURE 11. VOLTAGE-MODE BUCK CONVERTER COMPEN-

SATION DESIGN

OUT

OSC

REFERENCE

ESR

OSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

REFERENCE

COMP

OUT

HIP6019

COMP

DRIVER

DETAILED FEEDBACK COMPENSATION

PHASE

E/A

----------------------------------------

ESR

-----------------------------------------

-----------------------------------

(

)

-------------------------------------------------------

----------------------

-------------------------------------------------------

-----------------------------------

100

-20

-40

-60

10M

100K

10K

100

OPEN LOOP
ERROR AMP GAIN

20LOG

ESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

OSC

)

MODULATOR

GAIN

)

FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP
GAIN

HIP6019

2-263

settings above, and including 2.5V. This is accomplished by
inverting the triangle wave sent to PWM 2.

Component Selection Guidelines

Output Capacitor Selection

The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The linear regulator is internally
compensated and requires an output capacitor that meets
the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.

PWM Output Capacitors

Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and ESL (effective series
inductance) parameters rather than actual capacitance.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor's ESR determines the output ripple voltage and
the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor's ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately,
ESL is not a specified parameter. Work with your capacitor
supplier and measure the capacitor's impedance with
frequency to select suitable components. In most cases,
multiple electrolytic capacitors of small case size perform
better than a single large case capacitor. For a given transient
load magnitude, the output voltage transient response due to
the output capacitor characteristics can be approximated by
the following equation:

Linear Output Capacitors

The output capacitors for the linear regulator and the linear
controller provide dynamic load current. The linear controller
uses dominant pole compensation integrated in the error
amplifier and is insensitive to output capacitor selection.

Capacitor, C

OUT3

should be selected for transient load

regulation.

The output capacitor for the linear regulator provides loop
stability. The linear regulator (OUT4) requires an output
capacitor characteristic shown in Figure 13 The upper line
plots the 45 phase margin with 150mA load and the lower
line is the 45 phase margin limit with a 10mA load. Select a
C

OUT4

capacitor with characteristic between the two limits.

Output Inductor Selection

Each PWM converter requires an output inductor. The
output inductor is selected to meet the output voltage ripple
requirements and sets the converter's response time to a
load transient. The inductor value determines the converter's
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter's response time to a load transient.

One of the parameters limiting the converter's response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6019 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time interval
required to slew the inductor current from an initial current value
to the post-transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitors.
Minimizing the response time can minimize the output
capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following

TRAN

ESL

TRAN

---------------------

ESR

TRAN

1000

100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

CAPACITANCE (

ESR (

)

FIGURE 13. C

OUT4

OUTPUT CAPACITOR

ABLE

OPERA

TION

OUT

--------------------------------

OUT

----------------

OUT

ESR

HIP6019

2-264

equations give the approximate response time interval for
application and removal of a transient load:

where: I

TRAN

is the transient load current step, t

RISE

is the

response time to the application of load, and t

FALL

is the

response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application or
removal of load and dependent upon the output voltage setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline.

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors should be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.

For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.

MOSFET Selection/Considerations

The HIP6019 requires 4 N-Channel power MOSFETs. Two
MOSFETs are used in the synchronous-rectified buck
topology of PWM1 converter. PWM2 converter uses a
MOSFET as the buck switch and the linear controller drives
a MOSFET as a pass transistor. These should be selected
based upon r

DS(ON)

, gate supply requirements, and thermal

management requirements.

PWM1 MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the only component of

power dissipation for the lower MOSFETs. Only the upper
MOSFET has switching losses, since the lower device turns
on into near zero voltage.

The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET's body diode. The gate-
charge losses are proportional to the switching frequency
(F

) and are dissipated by the HIP6019, thus not

contributing to the MOSFETs' temperature rise. However,
large gate charge increases the switching interval, t

which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

The r

DS(ON)

is different for the two previous equations even

if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 14 shows the gate drive where the
upper gate-to-source voltage is approximately V

less the

input supply. For +5V main power and +12V

for the bias,

the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12V

. A logic-level MOSFET is a good choice

for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the
maximum voltage applied to V

Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the
lower MOSFET and the turn on of the upper MOSFET. The
diode must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to

RISE

TRAN

OUT

--------------------------------

FALL

TRAN

OUT

-------------------------------

UPPER

DS ON

(

)

OUT

------------------------------------------------------------

----------------------------------------------------

LOWER

DS ON

(

)

OUT

(

)

---------------------------------------------------------------------------------

+12V

PGND

HIP6019

GND

LGATE

UGATE

PHASE

+5V OR LESS

NOTE:

NOTE:
V

FIGURE 14. OUTPUT GATE DRIVERS

-5V

CR1

HIP6019

2-265

omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency might drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than twice the maximum
input voltage.

PWM2 MOSFET and Schottky Selection

The power dissipation in PWM2 converter power devices is
similar to PWM1 except that the power losses of the lower
device are representative of a Schottky diode instead of a
MOSFET. The transistor power losses follow the PWM1
upper MOSFET equation, so the selection process should
be somewhat similar. The equation below describes the
conduction power losses incurred by the Schottky diode.

As it can be observed, conduction losses in the Schottky
diode are proportional with the forward voltage drop (V

Linear Controller MOSFET Selection

The main criteria for selection of MOSFET for the linear
regulator is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:

Select a package and heatsink that maintains the junction
temperature below the maximum rating while operating at
the highest expected ambient temperature.

SCH

OUT

(

)

-------------------------------------------------------------

LINEAR

OUT

(

)

HIP6019

2-266

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

HIP6019 DC-DC Converter Application Circuit

Figure 15 shows an application circuit of a power supply for
a microprocessor computer system. The power supply
provides the microprocessor core voltage (V

OUT1

), the I/O

voltage (V

OUT2

), the GTL bus voltage (V

OUT3

) and clock

generator voltage (V

OUT4

) from +5V

and +12V

. For

detailed information on the circuit, including a Bill-of-
Materials and circuit board description, see Application Note
AN9800. Also see Intersil's web page
(http://www.intersil.com) or Intersil AnswerFAX
(407-724-7800) document # 99800 for the latest information.

VID1

VID2

VID3

VID4

GND

VCC

+5V

VID0

+12V

PGND

VSEN1

PGOOD

LGATE1

UGATE1

OCSET1

PHASE1

POWERGOOD

FB1

COMP1

OUT2

VSEN2

UGATE2

OCSET2

PHASE2

CR2

FB2

COMP2

GATE3

FB3

VOUT4

FB4

C47

OUT3

OUT4

C43-46

C24-36

HIP6019

C16

C1-4

C14-15

C18

OUT1

C40

C41

C42

R10

C48

R11

R12

R13

R14

270

4x1000

MBR2535CTL

C19-23
5x1000

HUF76137S3S

C37

C38

C39

4x1000

2x1

C17

1000pF

HUF76139S3S

7x1000

0.039

1.21K

0.1

10pF

0.68

4.99K

3.32K

220K

5.2

2.9

0.68

10pF

0.01

4.99K

2.21K

150K

732K

GND

1.87K

10K

HUF75307D3S

5.11K

R21

VID1

VID2

VID3

VID4

VID0

(1.8 TO 3.5V)

(3.3V)

(GTL = 1.5V)

(2.5V)

30A

FAULT/RT

FIGURE 15. APPLICATION CIRCUIT

HIP6019

Part Number HIP6019