HIP6004B

Buck and Synchronous-Rectifier (PWM)

Controller and Output Voltage Monitor

The HIP6004B provides complete control and protection for
a DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004B integrates all of the control, output
adjustment, monitoring and protection functions into a
single package.

The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004B includes a fully TTL-
compatible 5-input digital-to-analog converter (DAC) that
adjusts the output voltage from 1.3V

to 2.05V

0.05V and from 2.1V

to 3.5V

in 0.1V increments

steps. The precision reference and voltage-mode regulator
hold the selected output voltage to within

1% over

temperature and line voltage variations.

The HIP6004B provides simple, single feedback loop,
voltage-mode control with fast transient response. It
includes a 200kHz free-running triangle-wave oscillator that
is adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/

s slew rate which enables high converter bandwidth for

fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.

The HIP6004B monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within

10%. The

HIP6004B protects against over-current and overvoltage
conditions by inhibiting PWM operation. Additional built-in
overvoltage protection triggers an external SCR to crowbar
the input supply. The HIP6004B monitors the current by
using the r

DS(ON)

of the upper MOSFET which eliminates

the need for a current sensing resistor.

Features

· Drives Two N-Channel MOSFETs
· Operates from +5V or +12V Input
· Simple Single-Loop Control Design

- Voltage-Mode PWM Control

· Fast Transient Response

- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio

· Excellent Output Voltage Regulation

1% Over Line Voltage and Temperature

· TTL-Compatible 5-Bit Digital-to-Analog Output

Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.3V

to 3.5V

- 0.1V Binary Steps . . . . . . . . . . . . . . 2.1V

to 3.5V

- 0.05V Binary Steps . . . . . . . . . . . . 1.3V

to 2.05V

· Power-Good Output Voltage Monitor
· Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET's r

DS(ON)

· Small Converter Size

- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from

50kHz to over 1MHz

Applications

· Power Supply for Pentium®, Pentium Pro, Pentium II,

PowerPCTM, K6TM, 6X86TM and AlphaTM Microprocessors

· High-Power 5V to 3.xV DC-DC Regulators
· Low-Voltage Distributed Power Supplies

Pinout

HIP6004B

(SOIC, TSSOP)

TOP VIEW

6X86TM is a trademark of Cyrix Corporation.

AlphaTM is a trademark of Digital Equipment Corporation.

K6TM is a trademark of Advanced Micro Devices, Inc.

Pentium® is a registered trademark of Intel Corporation.

PowerPCTM is a trademark of IBM.

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

NO.

HIP6004BCB

0 to 70

20 Ld SOIC

M20.3

HIP6004BCV

0 to 70

20 Ld TSSOP

M20.173

NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the TSSOP variant in tape and reel, e.g., HIP6004BCV-T.

VSEN

OCSET

VID0

VID1

VID2

VID4

VID3

COMP

VCC

LGATE

PGND

OVP

BOOT

UGATE

PHASE

PGOOD

GND

Data Sheet

February 1999

FN4567.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

HIP6004B

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V

Boot Voltage, V

BOOT

- V

PHASE

. . . . . . . . . . . . . . . . . . . . . . . .+15V

Input, Output or I/O Voltage. . . . . . . . . . . . GND -0.3V to V

+0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Operating Conditions

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V

10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0

C to 70

Thermal Resistance (Typical, Note 1)

(

C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

110

SOIC Package (with 3in

of Copper) . . . . . . . . . . . .

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

140

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY CURRENT

Nominal Supply

UGATE and LGATE Open

POWER-ON RESET

Rising V

Threshold

OCSET

= 4.5V

10.4

Falling V

Threshold

OCSET

= 4.5V

8.2

Rising V

OCSET

Threshold

1.26

OSCILLATOR

Free Running Frequency

RT = OPEN

185

200

215

kHz

Total Variation

< RT to GND < 200k

-15

+15

Ramp Amplitude

OSC

RT = Open

1.9

P-P

REFERENCE AND DAC

DAC (VID0-VID4) Input Low Voltage

0.8

DAC (VID0-VID4) Input High Voltage

2.0

DACOUT Voltage Accuracy

-1.0

+1.0

ERROR AMPLIFIER

DC Gain

Gain-Bandwidth Product

GBW

MHz

Slew Rate

COMP = 10pF

GATE DRIVERS

Upper Gate Source

UGATE

BOOT

- V

PHASE

= 12V, V

UGATE

= 6V

350

500

Upper Gate Sink

UGATE

LGATE

= 0.3A

5.5

Lower Gate Source

LGATE

= 12V, V

LGATE

= 6V

300

450

Lower Gate Sink

LGATE

= 0.3A

3.5

6.5

PROTECTION

Over-Voltage Trip (V

SEN

/DACOUT)

115

120

OCSET Current Source

OCSET

= 4.5V

170

200

230

OVP Sourcing Current

OVP

SEN

= 5.5V, V

OVP

= 0V

Soft Start Current

HIP6004B

POWER GOOD

Upper Threshold (V

SEN

/DACOUT)

SEN

Rising

106

111

Lower Threshold (V

SEN

/DACOUT)

SEN

Falling

Hysteresis (V

SEN

/DACOUT)

Upper and Lower Threshold

PGOOD Voltage Low

PGOOD

= -5mA

0.5

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Typical Performance Curves

FIGURE 1. R

RESISTANCE vs FREQUENCY

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

100

1000

SWITCHING FREQUENCY (kHz)

I
S

ANCE

(

)

100

1000

PULLUP

TO +12V

PULLDOWN TO V

100

200

300

400

500

600

700

800

900

1000

(mA

)

SWITCHING FREQUENCY (kHz)

GATE

= 3300pF

GATE

= 1000pF

GATE

= 10pF

UPPER

= C

LOWER

= C

GATE

HIP6004B

Functional Pin Descriptions

VSEN (Pin 1)

This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.

OCSET (Pin 2)

Connect a resistor (R

OCSET

) from this pin to the drain of

the upper MOSFET. R

OCSET

, an internal 200

A current

source (I

OCS

), and the upper MOSFET on-resistance

DS(ON)

) set the converter over-current (OC) trip point

according to the following equation:

An over-current trip cycles the soft-start function.

SS (Pin 3)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10

A current source, sets the soft-

start interval of the converter.

VID0-4 (Pins 4-8)

VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter
output voltage. It also sets the PGOOD and OVP
thresholds. Table 1 specifies DACOUT for the all
combinations of DAC inputs.

COMP (Pin 9) and FB (Pin 10)

COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.

GND (Pin 11)

Signal ground for the IC. All voltage levels are measured
with respect to this pin.

PGOOD (Pin 12)

PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within

10%

of the

DACOUT reference voltage. Exception to this behavior is
the `11111' VID pin combination which disables the
converter; in this case PGOOD asserts a high level.

PHASE (Pin 13)

Connect the PHASE pin to the upper MOSFET source.
This pin is used to monitor the voltage drop across the
MOSFET for over-current protection. This pin also provides
the return path for the upper gate drive.

UGATE (Pin 14)

Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.

BOOT (Pin 15)

This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.

PGND (Pin 16)

This is the power ground connection. Tie the lower
MOSFET source to this pin.

LGATE (Pin 17)

Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.

VCC (Pin 18)

Provide a 12V bias supply for the chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.

RT (Pin 20)

This pin provides oscillator switching frequency
adjustment. By placing a resistor (R

) from this pin to GND,

the nominal 200kHz switching frequency is increased
according to the following equation:

Conversely, connecting a pull-up resistor (R

) from this pin

to V

reduces the switching frequency according to the

following equation:

VSEN

OCSET

VID0

VID1

VID2

VID4

VID3

COMP

VCC

LGATE

PGND

OVP

BOOT

UGATE

PHASE

PGOOD

GND

PEAK

OCSET

x R

OCSET

DS ON

(

)

-----------------------------------------------------

Fs 200kHz

5 x 10

(

)

---------------------

to GND)

Fs 200kHz

4 x 10

(

)

---------------------

to 12V)

HIP6004B

Functional Description

Initialization

The HIP6004B automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the V

pin and the input voltage (V

) on the OCSET pin. The level on

OCSET is equal to V

less a fixed voltage drop (see over-

current protection). The POR function initiates soft start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, V

and V

are equivalent and the +12V power source must

exceed the rising V

threshold before POR initiates operation.

Soft Start

The POR function initiates the soft start sequence. An internal
10

A current source charges an external capacitor (C

) on

the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft start interval with
C

= 0.1

F. Initially the clamp on the error amplifier (COMP

pin) controls the converter's output voltage. At t

in Figure 3,

the SS voltage reaches the valley of the oscillator's triangle
wave. The oscillator's triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE pulses
of increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t

. With sufficient

output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t

and t

in Figure 3.

At t

the SS voltage exceeds the DACOUT voltage and the

output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
`high' when the output voltage (V

SEN

pin) is within

5% of

DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.

Over-Current Protection

The over-current function protects the converter from a
shorted output by using the upper MOSFET's on-resistance,
r

DS(ON)

to monitor the current. This method enhances the

converter's efficiency and reduces cost by eliminating a
current sensing resistor.

The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R

OCSET

)

programs the over-current trip level. An internal 200

A current

sink develops a voltage across R

OCSET

that is referenced to

. When the voltage across the upper MOSFET (also

referenced to V

) exceeds the voltage across R

OCSET

, the

over-current function initiates a soft-start sequence. The soft-
start function discharges C

with a 10

A current sink and

inhibits PWM operation. The soft-start function recharges
C

, and PWM operation resumes with the error amplifier

clamped to the SS voltage. Should an overload occur while
recharging C

, the soft start function inhibits PWM operation

while fully charging C

to 4V to complete its cycle. Figure 4

shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the C

charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.

The over-current function will trip at a peak inductor current
(I

PEAK)

determined by:

where I

OCSET

is the internal OCSET current source

(200

A typical). The OC trip point varies mainly due to the

MOSFET's r

DS(ON)

variations. To avoid over-current

tripping in the normal operating load range, find the
R

OCSET

resistor from the equation above with:

1. The maximum r

DS(ON)

at the highest junction temperature.

2. The minimum I

OCSET

from the specification table.

3. Determine I

PEAK

for

where

I is the output inductor ripple current.

TIME (5ms/DIV.)

SOFT-START

(1V/DIV.)

OUTPUT

(1V/DIV.)

VOLTAGE

PGOOD

(2V/DIV.)

FIGURE 3. SOFT START INTERVAL

INDUCT

-
S

ART

TIME (20ms/DIV.)

10A

15A

FIGURE 4. OVER-CURRENT OPERATION

PEAK

OCSET

x R

OCSET

DS ON

(

)

-----------------------------------------------------

PEAK

OUT MAX

(

)

( )

HIP6004B

For an equation for the ripple current see the section under
component guidelines titled `Output Inductor Selection'.

A small ceramic capacitor should be placed in parallel with
R

OCSET

to smooth the voltage across R

OCSET

in the

presence of switching noise on the input voltage.

Output Voltage Program

The output voltage of a HIP6004B converter is programmed
to discrete levels between 1.8V

and 3.5V

. The voltage

identification (VID) pins program an internal voltage reference
(DACOUT) with a TTL-compatible 5-bit digital-to-analog
converter (DAC). The level of DACOUT also sets the PGOOD
and OVP thresholds. Table 1 specifies the DACOUT voltage
for the 32 different combinations of connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and exercise
the overvoltage protection.

`11111' VID pin combination resulting in a 0V output setting
activates the Power-On Reset function and disables the gate
drives circuitry. For this specific VID combination, though,
PGOOD asserts a high level. This unusual behavior has been
implemented in order to allow for operation in dual-
microprocessor systems where AND-ing of the PGOOD signals
from two individual power converters is implemented.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

VID4

VID3

VID2

VID1

VID0

VID4

VID3

VID2

VID1

VID0

1.30

1.35

2.1

1.40

2.2

1.45

2.3

1.50

2.4

1.55

2.5

1.60

2.6

1.65

2.7

1.70

2.8

1.75

2.9

1.80

3.0

1.85

3.1

1.90

3.2

1.95

3.3

2.00

3.4

2.05

3.5

NOTE: 0 = connected to GND or V

, 1 = connected to V

through pull-up resistors.

HIP6004B

Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors C

and C

each represent

numerous physical capacitors. Locate the HIP6004B within 3
inches of the MOSFETs, Q

and Q

. The circuit traces for the

MOSFETs' gate and source connections from the HIP6004B
must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C

close to the SS pin because the internal current source is
only 10

A. Provide local V

decoupling between V

and

GND pins. Locate the capacitor, C

BOOT

as close as

practical to the BOOT and PHASE pins.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

OUT

) is regulated to the Reference voltage level. The

error amplifier (Error Amp) output (V

E/A

) is compared with

the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V

the PHASE node.

The PWM wave is smoothed by the output filter (L

and C

The modulator transfer function is the small-signal transfer
function of V

OUT

E/A

. This function is dominated by a DC

Gain and the output filter (L

and C

), with a double pole

break frequency at F

and a zero at F

ESR

. The DC Gain

of the modulator is simply the input voltage (V

) divided by

the peak-to-peak oscillator voltage

OSC

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
(internal to the HIP6004B) and the impedance networks
Z

and Z

. The goal of the compensation network is to

provide a closed loop transfer function with the highest 0dB
crossing frequency (f

0dB

) and adequate phase margin.

Phase margin is the difference between the closed loop
phase at f

0dB

and 180

degrees

The equations below relate

the compensation network's poles, zeros and gain to the
components (R

, R

, C

, and C

) in Figure 7. Use

these guidelines for locating the poles and zeros of the
compensation network:

1. Pick Gain (R

) for desired converter bandwidth.

2. Place 1

Zero Below Filter's Double Pole (~75% F

3. Place 2

Zero at Filter's Double Pole.

4. Place 1

Pole at the ESR Zero.

5. Place 2

Pole at Half the Switching Frequency.

6. Check Gain against Error Amplifier's Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.

PGND

LGATE

UGATE

PHASE

OUT

RETURN

HIP6004B

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND

PLANES OR ISLANDS

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6004B

GND

BOOT

OUT

PHASE

BOOT

VCC

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

OUT

REFERENCE

ESR

OSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

DACOUT

COMP

OUT

HIP6004B

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

E/A

OSC

FLC

x LO x CO

-------------------------------------------

FESR

x ESR x CO

--------------------------------------------

HIP6004B

Compensation Break Frequency Equations

Figure 8 shows an asymptotic plot of the DC-DC converter's
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F

with the capabilities of

the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks
Z

and Z

to provide a stable, high bandwidth (BW)

overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when
determining phase margin.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and
supply the load transient current. The filtering requirements
are a function of the switching frequency and the ripple
current. The load transient requirements are a function of
the slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a mix
of capacitors and careful layout.

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible.
Be careful not to add inductance in the circuit board wiring
that could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1

ceramic capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor's ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor's ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor's
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter's response
time to the load transient. The inductor value determines
the converter's ripple current and the ripple voltage is a
function of the ripple current. The ripple voltage and current
are approximated by the following equations:

Increasing the value of inductance reduces the ripple
current and voltage. However, the large inductance values
reduce the converter's response time to a load transient.

x R

x C

------------------------------------

x R

(

)

x C

-------------------------------------------------------

x R

x C

----------------------

---------------------------------------------------------

x R

x C

------------------------------------

100

-20

-40

-60

10M

100K

10K

100

OPEN LOOP
ERROR AMP GAIN

20LOG

ESR

COMPENSATION

IN (

FREQUENCY (Hz)

GAIN

20LOG

OSC

)

MODULATOR

GAIN

)

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP

GAIN

I =

- V

OUT

Fs x L

OUT

I x ESR

HIP6004B

One of the parameters limiting the converter's response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6004B will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

where: I

TRAN

is the transient load current step, t

RISE

is the

response time to the application of load, and t

FALL

is the

response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
level equal to DACOUT, t

FALL

is the longest response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q

turns on. Place the

small ceramic capacitors physically close to the MOSFETs
and between the drain of Q

and the source of Q

The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is
a conservative guideline. The RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.

For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The HIP6004B requires 2 N-Channel power MOSFETs. These
should be selected based upon r

DS(ON)

, gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor (see the equations
below). Only the upper MOSFET has switching losses, since
the Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. These equations assume linear
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET's body
diode. The gate-charge losses are dissipated by the HIP6004B
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t

which increases the upper

MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

Standard-gate MOSFETs are normally recommended for
use with the HIP6004B. However, logic-level gate
MOSFETs can be used under special circumstances. The
input voltage, upper gate drive level, and the MOSFET's
absolute gate-to-source voltage rating determine whether
logic-level MOSFETs are appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V

. The boot capacitor, C

BOOT

develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V

less the boot diode drop (V

) when the lower MOSFET, Q

turns on. Logic-level MOSFETs can only be used if the
MOSFET's absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V

RISE

L x I

TRAN

- V

OUT

FALL

L x I

TRAN

OUT

UPPER

= Io

x r

DS(ON)

x D +

1
2

Io x V

x t

x F

LOWER

= Io

x r

DS(ON)

x (1 - D)

Where: D is the duty cycle = V

OUT

/ V

is the switch ON time, and

is the switching frequency.

HIP6004B

Figure 10 shows the upper gate drive supplied by a direct
connection to V

. This option should only be used in

converter systems where the main input voltage is +5V

less. The peak upper gate-to-source voltage is approximately
V

less the input supply. For +5V main power and +12V

for the bias, the gate-to-source voltage of Q

is 7V. A logic-

level MOSFET is a good choice for Q

and a logic-level

MOSFET can be used for Q

if its absolute gate-to-source

voltage rating exceeds the maximum voltage applied to V

Schottky Selection

Rectifier D

is a clamp that catches the negative inductor

swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum
input voltage.

+12V

PGND

HIP6004B

GND

LGATE

UGATE

PHASE

BOOT

VCC

+5V OR +12V

NOTE:

NOTE:
V

G-S

BOOT

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

G-S

-V

+ V

+12V

PGND

HIP6004B

GND

LGATE

UGATE
PHASE

BOOT

VCC

+5V OR LESS

NOTE:

NOTE:
V

G-S

FIGURE 10. UPPER GATE DRIVE - DIRECT V

DRIVE OPTION

G-S

-5V

HIP6004B

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HIP6004B DC-DC Converter Application Circuit

Figure 11 shows an application circuit of a DC-DC
Converter for an Intel Pentium Pro microprocessor.
Detailed information on the circuit, including a complete
Bill-of-Materials and circuit board description, can be found

in Application Note AN9672. Although the Application Note
details the HIP6004, the same evaluation platform can be
used to evaluate the HIP6004B.

+12V

PGND

HIP6004B

VSEN

COMP

VID0
VID1
VID2
VID3

OVP

PGOOD

D/A

GND

MONITOR

OSC

VCC

OUT

0.1

2x 1

0.1

2.2nF

8.2nF

20K

1.33K

5x 1000

9x 1000

0.1

LGATE

UGATE

OCSET

PHASE

BOOT

2N6394

1000pF

F 1

+5V

+12V

4
5

6
7

AND

PROTECTION

Component Selection Notes:

OUT

- Each 1000

F 6.3W VDC, Sanyo MV-GX or Equivalent.

- Each 330

F 25W VDC, Sanyo MV-GX or Equivalent.

- Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG.

- Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.

- 1N4148 or Equivalent.

- 3A, 40V Schottky, Motorola MBR340 or Equivalent.

FIGURE 11. PENTIUM PRO DC-DC CONVERTER

VID4

L1 - 1

HIP6004B

Part Number HIP6004B