File Number

4823.1

HI2325

3.3V Dual 8-Bit, 40MSPS A/D Converter
with Internal Reference and Digital Clamp

The HI2325 is a monolithic, dual 8-bit, 40MSPS analog-to-
digital converter fabricated in an advanced CMOS process.
It is designed for high speed applications where integration,
bandwidth and accuracy are essential. The HI2325 features
a 2-stage parallel architecture. Only one external clock is
necessary to drive both converters and an internal voltage
reference is provided allowing the system designer to realize
an increased level of system integration resulting in
decreased cost and power dissipation.

The HI2325 has excellent dynamic performance while
consuming less than 100mW power at 40MSPS. The A/D
only requires a single +3.3V power supply and encode clock.
Data output latches are provided which present valid data to
the output bus with a latency of 2 clock cycles.

Pinout

48 LEAD LQFP

TOP VIEW

Features

· Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS

· 6.5 Bits at f

= 1MHz

· Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW

· Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8mW

· Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz

· Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB

· Internal Digital Clamp

· Internal Voltage Reference

· Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.3V

· TTL/CMOS Compatible Digital Inputs

· CMOS Compatible Digital Outputs . . . . . . . . . . . . . . . 3.3V

· Offset Binary or 2's Complement Output Format

· Dual 8-Bit A/D Converters on a Monolithic Chip

Applications

· Wireless Local Loop

· PSK and QAM I&Q Demodulators

· Medical Imaging and Instrumentation

· Portable Communications

· Power Metering

· Hand-Held Data Collection Instruments

Ordering Information

PART

NUMBER

TEMP.

RANGE (

PACKAGE

PKG. NO.

HI2325IN

-20 to 85

48 Ld MQFP/PQFP

Q48.7x7-S

13 14 15 16

AVSS

AIO

AIN

AVDD
ART
ARTS

BRTS

BRT
AVDD

BIN

BIO

AVSS

B1
B2

DVDD

VSS

CLK

CLE

SEL

STB

VDD

ARBS

ARB

CLP

VSS

2S/B

REF0

REF1

REF2

TEST

VSS

BRBS

BRB

Data Sheet

March 2000

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Corporation.

Intersil Corporation 2000

Functional Block Diagram

36 35 34 33 32 31 30 29 28 27 26 25

BIO

BIN

BRITS

AIN

AIO

A-CH

8-BIT ADC

B-CH

8-BIT ADC

CLE

SEL

STB

AVDD

RBS

DVSS

CLK

CLP

VDD

11 12

AND

CLAMP DAC

CLAMP AND LATCH

AND TEST

19 REF1

REF2

TEST

AVSS

BRBS

BRB

13 B5

DVSS

2S/B

REF0

HI2325

Pin Descriptions

PIN NO.

SYMBOL

I/O

EQUIVALENT CIRCUIT

DESCRIPTION

46, 47, 48, 1- 5

A0 - A7

Digital Output. A0(LSB) - A7(MSB)

8 - 15

B0 - B7

Digital Output. B0(LSB) - B7(MSB)

6, 7

DVDD

Digital power supply.

DVSS

Digital ground.

2S/B

Pull-down resistors are
incorporated.

Selects output code.
H: 2's Compliment Code L: Binary Code

18, 19, 20

REF0 ~ 2

Pull-down resistors are
incorporated.

Determines the clamp circuit reference data. See the table "Digital
Clamp Reference Level".

TEST

Pull-down resistors are
incorporated.

Normally open.

22, 25

DVSS

Digital ground.

22, 25, 36

AVSS

Analog ground.

23
38

BRBS
ARBS

Shorting these pins to AVSS generates voltage of about 0.5V at the
BRB and ARB pins.

24
37

BRB
ARB

Reference voltage (bottom).

29
32

BRT
ART

Reference voltage (top).

30
31

BRTS
ARTS

Shorting these pins to AVDD generates voltage of about 2.5V at the
BRT and ART pins.

26
35

BIO
AIO

Analog output. The digital clamp circuit comprises a D/A converter
whose outputs are available on these pins.

27
34

BIN
AIN

Analog input.

28, 33, 39

AVDD

Analog power supply.

STB

Pull-down resistors are
incorporated.

Stand-by input.
H: Stand-by mode L: Operation mode.

SEL

Pull-down resistors are
incorporated.

Controls the CLP signal polarity.
H: CLP is High active L: CLP is Low active.

CLE

Pull-down resistors are
incorporated.

Clamp enable input.
H: Enable L: Disable.

CLP

Pull-down resistors are
incorporated.

Clamp pulse input. The polarity can be set to either High or Low by
setting SEL.

CLK

Pull-down resistors are
incorporated.

Clock input.

HI2325

Absolute Maximum Ratings

= 25

Thermal Information

Supply Voltage, AV

or DV

to AGND or DGND . . . . . . . . . . .4V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

Operating Conditions

Temperature Range

HI2325IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to 85

Thermal Resistance (Typical, Note 1)

(

C/W)

48 Ld MQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VDD

= D

VDD

= +3.3V; V

= 1.50V; f

= 40MSPS at 50% Duty Cycle;

= 10pF; T

= 25

C; Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ACCURACY

Resolution

Bits

Integral Linearity Error, INL

= 1MHz

0.2

LSB

Differential Linearity Error, DNL
(Guaranteed No Missing Codes)

= 1MHz

0.7

LSB

Offset Error, V

= DC

-50

Full Scale Error, FSE

= DC

LSB

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate

No Missing Codes

MSPS

Maximum Conversion Rate

No Missing Codes

MSPS

Effective Number of Bits, ENOB

= 1MHz

6.5

Bits

Signal to Noise and Distortion Ratio, SINAD

= 1MHz

Signal to Noise Ratio, SNR

= 1MHz

42.5

Total Harmonic Distortion, THD

= 1MHz

-46

dBc

2nd Harmonic Distortion

= 1MHz

-48

dBc

3rd Harmonic Distortion

= 1MHz

-52

dBc

Spurious Free Dynamic Range, SFDR

= 1MHz

48.5

dBc

Intermodulation Distortion, IMD

= 1MHz, f

= 1.02MHz

dBc

I/Q Channel Crosstalk

-75

dBc

I/Q Channel Offset Match

1.0

LSB

I/Q Channel Full Scale Error Match

0.25

LSB

Transient Response

(Note 2)

Cycle

Over-Voltage Recovery

0.2V Overdrive (Note 2)

Cycle

ANALOG INPUT

Maximum Peak-to-Peak Single-Ended
Analog Input Range

1.0

Analog Input Resistance, R

INA

or R

INB

INA

, V

INB

= V

REF

, DC

Analog Input Capacitance, C

INA

or C

INB

INA

, V

INB

= 1.5V, DC

RMS Signal

RMS Noise + Distortion

--------------------------------------------------------------

RMS Signal

RMS Noise

-------------------------------

HI2325

Analog Input Bias Current, I

A or I

INA

INB

= ART/BRT, ARB/BRB, DC

(Notes 2, 3)

Full Power Input Bandwidth, FPBW

= 40MHz, (Note 2)

MHz

REFERENCE VOLTAGE INPUT

Reference Voltage Input Range

Total Reference Resistance, R

RIN

370

Reference Current, I

RIN

5.4

Self Bias

0.54

1.9

SAMPLING CLOCK INPUT

Input Logic High Voltage, V

CLK

2.0

Input Logic Low Voltage, V

CLK

0.8

Input Logic High Current, I

CLK, V

= 3.3V

Input Logic Low Current, I

CLK, V

= 0V

Input Capacitance, C

CLK

DIGITAL OUTPUTS

Output Logic High Voltage, V

= 100

A; D

VDD

= 3.3V

Output Logic Low Voltage, V

= 1.5mA; D

VDD

= 3.3V

Output Logic High Voltage, V

= 100

A; D

VDD

= 3.0V

Output Logic Low Voltage, V

= 100

A; D

VDD

= 3.0V

Output Capacitance, C

OUT

TIMING CHARACTERISTICS

Aperture Delay, t

Aperture Jitter, t

RMS

Data Output Hold, t

10.7

Data Output Delay, t

11.7

Data Latency, t

LAT

For a Valid Sample (Note 2)

Cycles

Power-Up Initialization

Data Invalid Time (Note 2)

Cycles

Sample Clock Pulse Width (Low)

(Note 2)

11.25

12.5

Sample Clock Pulse Width (High)

(Note 2)

11.25

12.5

Sample Clock Duty Cycle Variation

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, A

VDD

(Note 2)

3.0

3.3

3.6

Digital Supply Voltage, D

VDD

(Note 2)

3.0

3.3

3.6

Supply Current, I

= 40MSPS

30.3

Power Dissipation

100

Offset Error Sensitivity,

VDD

or D

VDD

= 3.3V

0.125

LSB

Gain Error Sensitivity,

FSE

VDD

or D

VDD

= 3.3V

0.15

LSB

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

Electrical Specifications

VDD

= D

VDD

= +3.3V; V

= 1.50V; f

= 40MSPS at 50% Duty Cycle;

= 10pF; T

= 25

C; Unless Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HI2325

Part Number HI2325