CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

HC55171

5 REN Ringing SLIC for
ISDN Modem/TA and WLL

The HC55171 is backward compatible to the HC5517 with
the added capability of driving 5 REN loads. The HC55171 is
ideal for any modem or remote networking access
application that requires plain old telephone service POTS,
capability. The linear amplifier design allows a choice of
Sinusoidal, Square wave or Trapezoidal ringing. The voltage
feed architecture eliminates the need for a high current gain
node achieving improved system noise immunity, an
advantage in highly integrated systems.

The device is manufactured in a high voltage Dielectric
Isolation (DI) process with an operating voltage range from
-16V, for off-hook operation and -80V for ring signal injection.
The DI process provides substrate latch up immunity,
resulting in a robust system design.

Features

· 5 REN Thru SLIC Ringing Capability to 75V

PEAK

· Trapezoid, Square and Sinusoid Ringing Capability

· Bellcore Compliant Ringing Voltage Levels

· Lowest Component Count Trapezoidal Solution

· Single Additional +5V Supply

· Pin For Pin Compatible With HC5517

· DI Provides Latch-Up Immunity

Applications

· ISDN Internal/External Modems

· ISDN Terminal Adapters/Routers

· Wireless Local Loop Subscriber Terminals

· Cable Telephony Set-Top Boxes

· Digital Added Main Line

· Integrated LAN/PBX

· Related Literature

- AN9606, Operation of the HC5517/171 Evaluation

Board

- AN9607, Impedance Matching Design Equations

- AN9628, AC Voltage Gain

- AN9608, Implementing Pulse Metering

- AN9636, Implementing an Analog Port for ISDN Using

the HC5517

- AN549, The HC-5502X/4X Telephone Subscriber Line

Interface Circuits (SLIC)

Block Diagram

Ordering Information

PART NUMBER

TEMP. RANGE

(

PACKAGE

PKG.

NO.

HC55171IM

-40 to 85

28 Ld PLCC

N28.45

HC55171CM

0 to 75

28 Ld PLCC

N28.45

HC55171IB

-40 to 85

28 Ld SOIC

M28.3

HC55171CB

0 to 75

28 Ld SOIC

M28.3

TIP FEED

TIP SENSE

RING FEED

RING SENSE 2

BAT

AGND

BGND

4-WIRE

INTERFACE

BIAS

- IN 1

OUT 1

RING

LOOP CURRENT

DETECTOR

SHD

RTD

ALM
I

LMT

FAULT

DETECTOR

CURRENT

LIMIT

TST

RDI

IIL LOGIC INTERFACE

REF

RELAY

DRIVER

RDO

2-WIRE

INTERFACE

RTI

RING TRIP

DETECTOR

RING SENSE 1

Data Sheet

July 1998

File Number

4323.4

Absolute Maximum Ratings

= 25

Thermal Information

Maximum Supply Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

- V

BAT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V

Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V

Operating Conditions

Temperature Range

HC55171IM, HC55171IB . . . . . . . . . . . . . . . . . . . . -40

C to 85

HC55171CM, HC55171CB . . . . . . . . . . . . . . . . . . . . 0

C to 75

Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V
Positive Power Supply, V

. . . . . . . . . . . . . . . . . . . . . . . . +5V

Negative Power Supply, V

BAT

. . . . . . . . . . . . . . . . . . . .-16V to -80V

Thermal Resistance (Typical, Note 1)

(

C/W)

PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC, PLCC - Lead Tips Only)

Die Characteristics

Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 x 144
Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

BAT

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Unless Otherwise Specified, Typical Parameters are at T

= 25

C, Min-Max Parameters are over

Operating Temperature Range, V

BAT

= -24V, V

= +5V, AGND = BGND = 0V. All AC Parameters are specified

at 600

2-Wire terminating impedance.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

RINGING TRANSMISSION PARAMETERS

RING

Input Impedance

(Note 2)

5.4

4-Wire to 2-Wire Gain

RING

to V

T-R

(Note 2)

V/V

AC TRANSMISSION PARAMETERS

RX Input Impedance

300Hz to 3.4kHz (Note 2)

108

OUT1 Positive Output Voltage Swing

= 10k

(Note 2)

+2.5

OUT1 Negative Output Voltage Swing

= 10k

(Note 2)

-4.5

4-Wire Input Overload Level

300Hz to 3.4kHz R

= 1200

, 600

Reference

(Note 2)

+3.1

PEAK

2-Wire Return Loss

Matched for 600

, f = 300Hz (Note 2)

Matched for 600

, f = 1000Hz (Note 2)

Matched for 600

, f = 3400Hz (Note 2)

2-Wire Longitudinal to Metallic Balance
Off Hook

Per ANSI/IEEE STD 455-1976 300Hz to 3400Hz
(Note 2)

4-Wire Longitudinal Balance Off Hook

300Hz to 3400Hz (Note 2)

Longitudinal Current Capability

LINE

= 40mA, T

= 25

C (Note 2)

RMS

Insertion Loss, 2W-4W

0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3

0.05

0.2

Insertion Loss, 4W-2W

0dBmO,1kHz

0.05

0.2

Insertion Loss, 4W-4W

0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3

0.25

Frequency Response

300Hz to 3400Hz Referenced to Absolute Level
at 1kHz, 0dBm Referenced 600

0.02

0.06

HC55171

Level Linearity

+3 to 0dBm, Referenced to -10dBm (Note 2)

0.10

0 to -40dBm, Referenced to -10dBm (Note 2)

0.12

-40 to -55dBm, Referenced to -10dBm (Note 2)

0.30

Absolute Delay, 2W-4W

300Hz to 3400Hz (Note 2)

1.0

Absolute Delay, 4W-2W

300Hz to 3400Hz (Note 2)

1.0

Absolute Delay, 4W-4W

300Hz to 3400Hz (Note 2)

0.95

Transhybrid Loss

= 1V

P-P

at 1kH (Note 2)

Total Harmonic Distortion
2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire

Reference Level 0dBm at 600

300Hz to 3400Hz (Note 2)

-50

Idle Channel Noise
2-Wire and 4-Wire

C-Message (Note 2)

dBrnC

Psophometric (Note 2)

-87

dBmp

PSRR, V

to 2W

30Hz to 200Hz, R

= 600

(Note 2)

PSRR, V

to 4W

PSRR, VBAT to 2W

PSRR, VBAT to 4W

PSRR, V

to 2W

200Hz to 3.4kHz, R

= 600

(Note 2)

PSRR, V

to 4W

PSRR, VBAT to 2W

PSRR, VBAT to 4W

PSRR, V

to 2W

3.4kHz to 16kHz, R

= 600

(Note 2)

PSRR, V

to 4W

PSRR, VBAT to 2W

PSRR, VBAT to 4W

DC PARAMETERS

Loop Current Programming Range

(Note 3)

Loop Current Programming Accuracy

-10

+10

Loop Current During Power Denial

= 200

BAT

= -48V

Fault Current, Tip to Ground

(Note 2)

Fault Current, Ring to Ground

100

Fault Current, Tip and Ring to Ground

(Note 2)

130

Switch Hook Detection Threshold

Ring Trip Comparator Voltage Threshold

-0.28

-0.24

-0.22

Thermal ALARM Output

Safe Operating Die Temperature Exceeded
(Note 2)

160

Dial Pulse Distortion

(Note 2)

0.1

0.5

Electrical Specifications

Unless Otherwise Specified, Typical Parameters are at T

= 25

C, Min-Max Parameters are over

Operating Temperature Range, V

BAT

= -24V, V

= +5V, AGND = BGND = 0V. All AC Parameters are specified

at 600

2-Wire terminating impedance. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55171

UNCOMMITTED RELAY DRIVER

On Voltage, V

(RDO) = 30mA

0.2

0.5

Off Leakage Current

100

TTL/CMOS LOGIC INPUTS (F0, F1, RS, TST, RDI)

Logic Low Input Voltage

0.8

Logic High Input Voltage

2.0

5.5

Input Current

, 0V

-1

Input Current

, 0V

-100

LOGIC OUTPUTS (SHD, RTD, ALM)

Logic Low Output Voltage

LOAD

= 800

0.1

0.5

Logic High Output Voltage

LOAD

= 40

2.7

5.5

POWER DISSIPATION

Power Dissipation On Hook

= +5V, V

BAT

= -80V, R

LOOP

300

= +5V, V

BAT

= -48V, R

LOOP

150

Power Dissipation Off Hook

= +5V, V

BAT

= -24V, R

LOOP

= 600

= 25mA

280

= +5V, V

BAT

= -80V, R

LOOP

= +5V, V

BAT

= -48V, R

LOOP

= +5V, V

BAT

= -24V, R

LOOP

1.9

BAT

= +5V, V

- = -80V, R

LOOP

3.6

= +5V, V

- = -48V, R

LOOP

2.6

= +5V, V

- = -24V, R

LOOP

2.3

4.5

NOTES:

2. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon

initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and
specification compliance.

3. This parameter directly affects device junction temperature. Refer to Power Dissipation discussion of data sheet for design information.

Electrical Specifications

Unless Otherwise Specified, Typical Parameters are at T

= 25

C, Min-Max Parameters are over

Operating Temperature Range, V

BAT

= -24V, V

= +5V, AGND = BGND = 0V. All AC Parameters are specified

at 600

2-Wire terminating impedance. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55171

Functional Diagram

The truth table for the internal logic of the HC55171 is pro-
vided in the above table. This family of ringing SLICS can be
configured to support traditional unbalanced ringing and thru
SLIC balanced ringing. Refer to the HC5509A1R3060 for
unbalanced ringing application information. The device oper-
ating states used by thru SLIC ringing applications are loop
power denial and normal feed. During loop power denial, the
tip and ring amplifiers are disabled (high impedance) and the
DC voltage of each amplifier approaches ground. The SLIC
will not provide current to the subscriber loop during this mode
and will not detect loop closure. Voice transmission occurs
during the normal loop feed mode. During normal loop feed
the SLIC is completely operational and performs all transmis-
sion and supervisory functions.

Power Dissipation

Careful thermal design is required to guarantee that the
maximum junction temperature of 150

C of the device is not

exceeded. The junction temperature of the SLIC can be cal-
culated using:

Where T

is maximum ambient temperature and

is junc-

tion to air thermal resistance (and is package dependent).
The entire term in parentheses yields the SLIC power dissi-
pation. The power dissipation of the subscriber loop does
not contribute to device junction temperature and is sub-
tracted from the power dissipation term. Operating at 85

the maximum PLCC SLIC power dissipation is 1.18W. Like-
wise, the maximum SOIC SLIC power dissipation is 0.92W.

REF

OUT 1

R/20

R/2

TIP

90K

RING

4.5K

25K

100K

4.5K

90K

+2V

OP AMP

RING

RF2

BIAS

NETWORK

AGND

IIL LOGIC INTERF

TSD

RFC

ALM

RTD

SHD

TST

BAT

-IN 1

BGND

R = 108k

100K

90K

RTI

LMT

SENSE

SENSE 1

RING

SENSE 2

RDI

RDO

THERM

LTD

SHD

RTD

FAULT

DET

REF

VB/2

HC55171 DEVICE TRUTH TABLE

STATE

Loop power Denial Active

Power Down Latch RESET, Power on
RESET

RD Active

Normal Loop feed

BAT

LOOP

(

)

LOOP

(

)

(

)

(EQ. 1)

HC55171

Circuit Operation and Design Information

Introduction

The HC55171 is a high voltage Subscriber Line Interface Cir-
cuit (SLIC) specifically designed for through SLIC ringing
applications. Through SLIC ringing applications are broadly
defined as any application that requires ringing capability but
does not have the standard wired central office interface. The
most common implementation of the ringing SLIC is in the
analog pots port. The analog pots port provides the ringing
function as well as interface compatibility with answering and
fax machines.

Subscriber Line Interface Basics

The basic SLIC provides DC loop current to power the handset,
supports full duplex analog transmission between the handset
and CODEC, matches the impedance of the SLIC to the
impedance of the handset and performs loop supervision func-
tions to detect when the handset is off hook.

The ringing SLIC

adds through the SLIC ringing capability to this suite of fea-
tures. The analog interfaces of the SLIC are categorized as the
2-wire interface (high voltage DC, differential AC) and the 4-wire
interface (low voltage DC, single ended AC).

DC Loop Current

The Tip and Ring terminals of the subscriber line circuit are
biased at negative potentials with respect to ground. The Tip
terminal DC potential is slightly negative with respect to
ground, and the ring terminal DC potential is slightly positive
with respect to the battery voltage (resulting in a large nega-
tive voltage). The HC55171 typical Tip DC voltage is -4V and
the typical ring DC voltage is defined as V

BAT

+ 4V. For exam-

ple, when the battery voltage is -24V the ring voltage is -20V.

To clearly comprehend the Tip and Ring interface it is helpful
to understand that the handset and the SLIC constitute a DC
and AC current loop as shown in Figure 1. The loop is often
referred to as the subscriber loop.

When the handset is on hook (idle) the phone is an open cir-
cuit load and the DC loop current is zero. The SLIC can still
provide AC transmission in this condition, which supports
caller id services. The DC resistance of the off hook handset
is typically 400

. Since the Tip DC voltage is more positive

than the ring DC voltage, DC loop current flows from Tip to
Ring when the handset is off hook. The SLIC is designed
with feedback to limit the maximum loop current when the
handset is off hook.

Full Duplex Analog Transmission

Familiarity with the signal paths of the SLIC is critical in
understanding the full duplex transmission capability of the
device. The analog interfaces of the SLIC are categorized as
2-wire interfaces and 4-wire interfaces.

The 2-wire interface of the SLIC consists of the bidirectional
Tip and Ring terminals of the device. A differential transmit-
ter drives AC signals out of the Tip and Ring terminals to the
handset. A differential receiver across Tip and Ring receives
AC signals from the handset. The differential receiver is con-
nected across sense resistors that are in the Tip and Ring
signal paths. The differential transmitter and receiver con-
cept is depicted in Figure 2.

Since the receiver is connected across the transmit signal
path, one may deduce that in addition to receiving signals
from the handset, the receiver will detect part of the transmit
signal. Indeed this does occur and is the reason that all SLIC
circuits require a hybrid balance or echo cancellation func-
tion.

The 4-wire interface of the SLIC consists of the receive
(VRX) and transmit (OUT1) terminals. The 4-wire interfaces
are single ended signal paths. The receiver is a dedicated
input port and the transmitter is a dedicated output port. The
4-wire receive input of the SLIC drives the 2-wire differential
transmitter and the 2-wire differential receiver drives the 4-
wire transmit output.

The complete signal path for voice signals includes two digi-
tal data busses, a CODEC and a SLIC. There is a receive
data bus and transmit data bus, each with an independent 3-
wire serial interface. The CODEC contains a coder and
decoder. The coder converts the SLIC analog transmit out-
put to digital data for the transmit data bus. The receive digi-
tal data bus is converted to analog data and drives the SLIC
receive input.

The CODECs use logarithmic compression schemes to
extend the resolution of the 8-bit data to 14 bits. The
accepted compression schemes are A-law (Intersil CODEC -
CD22357A) and

-law (Intersil CODEC - CD22354A). The

complete signal path from the handset to the CODEC is
shown in Figure 3.

FIGURE 1. SUBSCRIBER LOOP

TIP

RING

SLIC

LOOP

CURRENT

FIGURE 2. DIFFERENTIAL TRANSMIT/RECEIVE CONCEPT

DIFFERENTIAL
TRANSMITTER

DIFFERENTIAL

RECEIVER

-1

HC55171

Impedance Matching

Impedance matching is used to match the AC source imped-
ance of the SLIC to the AC source impedance of the load.
When the impedance is matched, the voltage level at the
receive input of the SLIC will be the same voltage level that is at
the 2-wire differential output (i.e., Tip and Ring). Impedance
matching applies only to the 2-wire interface, not the 4-wire
interface.

Slic AC signal power levels are most commonly assigned the
units dBmO. The term dBmO refers to milliwatts in a 600

load. The typical AC power level is 0dBmO which is 1mW
referenced to a 600

load. The relationship between dBmO

and V

RMS

is provided in Equation 2.

Substituting 0dBmO into the equation should result in
0.7746 V

RMS

. For sinusoidal signals, multiply the RMS

voltage by 1.414 to obtain the peak sinusoidal voltage.

The SLIC impedance matching is achieved by applying a feed
back loop from the transmit output of the SLIC to the receive
input of the SLIC. The transmit output voltage of the HC55171
is proportional to the loop current (DC + AC) flowing in the sub-
scriber loop. The impedance matching feedback only uses the
AC portion of the transmit output voltage. Applying a voltage
gain to the feedback term and injecting it into the receive signal
path, will cause the SLIC to "synthesize" a source impedance
that is nonzero. Recall that the impedance matching sets the
SLIC source impedance equal to the load impedance.

The SLIC application circuit requires external sense resistors
in the Tip and Ring signal paths to achieve the differential
receive function. The sense resistors contribute to the source
impedance of the SLIC and are accounted for in the design
equations. Specifically, if the load impedance is 600

and

each sense resistor is 50

, the SLIC must synthesize an

additional source impedance of 500

(i.e., 600

- 2(50

)

In addition to the sense resistors, some applications may use a
protection resistor in each of the Tip and Ring leads as part of a
surge protection network. These resistors also contribute to the
SLIC source impedance and can be easily accounted for in the
design equations. If 50

protection resistors are added to the

prior example, the SLIC would then have to synthesize 400

match the load (i.e., 600

- 2(50

)

- 2(50

)

). A diagram

showing the impedance terms is shown in Figure 4.

Loop Supervision

The SLIC must detect when the subscriber picks up the
handset when the SLIC is not ringing the phone and when
the SLIC is ringing the phone. The HC55171 uses a switch
hook detector output to indicate loop closure when the SLIC
is not ringing the phone. When the SLIC is ringing the
phone, loop closure is indicated by the ring trip detector.

(Recall from earlier discussions that the subscriber loop is
open when the handset is on hook and closed when off
hook. The DC impedance of the handset when off hook is
typically 400

When the handset is off hook, DC loop current flows from
Tip to Ring and the transmit output voltage increases to a
negative value. In addition to interfacing to the CODEC and
providing the feedback for impedance matching, the transmit
output also drives the input to a voltage comparator. When
the comparator threshold is exceeded, the SHD output goes
to a logic low, indicating the handset is off hook. When the
call is terminated and the handset is returned on hook, the
transmit voltage decreases to zero, crossing the comparator
threshold and setting SHD to a logic high.

Loop closure must also be detected when the SLIC is ringing
the handset. The balanced ringing output of the SLIC coin-
cides with a zero DC potential between Tip and Ring. There-
fore the ring trip must be designed around an AC only
waveform at the transmit output. When the SLIC is ringing
and the handset is on hook, the echo of the ringing signal is
at the transmit output. When the handset goes off hook, the
amplitude of the ringing echo increases. The increase in
amplitude is detected by an envelope detector. When the
echo increases, the envelope detector output increases and
exceeds the ring trip comparator threshold. Then RTD goes
to a logic low, indicating the handset is off hook. When the
system controller detects a logic low on RTD, the ringing is
turned off and the Tip and Ring terminals return to their
typical negative DC potentials.

Design Equations and Operational Theory

The following discussion separates the SLICS's operation
into its DC and AC path, then follows up with additional cir-
cuit design and application information.

FIGURE 3. COMPLETE VOICE SIGNAL PATH

FIGURE 4. SLIC IMPEDANCE DIAGRAM

TIP

RING

OUT

OUT1

PCM

OUT

SLIC

ANALOG

DIGITAL

CODEC

-1

TIP

RING

RSYNTH

SLIC SOURCE IMPEDANCE

LOAD IMPEDANCE

dBmO

1000

RMS

(

)

600

------------------------

log

(EQ. 2)

HC55171

DC Operation of Tip and Ring Amplifiers

SLIC in the Active Mode

The tip and ring amplifiers are voltage feedback op amps
that are connected to generate a differential output (e.g., if
tip sources 20mA then ring sinks 20mA). Figure 5 shows the
connection of the tip and ring amplifiers. The tip DC voltage
is set by an internal +2V reference, resulting in -4V at the
output. The ring DC voltage is set by the tip DC output volt-
age and an internal V

BAT

/2 reference, resulting in V

BAT

+4V

at the output. (See Equation 3, Equation 4 and Equation 5.)

Transmit Output Voltage

The transmit output voltage in terms of loop current is
expressed as 200x I

LOOP

. The 200 term is actually formed

by the sum of twice the sense resistors and is shown in the
following equation.

This is a relationship that is critical when modifying the
sense resistor (R

, R

). The 200 term factors into the loop

current limit and loop detector functions of the SLIC.

Current Limit

The tip feed to ring feed voltage (Equation 3 minus
Equation 5) is equal to the battery voltage minus 8V. Thus,
with a 48 (24) volt battery and a 600

loop resistance,

including the feed resistors, the loop current would be
66.6mA (26.6mA). On short loops the line resistance often
approaches zero and there is a need to control the maximum
DC loop current.

Current limiting is achieved by a feedback network (Figure 5)
that modifies the ring feed voltage (V

) as a function of the

loop current. The output of the Transversal Amplifier (TA) has
a DC voltage that is directly proportional to the loop current.
This voltage is scaled by R

IL1

and R

IL2

. The scaled voltage

is the input to a transconductance amplifier (GM) that com-
pares it to an internal reference level. When the scaled volt-
age

exceeds

the

internal

reference

level,

the

transconductance amplifier sources current. This current
charges C

in the positive direction causing the ring feed

voltage (V

) to approach the tip feed voltage (V

). This

effectively reduces the tip feed to ring feed voltage (V

T-R

and holds the maximum loop current constant.

The maximum loop current is programed by resistors R

IL1

and R

IL2

as shown in Equation 7 (Note: R

IL1

is typically

100k

Figure 6 illustrates the relationship between V

T-R

and the

loop resistance. The conditions are shown for a battery
voltage of -24V and the loop current limit set to 25mA. For an
open circuit loop the tip feed and ring feed are at -4V and
-20V respectively. When the loop resistance decreases from
infinity to about 640

the loop current (obeying Ohm's Law)

increases from 0mA to the set loop current limit. As the loop
resistance continues to decrease, the ring feed voltage
approaches the tip feed voltage as a function of the
programmed loop current limit (Equation 7).

TIPFEED

R 2

-----------

(EQ. 3)

RINGFEED

BAT

---------------

R
R

----

TIPFEED

R
R

----

(EQ. 4)

RINGFEED

BAT

(EQ. 5)

FIGURE 5. OPERATION OF THE TIP AND RING AMPLIFIERS

OUT1

RING

BAT

90k

R/20

R/2

TIP FEED

RING FEED

OUT1

, V

GROUNDED FOR

TIP

RING

TRANSVERSAL

IL1

IL2

RF2

90k

INTERNAL

DC ANALYSIS

AMP

+2V REF

200

LOOP

2 R

(

)

LOOP

(EQ. 6)

LIMIT

0.6

(

)

IL1

IL2

(

)

200xR

IL2

(

)

--------------------------------------------------

(EQ. 7)

-25

-20

-15

-10

-5

LOOP RESISTANCE (

)

CONSTANT VOLTAGE

REGION

TIP AND RING V

GE (V)

FIGURE 6. V

T-R

vs R

BAT

= -24V,

LIMIT

= 25mA

)

250

500

750

RING FEED

= -20V

TIP FEED

= -4V

CURRENT LIMIT

REGION I

LOOP

= 25mA

HC55171

AC Voltage Gain Design Equations

The HC55171 uses feedback to synthesize the impedance
at the 2-wire tip and ring terminals. This feedback network
defines the AC voltage gains for the SLIC.

The 4-wire to 2-wire voltage gain (V

to V

) is set by the

feedback loop shown in Figure 7. The feedback loop senses
the loop current through resistors R

and R

, sums their volt-

age drop and multiplies it by 2 to produce an output voltage at
the V

pin equal to +4R

. The V

voltage is then fed into

the -IN1 input of the SLIC's internal op amp. This signal is multi-
plied by the ratio R

and fed into the tip current summing

node via the OUT1 pin. (Note: the internal V

BAT

/2 reference

(ring feed amplifier) and the internal +2V reference (tip feed
amplifier) are grounded for the AC analysis.)

The current into the summing node of TF amp is equal to:

Equation 9 is the node equation for the tip amplifier summing
node. The current in the tip feedback resistor (I

) is given in

Equation 7.

The AC voltage at V

is then equal to:

and the AC voltage at V

is:

The values for R

and R

are selected to match the

impedance

requirements

tip

and

ring,

for

information refer to AN9607 "Impedance Matching Design
Equations for the HC5509 Series of SLICs". The following
loop current calculations will assume the proper R

and

values for matching a 600

load.

The loop current (

) with respect to the feedback network, is

calculated in Equations 14 through 17. Where R

= 40k

, R

= 600

= R

= 50

Substituting the expressions for V

and V

Equation 15 simplifies to

Solving for

results in

Equation 17 is the loop current with respect to the feedback
network. From this, the 4-wire to 2-wire and the 2-wire to
4-wire AC voltage gains are calculated. Equation 18 shows
the 4-wire to 2-wire AC voltage gain is equal to 1.00.

Equation 19 shows the 2-wire to 4-wire AC voltage gain is
equal to -0.333.

Impedance Matching

The feedback network, described above, is capable of
synthesizing both resistive and complex loads. Matching the
SLIC's 2-wire impedance to the load is important to maxi-
mize power transfer and maximize the 2-wire return loss.
The 2-wire return loss is a measure of the similarity of the
impedance of a transmission line (tip and ring) and the
impedance at it's termination. It is a ratio, expressed in deci-
bels, of the power of the outgoing signal to the power of the
signal reflected back from an impedance discontinuity.

Requirements for Impedance Matching

Impedance matching of the HC55171 application circuit to the
transmission line requires that the impedance be matched to
points "A" and "B" in Figure 7. To do this, the sense and pro-
tection resistors R

, R

and R

must be accounted

for by the feedback network to make it appear as if the output
of the tip and ring amplifiers are at points "A" and "B". The
feedback network takes a voltage that is equal to the voltage
drop across the sense resistors and feeds it into the summing
node of the tip amplifier. The effect of this is to cause the tip
feed voltage to become more negative by a value that is pro-
portional to the voltage drop across the sense resistors R

and R

. At the same time the ring amplifier becomes more

positive by the same amount to account for resistors R

and R

The net effect cancels out the voltage drop across the feed
resistors. By nullifying the effects of the feed resistors the

OUT1

--------------------

-----------

(EQ. 8)

--------------------

-----------

(EQ. 9)

--------------------

-----------

(EQ. 10)

( )

(EQ. 11)

-----------

(EQ. 12)

-----------

(EQ. 13)

------------------------------------------------------------------------------

(EQ. 14)

-----------

------------------------------------------------------------------------------

(EQ. 15)

400 I

800

----------------------------------------

(EQ. 16)

600

-----------

(EQ. 17)

-----------

(

)

---------------------

600

-----------

600

(

)

---------------------------

(EQ. 18)

OUT1

-------------------

-----------

(

)

------------------------------------------

200

600

-----------

( )

600

-----------

600

(

)

----------------------------------

1
3

---

(EQ. 19)

HC55171

feedback circuitry becomes relatively easy to match the
impedance at points "A" and "B".

Impedance Matching Design Equations

Matching the impedance of the SLIC to the load is
accomplished by writing a loop equation starting at V

and

going around the loop to V

The loop equation to match the impedance of any load is as
follows (note: V

= 0 for this analysis):

Equation 22 can be separated into two terms, the feedback
(-8R

)) and the loop impedance (+4R

The result is shown in Equation 23. Figure 8 is a schematic
representation of Equation 18. To match the impedance of
the SLIC to the impedance of the load, set:

If R

is made to equal 8R

then:

Therefore to match the HC5517, with R

equal to 50

, to a

600

load:

and

To prevent loading of the V

output, the value of R

and

are typically scaled by a factor of 100:

Since the impedance matching is a function of the voltage
gain, scaling of the resistors to achieve a standard value is
recommended.

For complex impedances the above analysis is the same.

Refer to application note AN9607 ("Impedance Matching
Design Equations for the HC5509 Series of SLICs") for the
values of KR

and KR

for many worldwide typical line

impedances.

Through SLIC Ringing

The HC55171 uses linear amplification to produce the ringing
signal. As a result the ringing SLIC can produce sinusoid,
trapezoid or square wave ringing signals. Regardless of the
wave shape, the ringing signal is balanced. The balanced
waveform is another way of saying that the tip and ring DC
potentials are the same during ringing. The following figure
shows the Tip and Ring waveforms for sinusoid and trapezoid
wave shapes as can be displayed using an oscilloscope.

Pertinent Bellcore Ringing Specifications

Bellcore has defined bounds around the existing unbalanced
ringing signal that is supplied by the central office. The

= R

TIP

(

)

------------------------------

-------------

RX
R

-------------

FIGURE 7. AC VOLTAGE GAI

90k

R/2

RING

R/20

-----------

(EQ. 20)

-----------

(EQ. 21)

-----------

(EQ. 22)

-------------

-----------

[

]

(EQ. 23)

8RS

-------------

LOAD

SLIC

FIGURE 8. SCHEMATIC REPRESENTATION OF EQUATION 20

-----------

(EQ. 24)

(EQ. 25)

8 50

(

)

400

(EQ. 26)

600

200

400

(EQ. 27)

40k

(EQ. 28)

40k

(

)

100 Resistive

200

(

)

Reactive

100

--------------------------

(EQ. 29)

HC55171

HC55171 ringing SLIC meets the REN drive requirement, the
crest factor limitations and the minimum RMS ringing voltage.

The foremost requirement is that the ringing source must be
able to drive 5 REN. A REN is a ringer equivalence number
modeled by a 6.93k

resistor in series with a 8

F capacitor

(see Figure 10). The impedance of 1 REN at 20Hz is approx-
imately 7k

. 5 REN is equivalent to five of the networks in

parallel. Figure 10 provides the Bellcore REN models.

The crest factor of the ringing waveform is the ratio of the
peak voltage to the RMS voltage. For reference, the crest
factor of a sinusoid is 1.414 and of a square wave is 1.0.
Bellcore defines the crest factor range from 1.2 to 1.6. A sig-
nal with a crest factor between 1.2 and 1.414 resembles the
trapezoid of Figure 9. A signal with a crest factor between
1.414 and 1.6 resembles a "rounded triangular" wave shape
and is an inefficient waveform for the ringing SLIC.

The third pertinent Bellcore requirement is the that RMS ringing
voltage must be greater than 40V

RMS

at the telephone instru-

ment. The HC5517 is able to deliver 40V

RMS

at the end of

500

loops. The 500

loop drive capability of the HC5517 is

achieved with trapezoidal ringing.

Sinusoidal Ringing

The HC55171 uses the same sinusoidal application circuit
as the HC5517. The only difference being the values of three
components in the ring trip filter. The following table lists the
components and the different values required by each
device. All reference designators refer to the application

circuit published in the HC5517 and HC55171 data sheet.

The sinusoidal circuit published in the HC5517 can be used
as an additional reference circuit for the HC55171. To gener-
ate a sinusoid ringing signal, two conditions must be met on
the ringing (V

RING

) input of the SLIC.

The first condition is that a positive DC voltage, which is directly
related to the battery voltage, must be present at the ringing
input. The DC voltage is used to force the Tip and Ring DC out-
puts to half the battery voltage. Having both the Tip and Ring
amplifiers biased at the same DC voltage during ringing is one
characteristic of balanced ringing. The centering voltage (V

)

can be calculated from the following equation.

Substituting values of battery voltage, the centering voltage
is +1.8V for a -80V battery and +1.3V for a -60V battery.

The second condition that must be met for sinusoidal ringing
is a low level ringing signal must be applied to the ringing
input of the SLIC. The AC signal that is present at V

RING

will

be amplified by a gain of 20 through the Tip amplifier and a
then inverted through the ring amplifier, resulting in a differ-
ential gain of 40. The maximum low level amplitude that can
be injected for a given battery voltage can be determined
from the following equation.

The maximum output swing may be increased by driving the
V

RING

negative by 200mV. Equation 31 can then by

rewritten as:

Exceeding the maximum signal calculated from the above
equation will cause the peaks of the sinusoid to clip at
ground and battery. The compression will reduce the crest
factor of the waveform, producing a trapezoidal waveform.
This is just one method, though inefficient, for achieving trap-
ezoidal ringing. The application circuit provided with the
HC55171 has been specifically developed for trapezoidal
ringing and may also be used with the HC5517.

Trapezoidal Ringing

The trapezoidal ringing waveform provides a larger RMS
voltage to the handset. Larger RMS voltages to the handset
provide more power for ringing and also increase the loop
length supported by the ringing SLIC.

The HC55171 trapezoidal ringing application circuit will oper-
ate for loop lengths ranging from 0

to 500

. In addition, one

FIGURE 9. BALANCED RINGING WAVESHAPES

(A) SINUSOID

GROUND

BATTERY

TIP

RING

(B) TRAPEZOID

GROUND

BATTERY

TIP

RING

FIGURE 10. BELLCORE RINGER EQUIVALENCE MODELS

5 REN

1386

1 REN

6930

TABLE 1. RING TRIP COMPONENT DIFFERENCES

COMPONENT

HC5517

COMPONENT

HC55171

47k

RT3

51.1k

56.2k

RT1

49.9k

1.0

0.47

BAT

---------------

(EQ. 30)

RING Max

(

)

BAT

(

)

(EQ. 31)

RING Max

(

)

BAT

(

)

(EQ. 32)

HC55171

set of component values will satisfy the entire ringing loop
range of the SLIC. A single resistor sets the open circuit RMS
ringing voltage, which will set the crest factor of the ringing
waveform. The crest factor of the HC55171 ringing waveform
is independent of the ringing load (REN) and the loop length.
Another robust feature of the HC55171 ringing SLIC is the
ring trip detector circuit. The suggested values for the ring trip
detector circuit cover quite a large range of applications.

The assumptions used to design the trapezoidal ringing
application circuit are listed below:

· Loop current limit set to 25mA.

· Impedance matching is set to 600

resistive.

· 2-wire surge protection is not required.

· System able to monitor RTD and SHD.

· Logic ringing signal is used to drive RC trapezoid network.

Crest Factor Programming

As previously mentioned, a single resistor is required to set
the crest factor of the trapezoidal waveform. The only design
variable in determining the crest factor is the battery voltage.
The battery voltage limits the peak signal swing and
therefore directly determines the crest factor.

A set of tables will be provided to allow selection of the crest
factor setting resistor. The tables will include crest factors
below the Bellcore minimum of 1.2 since many ringing SLIC
applications are not constrained by Bellcore requirements.

The RMS voltage listed in the table is the open circuit RMS
voltage generated by the SLIC.

Ringing Voltage Limiting Factors

As the load impedance decreases (increasing REN), the
feedback used for impedance synthesis slightly attenuates
the ringing signal. Another factor that attenuates the ringing
signal is the voltage divider formed by the sense resistors
and the impedance of the ringing load. As the load imped-
ance decreases, the 100

of sense resistors becomes a

larger percentage of the load impedance.

If surge protection resistance must be used with the
trapezoidal circuit, the loop length performance of the circuit
will decrease. The decrease in ringing loop length is caused
by the addition of protection resistors in series with the Tip
and Ring outputs. The amount of protection resistance that
is added will subtract directly from the loop length. For exam-
ple if 30

protection resistors is used in each of the Tip and

Ring leads, the ringing loop length will decrease by a total of
60

. Therefore, subtracting 60

from the graphs will provide

the reduced loop length data.

Lab Measurements

The lab measurements of the trapezoidal ringing circuit were
made with the crest factor programming resistor set to 0

and the battery voltage set to -80V. The Bellcore suggested
REN model was used to simulate the various ringing loads.
A resistor in series with the Tip terminal was used to emulate
loop length.

A logic gate is used to drive the RC shaping network. When
the crest factor programming resistor is set to 0

, the output

impedance of the logic gate results in a 0.8V/ms slewing
voltage on C

TRAP

Each graph shows the RMS ringing voltage into a fixed REN
load versus loop length. The ringing voltage was measured
across the test load. Each test also verified proper operation
of the ring trip detector. Proper ring trip detector operation is
defined as a constant logic high while ringing and on hook
and a constant logic low when off hook is detected. The
component values in the application circuit provide a ring trip
response in the 100ms to 150ms range.

TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -80V

TRAP

RMS

TRAP

RMS

1.10

65.0

825

1.25

57.6

389

1.15

62.6

964

1.30

55.4

640

1.20

60.0

1095

1.35

53.3

TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -75V

TRAP

RMS

TRAP

RMS

1.10

60.9

1010

1.25

53.7

500

1.15

58.3

1190

1.30

51.6

791

1.20

55.9

1334

1.35

49.7

TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -65V

TRAP

RMS

TRAP

RMS

1.10

52.5

1330

1.25

45.9

660

1.15

49.8

1600

1.30

44.1

1040

1.20

47.8

1800

1.35

42.5

TABLE 5. CREST FACTOR PROGRAMMING RESISTOR FOR

BAT

= -60V

TRAP

RMS

TRAP

RMS

1.10

48.2

1460

1.25

42.0

740

1.15

45.6

1760

1.30

40.4

1129

1.20

43.7

2030

1.35

38.8

HC55171

Low Level Ringing Interface

The trapezoidal application circuit only requires a cadenced
logic signal applied to the wave shaping RC network to
achieve ringing. When not ringing, the logic signal should be
held low. When the logic signal is low, Tip will be near
ground and Ring will be near battery. When the logic signal
is high, Tip will be near battery and Ring will be near ground.

FIGURE 11. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 1

FIGURE 12. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 2

FIGURE 13. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 3

RMS RINGING V

100

200

300

400

500

LOOP IMPEDANCE

RMS RINGING V

100

200

300

400

500

LOOP IMPEDANCE

RMS RINGING V

100

200

300

400

500

LOOP IMPEDANCE

FIGURE 14. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 4

FIGURE 15. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 5

RMS RINGING V

100

200

300

400

500

LOOP IMPEDANCE

RMS RINGING V

100

200

300

400

500

LOOP IMPEDANCE

HC55171

Loop Detector Interface

The RTD output should be monitored for off hook detection
during the ringing period. At all other times, the SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and set-
ting F0 low for the entire duration of the ringing period. The
modifications to the application circuit for the single detector
interface are shown in Figure 16.

SLIC Operating State During Ringing

The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector inter-
face). Figure 17 shows the control interface for the dual
detector interface and the single detector interface.

Additional Application Information

Tip-to-Ring Open Circuit Voltage

The tip-to-ring open-circuit voltage, V

, of the HC55171

may be programmed to meet a variety of applications. The
design of the HC5517 defaults the value of V

to:

Using a zener diode clamping circuit, the default open circuit
voltage of the SLIC may be defeated. Some applications that
have to meet Maintenance Termination Unit (MTU) compli-
ance have a few options with the HC55171. One option is to
reduce the ringing battery voltage until MTU compliance is
achieved. Another option is to use a zener clamping circuit
on V

REF

to over ride the default open circuit voltage when

operating from a high battery.

If a clamping network is used it is important that it is disabled
during ringing. The clamping network must be disabled to
allow the SLIC to achieve its full ringing capability. A zener
clamping circuit is provided in Figure 18.

The following equations are used to predict the DC output of
the ring feed amplifier when using the zener clamping net-
work, V

RDC

Where V

is the zener diode voltage and V

and V

are

the saturation voltages of the pnp transistor. Using Equa-
tions 31 and 32, the tip-to-ring open-circuit voltage can be
calculated for any value of zener diode and battery voltage.

When the base of the pnp transistor is pulled high (+5V), the
transistor is off and the zener clamp is disabled. When the
base of the transistor is pulled low (0V) the transistor is on
and the zener will clamp as long as half the battery voltage is
greater than the zener voltage.

FIGURE 16. APPLICATION CIRCUIT WIRING FOR SINGLE

LOOP DETECTOR INTERFACE

HC55171

RING

TRAP

RING

TRAP

RDO 21

RDI 20

NU 23

ADDITIONAL PULL UP RESISTOR

FIGURE 17. DETECTOR LOGIC INTERFACES

RINGING

ACTIVE

RING

MODE

(LOGIC HI)

RTD

SHD

VALID DET

RINGING

ACTIVE

RING

MODE

(LOGIC HI)

SHD

VALID DET

(SINGLE DETECTOR INTERFACE)

(DUAL DETECTOR INTERFACE)

BAT

FIGURE 18. ZENER CLAMP CIRCUIT WITH DISABLE

+5V

47k

2N2907

REF

HC55171

BAT

---------------

RDC

BAT

---------------

(EQ. 33)

BAT

---------------

RDC

(

)

(

)

(EQ. 34)

BAT

---------------

TDC

BAT

---------------

(EQ. 35)

BAT

---------------

TDC

(

)

(

)

(EQ. 36)

HC55171

Polarity Reversal

The HC55171 supports applications that use polarity reversal
outside the speech phase of a call connection. The most com-
mon implementation of this type of polarity reversal is used
with pay phones. By reversing the polarity of the tip and ring
terminals of a pay phone, DC current changes direction in a
solenoid and the coins are released from the phone. To
reverse the polarity of the HC55171, simply toggle the V

RING

input high. Setting the V

RING

input high will cause Tip and

Ring to reverse polarity.

Transhybrid Balance

Since the receive signal and its echo are 180 degrees out of
phase, the summing node of an operational amplifier can be
used to cancel the echo. Nearly all CODECs have an inter-
nal amplifier for echo cancellation. The following Figure 19
shows the cancellation amplifier circuit.

When the SLIC is matched to a 600

load, the echo ampli-

tude is 1/3 the receive input amplitude. Therefore, by config-
uring the transhybrid amplifier with a gain of 3 in the echo
path, cancellation can be achieved. The following equations:

Substituting the fact that V

OUT1

is -1/3 of V

Since cancellation implies that under these conditions, the
output V

should be zero, set Equation 37 equal to zero and

solve for R

Another outcome of the transhybrid gain selection is the 2-
wire to 4-wire gain of the SLIC as seen by the CODEC. The
1/3 voltage gain in the transmit path is relevant to the receive
input as well as any signals from the 2-wire side. Therefore
by setting the V

OUT1

gain to three in the previous analysis,

the 2-wire to 4-wire gain was set to unity.

Single Supply Codec Interface

The majority of CODECs that interface to the ringing SLIC
operate from a single +5V supply and ground. Figure 20
shows the circuitry required to properly interface the ringing
SLIC to the single supply CODEC.

The CODEC signal names may vary from different
manufacturers, but the function provided will be the same.

The DC reference from the CODEC is used to bias the
analog signals between +5V and ground. The capacitors are
required so that the DC gain is unity for proper biasing from
the CODEC reference. Also, the capacitors block DC signals
that may interfere with SLIC or CODEC operation.

Layout Guidelines and Considerations

The printed circuit board trace length to all high impedance
nodes should be kept as short as possible. Minimizing length
will reduce the risk of noise or other unwanted signal pickup.
The short lead length also applies to all high gain inputs. The
set of circuit nodes that can be categorized as such are:

· V

pin 27, the 4-wire voice input.

· -IN1 pin 13, the inverting input of the internal amplifier.

· V

REF

pin 3, the noninverting input to ring feed amplifier.

· V

RING

pin 24, the 20V/V input for the ringing signal.

For multi layer boards, the traces connected to tip should not
cross the traces connected to ring. Since they will be carry-
ing high voltages, and could be subject to lightning or surge
depending on the application, using a larger than minimum
trace width is advised.

The 4-wire transmit and receive signal paths should not
cross. The receive path is any trace associated with the V

input and the transmit path is any trace associated with V

output. The physical distance between the two signal paths
should be maximized to reduce crosstalk.

The mode control signals and detector outputs should be
routed away from the analog circuitry. Though the digital sig-
nals are nearly static, care should be taken to minimize cou-
pling of the sharp digital edges to the analog signals.

The part has two ground pins, one is labeled AGND and the
other BGND. Both pins should be connected together as
close as possible to the SLIC. If a ground plane is available,
then both AGND and BGND should be connected directly to
the ground plane.

A ground plane that provides a low impedance return path
for the supply currents should be used. A ground plane pro-
vides isolation between analog and digital signals. If the lay-
out density does not accommodate a ground plane, a single
point grounding scheme should be used.

FIGURE 19. TRANHYBRID AMPLIFIER CIRCUIT

OUT1

--------

OUT1

--------

(EQ. 37)

--------

1
3

---

--------

(EQ. 38)

--------

(EQ. 39)

FIGURE 20. SINGLE SUPPLY CODEC INTERFACE

HC55171

CODEC

+2.5V

VOUT1

RX OUT

TX IN

HC55171

Pin Descriptions

PLCC

SYMBOL

DESCRIPTION

AGND

Analog Ground - Serves as a reference for the transmit output and receive input terminals.

Positive Voltage Source - Most Positive Supply.

REF

An external voltage connected to this pin will override the internal V

BAT

/2 reference.

Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier will
ramp close to the output voltage of the tip amplifier.

TTL compatible logic control input that must be tied high for proper SLIC operation.

SHD

Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition.

RTD

Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is
ringing.

TST

A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with the
ALM pin can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system
controller that monitors the ALM pin. When the ALM pin is active (low) the system controller issues a command to the
TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller.

ALM

A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die
temperature has been exceeded.

LMT

Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions.

OUT1

The analog output of the spare operational amplifier.

-IN1

The inverting analog input of the spare operational amplifier. The non-inverting input is internally connected to AGND.

TIP SENSE

An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor. Functions
with the RING terminal to receive voice signals and for loop monitoring purpose.

RING SENSE 1

An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions

with the TIP terminal to receive voice signals and for loop monitoring purposes.

RING SENSE 2

This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation.

Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed
and Ring Feed amplifiers deferentially.

Not used in this application.This pin should be left floating.

Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP
and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is necessary.

RDI

TTL compatible input to drive the uncommitted relay driver.

RDO

This is the output of the uncommitted relay driver.

BGND

Battery Ground - All loop current and some quiescent current flows into this terminal.

Not used in this application. This pin should be either grounded or left floating.

RING

Ring signal input.

This is the output of the tip amplifier.

This is the output of the ring amplifier.

BAT

The negative battery source.

RTI

Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection.

HC55171

Trapezoidal Ringing Application Circuit

Pinouts

HC55171 (PLCC)

TOP VIEW

HC55171 (SOIC)

TOP VIEW

VRING

RING SENSE 2

RING SENSE 1

BGND

RDO

RDI

GND

ILMT

OUT 1

-IN 1

TIP SENSE

VREF

SHD

RTD

TST

ALM

AGND

VREF

SHD

RTD

TST

ALM

ILMT

OUT 1

-IN 1

TIP SENSE

RTI

VRING

RDO

RING SENSE 2

RING SENSE 1

BAT

BGND

RDI

TIP

ILIMT 11

26 RF

25 TF

14 TIP SENSE

IL1

HC55171

REF

RING

SHD 7

RTD 8

ALM 10

9 TST

6 RS

RT3

RT2

-IN1 13

OUT1 12

RING

RTI 28

27 V

BAT

22 BGND

1 AGND

2 V

15 RING SENSE 1

16 RING SENSE 2

PS1

PS2

TRAP

IL2

V-REC

FIGURE 21. TRAPEZOIDAL RINGING APPLICATION CIRCUIT

RT1

V-XMIT

RING

BAT

5 F0

4 F1

SHD

RTD

ALM

VCC

TST

20 RDI

TRAP

HC55171

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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EUROPE
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Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

HC55171 Trapezoidal Ringing Application Circuit Parts List

COMPONENT

VALUE

TOLERANCE

RATING

COMPONENT

VALUE

TOLERANCE

RATING

U1 - Ringing Slic

HC55171

N/A

IL2

7.68k

1/8W

, R

49.9

1/2W

TRAP

App Driven

1/8W

, R

IL1

56.2k

1/8W

PS1

, C

PS2

0.1

10%

100V

RT1

49.9k

1/8W

, C

0.47

10%

50V

RT2

1.5M

1/8W

TRAP

4.7

10%

10V

RT3

51.1k

1/8W

, D

TRAP

1N914

Generic Rectifier Diode

45.3k

1/8W

HC55171

Part Number HC55171