4-62
CDP1857C
4-Bit Bus Buffer/Separator
Features
· Provides Easy Connection of I/O to CDP1800-Series
Microprocessor Data Bus
· Non-Inverting Fully Buffered Data Transfer
Description
The CDP1857C is a 4-bit CMOS non-inverting bus separator
designed for use in CDP1800-series microprocessor systems. It can
be controlled directly by a 1800-series microprocessor without the
use of additional components.
The CDP1857 is designed for use as a bus buffer or separator
between the 1800-series microprocessor data bus and I/O devices.
It provides a chip-select (CS) input signal which, when high (1),
enables the bus-separator three-state output drivers. The direction
of data flow, when enabled, is controlled by the MRD input signal.
In the CDP1857, when MRD = 1, it enables the three-state bus drivers
(DB0-DB3) and transfers data from the DATA-IN lines onto the data
bus. When MRD = 0, it disables the three-state bus drivers (DB0-
DB3) and enables the three-state data output drivers (DO0-DO3),
thus, transferring data from the data bus to the DATA-OUT terminals.
The CDP1857 can be used as a bidirectional bus buffer by connecting
the corresponding DI and DO terminals (Figure 1). The MRD output
signal from the 1800-series microprocessor has the correct polarity to
control the CDP1857 when it is used as I/O bus buffer/separator.
Therefore, the 1800-series microprocessor MRD signal can be
connected directly to the MRD input of CDP1857. See Function Table
1 for use of the CDP1857 as an I/O bus buffer/separator.
The CDP1857C is supplied in 16-lead hermetic, dual-in-line ceramic
packages (D suffix), and in 16-lead plastic packages (E suffix).
Pinout
16 LEAD DIP
TOP VIEW
Functional Diagram For CDP1857
Ordering Information
PART
NUMBER
TEMP. RANGE
PACKAGE
PKG. NO.
CDP1857CE
-40
o
C to +85
o
C
PDIP
E16.3
CDP1857CD
-40
o
C to +85
o
C
SBDIP
D16.3
TABLE 1. CDP1857 FUNCTION FOR I/O BUS SEPARATOR
OPERATION
CS
MRD
DATA BUS OUT
DB0-DB3
DATA OUT
DO0-DO3
0
X
High Impedance
High Impedance
1
0
High Impedance
Data Bus
1
1
Data In
High Impedance
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
DI0
DI1
DO0
DO1
DO2
DO3
V
SS
DI2
V
DD
DB0
DB1
DB2
DB3
MRD
DI3
CS
2
15
3
1
4
7
5
9
6
10
14
DB0
CS
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
16 = V
DD
8 = V
SS
MRD
13
DB1
12
DB2
11
DB3
March 1997
File Number
1192.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
4-63
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V
DD
)
(All Voltages Referenced to V
SS
Terminal) . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . . .±
10mA
Thermal Resistance (Typical)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
85
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
85
22
Device Dissipation Per Output Transistor
T
A
= Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T
A
)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40
o
C to +85
o
C
Storage Temperature Range (T
STG
). . . . . . . . . . . .-65
o
C to +150
o
C
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265
o
C
At distance 1/16
±
1/32 In. (1.59
±
0.79mm)
from case for 10s max
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Static Electrical Specifications
At T
A
= -40
o
C to +85
o
C, Except as Noted:
PARAMETER
SYMBOL
CONDITIONS
MIN
(NOTE 1)
TYP
MAX
UNITS
V
O
(V)
V
IN
(V)
V
DD
(V)
Quiescent Device Current
I
DD
-
0, 5
5
-
5
50
µ
A
Output Low Drive (Sink) Current
I
OL
0.4
0, 5
5
1.6
3.2
-
mA
Output High Drive (Source) Current
I
OH
4.6
0, 5
5
-1.15
-2.3
-
mA
Output Voltage Low-Level (Note 3)
V
OL
-
0, 5
5
-
0
0.1
V
Output Voltage High-Level (Note 3)
V
OH
-
0, 5
5
4.9
5
-
V
Input Low Voltage
V
IL
0.5, 4.5
-
5
-
-
1.5
V
Input High Voltage
V
IH
0.5, 4.5
-
5
3.5
-
-
V
Input Leakage Current
I
IN
Any Input
0, 5
5
-
-
1
µ
A
Operating Current (Note 2)
I
DD1
0, 5
0, 5
5
-
50
100
µ
A
Input Capacitance
C
IN
-
-
-
-
5
7.5
pF
NOTES:
1. Typical values are for T
A
=+25
o
C and nominal voltage.
2. Operating current measured in a CDP1802 system at 3.2MHz with outputs floating.
3. I
OL
= I
OH
= 1
µ
A.
Dynamic Electrical Specifications
At T
A
= -40
o
C to +85
o
C, V
DD
= 5V
±
5%, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, t
R
, t
F
= 20ns, C
L
= 100pF
PARAMETER
SYMBOL
V
DD
(V)
(NOTE 1)
TYP
MAX
UNITS
Propagation Delay Time:
MRD or CS to DO
t
ED
5
150
225
ns
MRD or CS to DB
t
EB
5
150
225
ns
DI to DB
t
IB
5
100
150
ns
DB to DO
t
BO
5
100
150
ns
NOTE:
1. Typical values are for T
A
= 25
o
C and nominal voltages.
CDP1857C
4-64
Recommended Operating Conditions
At T
A
= Full Package Temperature Range.For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
PARAMETER
MIN
MAX
UNITS
Supply-Voltage Range
4
6.5
V
Recommended Input Voltage Range
V
SS
V
DD
V
Timing Diagrams
FIGURE 1A. ENABLE TO DB TIME
FIGURE 1B. ENABLE TO DO TIME
FIGURE 1C. DI TO DB TIME
FIGURE 1D. DB TO DO TIME
FIGURE 1. TIMING DIAGRAMS FOR CDP1857C
MRD
CS
DI
DB
t
EB
t
EB
90%
10%
MRD
CS
DI
DB
t
ED
t
ED
90%
10%
VALID DATA
CS
DI
DB
t
IB
t
IB
MRD
VALID DATA
MRD
CS
DI
DB
t
BO
t
BO
CDP1857C
4-65
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Typical Applications
FIGURE 2. CDP1857 BIDIRECTIONAL BUS BUFFER OPERATION
FIGURE 3. CDP1857 BUS SEPARATOR OPERATION
CDP1857
BUS
DO0-DO3
DB0-DB3
DI0-DI3
MRD
CS
ENABLE BUS-TO-BUS
DATA TRANSFER
DIRECTION
CONTROL
BUS
MRD
CDP1800
SERIES
CPU
N0, N1
OR N2
MWR
DATA
BUS
CS
CDP1857
DO0-DO3
DB0-DB3
(4)
I/O
MRD
CDP1857
DI0-DI3
DB0-DB3
DO0-DO3
CS
(4)
(4)
(4)
(4)
(8)
DI0-0I3
MRD
D
A
T
A
B
US (8)
(8)
(4)
CDP1857C
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