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Part Number CD4051BMS

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7-937
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4051BMS, CD4052BMS
CD4053BMS
CMOS Analog
Multiplexers/Demultiplexers*
Description
CD4051BMS, CD4052BMS and CD4053BMS analog multi-
plexers/demultiplexers are digitally controlled analog
switches having low ON impedance and very low OFF leak-
age current. Control of analog signals up to 20V peak-to-
peak can be achieved by digital signal amplitudes of 4.5V to
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be con-
trolled; for VDD-VEE level differences above 13V, a VDD-
VSS of at least 4.5V is required). For example, if VDD =
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from -
13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
ranges, independent of the logic state of the control signals.
When a logic "1" is present at the inhibit input terminal all
channels are off.
The CD4051BMS is a single 8 channel multiplexer having
three binary control inputs, A, B, and C, and an inhibit input.
The three binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inputs to the output.
The CD4052BMS is a differential 4 channel multiplexer hav-
ing two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels
to be turned on and connect the analog inputs to the out-
puts.
The CD4053BMS is a triple 2 channel multiplexer having
three separate digital control inputs, A, B, and C, and an
inhibit input. Each control input selects one of a pair of chan-
nels which are connected in a single pole double-throw con-
figuration.
The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
Braze Seal DIP
*H4X
H4T
Frit Seal DIP
H1E
Ceramic Flatpack
H6W
*CD4051B Only
CD4052B, CD4053 Only
Features
· Logic Level Conversion
· High-Voltage Types (20V Rating)
· CD4051BMS Signal 8-Channel
· CD4052BMS Differential 4-Channel
· CD4053BMS Triple 2-Channel
· Wide Range of Digital and Analog Signal Levels:
- Digital 3V to 20V
- Analog to 20Vp-p
· Low ON Resistance: 125
(typ) Over 15Vp-p Signal
Input Range for VDD - VEE = 15V
· High OFF Resistance: Channel Leakage of
±
100pA
(typ) at VDD - VEE = 18V
· Logic Level Conversion:
- Digital Addressing Signals of 3V to 20V (VDD - VSS
= 3V to 20V)
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V);
See Introductory Text
· Matched Switch Characteristics: RON = 5
(typ) for
VDD - VEE = 15V
· Very Low Quiescent Power Dissipation Under All Digi-
tal Control Input and Supply Conditions: 0.2
µ
W (typ)
at VDD - VSS = VDD - VEE = 10V
· Binary Address Decoding on Chip
· 5V, 10V and 15V Parametric Ratings
· 100% Tested for Quiescent Current at 20V
· Maximum Input Current of 1
µ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
· Break-Before-Making Switching Eliminates Channel
Overlap
Applications
· Analog and Digital Multiplexing and Demultiplexing
· A/D and D/A Conversion
· Signal Gating
* When these devices are used as demultiplexers the "CHANNEL
IN/OUT" terminals are the outputs and the "COMMON OUT/IN" ter-
minals are the inputs.
File Number
3316
December 1992
7-938
CD4051BMS, CD4052BMS, CD4053BMS
Pinouts
CD4051BM
TOP VIEW
CD4052BMS
TOP VIEW
CD4053BMS
TOP VIEW
Functional Diagrams
CD4051BMS
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CHANNELS
6
COM OUT/IN
7
5
INH
VSS
VEE
VDD
1
0
3
A
B
C
2
IN/OUT
4
CHANNELS
IN/OUT
CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Y CHANNELS
2
COMMON "Y" OUT/IN
3
1
INH
VSS
VEE
VDD
1
COMMON "X" OUT/IN
0
3
A
B
2
IN/OUT
0
Y CHANNELS
IN/OUT
X CHANNELS
IN/OUT
X CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
bx
cy
OUT/IN CX or CY
IN/OUT CX
INH
VSS
VEE
VDD
OUT/IN ax or ay
ay
ax
A
B
C
OUT/IN bx or by
IN/OUT
by
IN/OUT
7
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
TG
TG
TG
TG
TG
TG
TG
TG
3
6
8
9
10
11
16
VEE
VSS
*
*
*
*
A
B
C
INH
VDD
COMMON
OUT/IN
CHANNEL IN/OUT
1
2
4
5
12
13
14
15
7
6
5
4
3
2
1
0
VDD
VSS
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
7-939
CD4051BMS, CD4052BMS, CD4053BMS
CD4052BMS
CD4053BMS
Functional Diagrams
(Continued)
7
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
TG
TG
TG
TG
TG
TG
TG
TG
3
6
8
9
10
16
VEE
VSS
*
*
*
A
B
INH
VDD
COMMON Y
OUT/IN
X CHANNELS IN/OUT
11
12
14
15
3
2
1
0
Y CHANNELS IN/OUT
1
4
2
5
0
1
2
3
COMMON X
OUT/IN
13
7
LOGIC
LEVEL
CONVERSION
TG
TG
TG
TG
TG
TG
9
8
10
11
16
VEE
VSS
*
*
*
A
B
C
VDD
IN/OUT
1
12
13
2
by
bx
ay
ax
OUT/IN
bx or by
3
5
cy
cx
4
15
14
OUT/IN
ax or ay
OUT/IN
cx or cy
6
*
INH
BINARY TO 1 OF 2
DECODERS WITH
INHIBIT
VDD
VSS
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
7-940
Specifications CD4051BMS, CD4052BMS, CD4053BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . .
80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . .
70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1
+25
o
C
-
10
µ
A
2
+125
o
C
-
1000
µ
A
VDD = 18V, VIN = VDD or GND
3
-55
o
C
-
10
µ
A
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
VDD = 18V
3
-55
o
C
-100
-
nA
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
VDD = 18V
3
-55
o
C
-
100
nA
On-State Resistance
RL = 10K Returned to
VDD - VSS/2
RON
VDD = 5V
VIS = VSS to VDD
1
+25
o
C
-
1050
2
+125
o
C
-
1300
3
-55
o
C
-
800
VDD = 10V
VIS = VSS to VDD
1
+25
o
C
-
400
2
+125
o
C
-
550
3
-55
o
C
-
310
VDD = 15V
VIS = VSS to VDD
1
+25
o
C
-
240
2
+125
o
C
-
320
3
-55
o
C
-
220
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
µ
A
1
+25
o
C
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
µ
A
1
+25
o
C
0.7
2.8
V
Functional
(Note 4)
F
VDD = 2.8V, VIN = VDD or GND
7
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND
7
+25
o
C
VDD = 18V, VIN = VDD or GND
8A
+125
o
C
VDD = 3V, VIN = VDD or GND
8B
-55
o
C
Input Voltage Low
(Note 2)
VIL
VDD = 5V = VIS thru 1k,
VEE = VSS
RL = 1k to VSS, |IIS| < 2
µ
A
OFF Channels
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
1.5
V
Input Voltage High
(Note 2)
VIH
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V = VIS thru 1K
VEE = VSS
RL = 1K to VSS, |ISS|, <2
µ
A
On All OFF Channels
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
4
V
Input Voltage High
(Note 2)
VIH
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
11
-
V
Off Channel Leakage
Any Channel OFF
Or
All Channels Off
(Common Out/In)
IOZL
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
+25
o
C
-0.1
-
µ
A
2
+125
o
C
-1.0
-
µ
A
VDD = 18V
3
-55
o
C
-0.1
-
µ
A
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
1
+25
o
C
-
0.1
µ
A
2
+125
o
C
-
1.0
µ
A
VDD = 18V
3
-55
o
C
-
0.1
µ
A
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
4. VDD = 2.8V/3.0V, RL = 200k to VDD
VDD = 20V/18V, RL = 10k to VDD
7-941
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (Notes 1, 2)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
(Note 1)
Address to Signal Out
Channels On or Off
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
+25
o
C
-
720
ns
10, 11
+125
o
C, -55
o
C
-
972
ns
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning On)
TPZH
TPZL
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
+25
o
C
-
720
ns
10, 11
+125
o
C, -55
o
C
-
972
ns
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning Off)
TPHZ
TPLZ
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
+25
o
C
-
450
ns
10, 11
+125
o
C, -55
o
C
-
608
ns
NOTES:
1. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
2. CL = 50pF, RL = 10K
, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
5
µ
A
+125
o
C
-
150
µ
A
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
10
µ
A
+125
o
C
-
300
µ
A
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
10
µ
A
+125
o
C
-
600
µ
A
Input Voltage Low
VIL
VDD = VIS = 10V, VEE = VSS
RL = 1K to VSS
|IIS|, 2
µ
A On/Off Channel
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
3
V
Input Voltage High
VIH
1, 2
+25
o
C, +125
o
C,
-55
o
C
+7
-
V
Propagation Delay
Address to Signal Out
(Channels On or Off)
TPHL
TPLH
VDD = 10V
VEE = VSS = 0V
1, 2, 3
+25
o
C
-
320
ns
VDD = 15V
1, 2, 3
+25
o
C
-
240
ns
VDD = 5V
VEE = -5V
1, 2, 3
+25
o
C
-
450
ns
Propagation Delay
Inhibit to Signal Out
(Channel Turning On)
TPZH
TPZL
VDD = 10V
VEE = VSS = 0V
1, 2, 3
+25
o
C
-
320
ns
VDD = 15V
1, 2, 3
+25
o
C
-
240
ns
VDD = 5V
VEE = -10V
1, 2, 3
+25
o
C
-
400
ns
Propagation Delay
Inhibit to Signal Out
(Channel Turning Off)
TPHZ
TPLZ
VDD = 10V
VEE = VSS = 0V
1, 2, 3
+25
o
C
-
210
ns
VDD = 15V
1, 2, 3
+25
o
C
-
160
ns
VDD = 5V
VEE = -15V
1, 2, 3
+25
o
C
-
300
ns
Input Capacitance
CIN
Any Address or Inhibit Input
1, 2
+25
o
C
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are char-
acterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.