4-231
Description
The CD22301 monolithic PCM repeater circuit is designed
for T1 carrier systems operating with a bipolar pulse train of
1.544Mbits/s. It can also be used in the T148 carrier system
operating with a ternary pulse train of 2.37Mbits/s. The cir-
cuit operates from a 5.1V
±
5% externally regulated supply.
The CD22301 provides active circuitry to perform all func-
tions of signal equalization and amplification, automatic line
buildout (ALBO), threshold detection, clock extraction, pulse
timing and buffered output formation.
Features
· Automatic Line Buildout
· Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1V
· Buffered Output
Applications
· Bipolar Carrier System . . . . . . . . . . . . .T1 1.544Mbits/s
· Ternary Carrier System . . . . . . . . . . . .T148 2.37Mbits/s
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
CD22301E
-40 to 85
18 Ld PDIP
E18.3
January 1997
Functional Diagram
ALBO OUTPUT CIRCUIT
17
1
2
3
4
V
CC
FROM ALBO
PEAK DETECTOR
V
EE
100
ALBO BIAS
AO1
50K
18K
15K
AO2
AO3
ALBO GND
100
100
100
100
100
1K
Pinout
CD22301 (PDIP)
TOP VIEW
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
ALBO GROUND
ALBO 1 OUTPUT
ALBO 2 OUTPUT
ALBO 3 OUTPUT
PREAMP INPUT +
PREAMP INPUT -
PREAMP OUTPUT +
PREAMP OUTPUT -
SUBSTRATE
ALBO BIAS
OSC BIAS
LC TANK INPUT
CLOCK LIMITER OUTPUT
TIMING PULSE INPUT
OUTPUT PULSE 1
OUTPUT PULSE 2
V
EE
V
CC
CD22301
Monolithic PCM Repeater
File Number
1368.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
4-232
CD22301
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Input Current (Into Pin 9 or 10). . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Peak Current (Into Pin 9 or 10). . . . . . . . . . . . . . . . . . . . . . . . 100mA
Input Surge Voltage (Between Pins 5 and 6, t = 10ms) . . . . . . . 50V
Output Surge Voltage (Between Pins 10 and 11, t = 1ms) . . . . . 50V
Power Dissipation
For T
A
= -40
o
C to 60
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
For T
A
= 60
o
C to 85
o
C . . . . Derate Linearly 12mW/
o
C to 200mW
Device Dissipation per Output Transistor
For T
A
= Full Package Temperature Range (All Types) . . . . . 100mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . -65
o
C
T
A
150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40
o
C
T
A
85
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
T
A
= 25
o
C, V
CC
= 5.1V
±
5% (See Figure 4)
PARAMETER
MIN
TYP
MAX
UNITS
STATIC DC VOLTAGES
ALBO Pins (Pins 2, 3, 4 and 17)
-
0
0.1
V
Pre Amp Inputs and Outputs (Pins 5, 6, 7 and 8)
2.4
2.9
3.4
V
Output Pulse 1, 2 (Pins 10 and 11)
-
5.1
-
V
Oscillator/Clock (Pins 12, 13, 15 and 16)
3.1
3.6
4.1
V
STATIC DC CURRENTS
I
CC
-
22
30
mA
Output Pulse 1, 2 (Pins 10 and 11)
-
0
100
µ
A
Electrical Specifications
T
A
= 25
o
C, V
CC
= 5.1V
±
5%
PARAMETER
SYMBOL
FIGURE
NOTE
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS
Preamplifier Input Impedance
Z
IN
7
20
-
-
k
Preamplifier Output Impedance
Z
OUT
7
-
-
2
k
Preamplifier Gain at 2.37MHz
A
O
7
47
50
-
dB
Preamplifier Output Offset Voltage
V
OUT
7
1
-50
0
50
mV
Clock Limiter Input Impedance
Z
IN
(CL)
5
2
10
-
-
k
ALBO Off Impedance
Z
ALBO
(off)
5
3
20
-
-
k
ALBO On Impedance
Z
ALBO
(on)
5
4
-
-
10
DATA Threshold Voltage
V
TH
(D)
6
5, 8
0.62
0.7
0.78
V
CLOCK Threshold Voltage
V
TH
(CL)
6
6, 8
0.92
1.1
1.28
V
ALBO Threshold
V
TH
(AL)
6
7, 8
1.4
1.5
1.6
V
V
TH
(D) as % of V
TH
(AL)
44
47
49
%
V
TH
(CL) as % of V
TH
(AL)
66
73
80
%
Buffer Gate Voltage (low)
V
OL
4
9
0.65
0.8
0.95
V
Differential Buffer Gate Voltage
V
OL
4
9
-0.15
0
0.15
V
Output Pulse Rise Time
t
R
4, 8
9, 10
-
-
40
ns
4-233
CD22301
Output Pulse Fall Time
t
F
4, 8
9, 10
-
-
40
ns
Output Pulse Width
t
W
4, 8
9, 10
290
324
340
ns
Pulse Width Differential
t
W
4, 8
9, 10
-10
0
10
ns
Clock Drive Current
I
CL
-
2
-
mA
NOTES:
1. No signal input. Measure voltage between pins 7 and 8.
2. Measure clock limiter input impedance at pin 15. See Figure 5.
3. Adjust potentiometer for 0V (See Figure 5). Measure ALBO off impedances from pins 2, 3 and 4 to pin 1.
4. Increase potentiometer until voltage at pin 17 = 2V (See Figure 5). Measure ALBO on impedances from pins 2, 3 and 4 to pin 1.
5. Adjust potentiometer for
V = 0V (See Figure 6). Then slowly increase
V in the positive direction until pulses are observed at the DATA
terminal.
6. Continue increasing
V until the DC level at the clock terminal drops to 4V (See Figure 6).
7. Continue increasing
V until the ALBO terminal rises to 1V (See Figure 6).
8. Turn potentiometer in the opposite direction and measure negative threshold voltages by repeating tests outlined in notes 5, 6 and 7.
9. Set e
IN
= 2.75mV
RMS
at f
1.185MHz. Adjust frequency until maximum amplitude is obtained at pin 15. Observe output pulses at pins
10 and 11.
10. Adjust input signal amplitude until pulses just appear in outputs. Increase input amplitude by 3dB.
Electrical Specifications
T
A
= 25
o
C, V
CC
= 5.1V
±
5% (Continued)
PARAMETER
SYMBOL
FIGURE
NOTE
MIN
TYP
MAX
UNITS
9
8
7
6
5
3
2
4
1
18
17
16
15
14
11
10
12
13
FF
FF
TIMING
PULSE
AMPLIFIER
LIMITER
CLOCK
CIRCUIT
SEE FIG. 2
ALBO
OUTPUT
CIRCUIT
SEE
FIG. 1
GATE
GATE
AO1
AO2
AO3
PULSE
INPUT
430
1.8K
8.2K
2.7K
470
µ
H
2200pF
510
82pF
0.1
µ
F
0.1
µ
F
4.53K
1.33K
150pF
6.19K
15
µ
H
1500pF
0.1
µ
F
ALBO
GND
SUBSTRATE
ALBO
BIAS
1
µ
F
+
PEAK
DETECTOR
CLOCK THRESHOLD
COMPARATOR
DATA THRESHOLD
COMPARATOR
17
µ
H
0.1
µ
F
600 - 800pF
120K
BIAS
LC TANK
INPUT
V
CC
V
EE
V
CC
100
µ
H
PULSE
OUTPUT
PHASE
SHIFT
NETWORK
3.83K
33pF
PRE-
AMPLIFIER
130
FIGURE 1. TYPICAL 1.544MHz T1 REPEATER SYSTEM
4-234
CD22301
FIGURE 2. CLOCK INTERFACE CIRCUIT
FIGURE 3. PHASE-SHIFT INTERFACE CIRCUITS
FIGURE 4. DC AND OUTPUT PULSE TEST CIRCUIT
FIGURE 5. TEST CIRCUIT FOR IMPEDANCE MEASUREMENT
16
15
V
CC
TO AMPLIFIER
V
EE
5.1K
5.1K
FROM CLOCK
THRESHOLD DETECTOR
13
12
5.5K
V
CC
V
EE
FROM
LIMITER
12K
V
EE
V
CC
TO TIMING
PULSE
AMPLIFIER
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
0.1
µ
F
0.001
µ
F
0.1
µ
F
8.2k
8.2k
0.68
µ
F
1
µ
F
91k
0.1
µ
F
3.83k
100
µ
H
130
130
20
pF
L
1
C
1
V
CC
= 5.1V
PULSE OUTPUT
C
1
AND L
1
RESONATE AT 1.272MHz
e
IN
(NOTE)
(NOTE)
NOTE:
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
0.1
µ
F
0.01
µ
F
5K
V
CC
= 5.1V
4-235
CD22301
FIGURE 6. TEST CIRCUIT FOR THRESHOLD VOLTAGE MEASUREMENT
FIGURE 7. PREAMPLIFIER GAIN AND IMPEDANCE MEASUREMENT CIRCUIT
FIGURE 8. OUTPUT PULSE WAVEFORM
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
1
µ
F
1
µ
F
1
µ
F
1
µ
F
0.1
µ
F 75
130
DATA
V
CLOCK
V
CC
= 5.1V
2.75V
RMS
at
1.185MHz
IN4152
0.1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
8.2
k
8.2k
8.2k
5k
8.2k
3V +
-
2k
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
NC
e
in
1.0
µ
F
50
200
k
1.0
µ
F
200k
NC
NC
0.1
µ
F
V
CC
= 5.1V
100%
90%
50%
10%
0%
t
R
t
W
t
F
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