1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
©
Intersil Corporation 1999
Features
· Output Current Drive Capability
- All Outputs ON, Equal . . . . . . . . . . . . . . 0.625A Each
- Per Output Individually . . . . . . . . . . . . . . . . . 1A Each
- Maximum Total of Outputs ON . . . . . . . . . . . . . . . .5A
· High Voltage Power BiMOS Outputs
- 8 Open Drain NDMOS Drivers
- Individual Output Latch
- Over-Current Limit Protection . . . . . . . . . . . . . 1.05A
- Over-Voltage Clamp Protection. . . . . . . . . . . . . . . 30V
· High Speed CMOS Logic Control
- Low Quiescent I
DD
Current . . . . . . . . . . . . . . . . . 5mA
- SPI Bus Controlled Interface
- Individual Fault Unlatch and Feedback
- Common Reset Line
· Operating Temperature Range . . . . . . . -40
o
C to 125
o
C
Applications
· Automotive and Industrial Systems
· Solenoids, Relays and Lamp Drivers
· Logic and
µ
P Controlled Drivers
· Robotic Controls
Description
The CA3282 is a logic controlled, eight channel octal power
driven. The serial peripheral interface (SPI) utilized by the
CA3282 is a serial synchronous bus compatible with Intersil
CDP68HC05, or equivalent, microcomputers. As shown in
the Block Diagram for the CA3282 each of the open drain
NDMOS output drivers has individual protection for over-volt-
age and over-current. Each output channel has separate
output latch control with fault unlatch and diagnostic feed-
back. Under normal ON conditions, each output driver is in a
low, saturation state. Comparators in the diagnostic circuitry
monitor the output drivers to determine if an out of saturation
condition exists. If a comparator senses a fault, the respec-
tive output driver is unlatched. In addition, over current pro-
tection is provided with current limiting in each output,
independent of the diagnostic feedback loop.
The CA3282 is fabricated in a Power BiMOS IC process, and is
intended for use in automotive and other applications having a
wide range of temperature and electrical stress conditions. It is
particularly suited for driving lamps, relays, and solenoids in
applications where low operating power, high breakdown volt-
age, and high output current at high temperatures is required.
The CA3282 is supplied in 15 lead plastic SIP package with
lead forms for either vertical or surface mount.
Ordering Information
PART
NUMBER
TEMP.
RANGE(
o
C)
PACKAGE AND
LEAD FORM
PKG
NO.
CA3282AS1
-40 to 125
15 Ld Plastic SIP
Staggered Vertical
Z15.05A
CA3282AS2
-40 to 125
15 Ld Plastic SIP
Surface Mount
Z15.05B
Pinout
CA3282 (SIP)
TOP VIEW
Block Diagram
NOTE:
HEAT SINK TAB
INTERNALLY
CONNECTED TO
GROUND (V
SS
)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
RESET
V
DD
MISO
V
SS
MOSI
SCK
CE
OUTPUT 0
OUTPUT 1
OUTPUT 2
OUTPUT 3
MOSI
SCK
MISO
CE
RESET
SHIFT
REGISTER
OUTPUT
LATCH
CURRENT
LIMIT
CONTROL
LOGIC
DIAGNOSTIC
CIRCUITRY
OUTPUT #0
(1 OF 8)
TO DRIVERS
1 THRU 7
SPI INTERF
A
CE CIRCUIT
June 1998
CA3282
Octal Low Side Power Driver
with Serial Bus Control
File Number
2767.6
2
Absolute Maximum Ratings
Thermal Information
Output Voltage, V
O
(Note 1) . . . . . . . . . . . . . . . . . . . . . V
OC
(Clamp)
Output Load Current, I
LOAD
(Per Output, Individual) . . . . . . . . . 1A
Output Load Current, I
LOAD
(All 8 Outputs ON, Equal I
OUT
) . . . . .
0.625A
Output Load Current, I
LOAD
(Max. Total of Outputs ON) . . . . 5.0A
DC Logic Supply, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.7 to +7V
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . -40
o
C to 125
o
C
Junction Temperature Range . . . . . . . . . . . . . . . . . -40
o
C to 150
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
JC
(
o
C/W)
Plastic SIP
No Heat Sink . . . . . . . . . . . . . . . . . . .
45
N/A
Infinite Heat Sink . . . . . . . . . . . . . . . . .
N/A
3
Power Dissipation
Up to 125
o
C w/o Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . 0.56W
Above 125
o
C w/o Heat Sink . . . . . . .Derate Linearly at 22mW/
o
C
Up to 125
o
C w/Infinite Heat Sink . . . . . . . . . . . . . . . . . . . . 8.33W
Above 125
o
C w/Infinite Heat Sink. . . . Derate Linearly at 333mW/
o
C
Maximum Storage Temperature Range . . . . . . . . . -55
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . 265
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the
Output Clamp Voltage, V
OC
.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= 5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Quiescent Supply Current, ON
I
DD
All Outputs ON, 0.5A Load Per Output
-
5
10
mA
Quiescent Supply Current, OFF
I
DD
All Outputs OFF
-
0.2
-
mA
Output Clamping Voltage
V
OC
I
LOAD
= 0.5A, Output Programmed OFF
27
32
40
V
Output Clamping Energy
E
OC
I
LOAD
= 0.5A, Output ON
20
-
-
mJ
Output Leakage Current
I
O LEAK
Output Programmed OFF
V
O
= 24V
-
150
1000
µ
A
V
O
= 14V
-
150
500
µ
A
V
O
= 5V
-
150
200
µ
A
Output ON Resistance
r
DS(ON)
I
LOAD
= 0.5A (Note 3)
-
-
1
Output Current Limit
I
O LIMIT
Output Programmed ON, V
OUT
> 3V
1.05
1.5
-
A
Turn-On Delay
t
PHL
I
O
= 500mA, No Reactive Load
-
1
10
µ
s
Turn-Off Delay
t
PLH
I
O
= 500mA, No Reactive Load
-
2
10
µ
s
Fault Reference Voltage
V
OREF
Output Programmed ON, Fault Detected
If V
O
> V
OREF
1.6
1.8
2.0
V
Fault Reset Delay (After CE Low
to High Transition)
t
UD
See Figure 1
50
80
250
µ
s
Output OFF Voltage
V
OFF
Output Programmed OFF, Output Pin
Floating
-
0
1
V
LOGIC INPUTS
(MOSI, CE, SCK and RESET)
Threshold Voltage at Falling
Edge
V
T-
V
DD
= 5V
±
10%
0.2V
DD
0.3V
DD
-
V
Threshold Voltage at Rising
Edge
V
T+
V
DD
= 5V
±
10%
-
0.6V
DD
0.7V
DD
V
Hysteresis Voltage
V
H
V
T+
- V
T-
0.85
1.4
2.25
V
Input Current
I
I
V
DD
= 5.5V, 0 < V
I
< V
DD
-10
-
+10
µ
A
Input Capacitance
C
I
0 < V
I
< V
DD
-
-
20
pF
LOGIC OUTPUT
(MISO)
Output LOW Voltage
V
OL
I
OL
= 1.6mA
-
0.2
0.4
V
Output HIGH Voltage
V
OH
I
OL
= 0.8mA
V
DD
- 1.3V
V
DD
- 0.2V
-
V
CA3282
3
Output Three State Leakage
Current
I
OL
V
DD
= 5.25V, 0 < V
O
< V
DD
,
CE Pin Held High
-10
-
+10
µ
A
Output Capacitance
C
OUT
0 < V
O
< V
DD
, CE Pin Held High
-
-
20
pF
Electrical Specifications
V
DD
= 5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Serial Peripheral Interface Timing
(See Figure 1B)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Frequency
f
OPER
D.C.
Note 4
3.0
MHz
Enable Lead Time
(2)
t
LEAD
-
<100
200
ns
Enable Lag Time
(3)
t
LAG
-
<100
200
ns
Clock HIGH Time
(4)
t
wSCK
H
-
50
100
ns
Clock LOW Time
(5)
t
wSCK
L
-
50
100
ns
Data Setup Time
(6)
t
SU
-
20
50
ns
Data Hold Time
(7)
t
H
-
20
50
ns
Enable Time
(8)
t
EN
-
50
100
ns
Disable Time
(9)
t
DIS
-
150
300
ns
Data Valid Time
(10)
t
V
-
75
150
ns
Output Data Hold Time
(11)
t
HO
0
50
-
ns
Rise Time (MISO Output)
(12)
t
rSO
V
DD
= 20% to 70%, C
L
= 200pF
-
35
100
ns
Rise Time SPI Inputs (SCK, MOSI, CE)
(12)
t
rSI
V
DD
= 20% to 70%, C
L
= 200pF
-
-
50
ns
Fall Time (MISO Output)
(13)
t
fSO
V
DD
= 70% to 20%, C
L
= 200pF
-
45
100
ns
Fall Time SPI Inputs (SCK, MOSI, CE)
(13)
t
fSI
V
DD
= 70% to 20%, C
L
= 200pF
-
-
50
ns
NOTES:
3. Refer to Figure 4A for I
OUT
current vs V
SAT
voltage. Typical r
DS(ON)
values are given for -40
o
C, 25
o
C, 105
o
C and 125
o
C temperatures.
4. The Maximum Operating Frequency is typically greater than 10MHz but it is application limited primarily by external SPI input rise/fall
times and MISO output loading.
Timing Diagrams
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
CE
SCK
MSB 6 5 4 3 2 1 LSB
(CPOL = 0, CPHA = 1)
INTERNAL STROBE FOR DATA CAPTURE
CA3282
4
Signal Descriptions
Power Output Drivers, Output 0 - Output 7 - The input and
output bits corresponding to Output 0 thru Output 7 are
transmitted and received most significant bit (MSB) first via
the SPI bus. The outputs are provided with current limiting
and voltage sense functions for fault indication and protec-
tion. The nominal load current for these outputs is 500mA,
with current limiting set to a minimum of 1.05A. An on-chip
clamp circuit capable of handling 500mA is provided at each
output for clamping inductive loads.
RESET - Active low reset input. When this input line is low,
the shift register and output latches are configured to turn off
all output drivers. A power on clear function may be imple-
mented by connecting this pin to V
DD
with an external resis-
tor, and to V
SS
with an external capacitor. In any case, this
pin must not be left floating.
CE - Active low chip enable. Data is transferred from the shift
register to the outputs on the rising edge of this signal. The
falling edge of CE loads the shift register with the output volt-
age sense bits coming from the output stages. The output
driver for the MISO pin is enabled when this pin is low. CE
must be a logic low prior to the first serial clock (SCK) and
must remain low until after the last (eighth) serial clock cycle.
A low level on CE also activates an internal disable circuit
used for unlatching output states that are in a fault mode as
FIGURE 1B.
SPI TIMING DIAGRAM
FIGURE 2. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET
Timing Diagrams
(Continued)
CE
(INPUT)
SCK
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
DRIVER
OUTPUT
HIGH
Z
LAST BIT
TRANSMITTED
D70
D60
D10
D71
D61
D11
OLD
FAULT-INDUCED
TURN-OFF
t
PHL
t
PLH
t
UD
(9)
(11)
(10)
(3)
(7)
(6)
(5)
(12)
(13)
(1)
(4)
(2)
(8)
NEW
OLD
NEW
FAULTS
RESET
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RESET
CE
SCK
MOSI
MISO
OUTPUTS
CA3282
5
sensed by an out of saturation condition. A high on CE
forces MISO to a high impedance state. Also, when CE is
high, the octal driver ignores the SCK and MOSI signals.
SCK, MISO, MOSI - See Serial Peripheral Interface (SPI)
section in this data sheet.
V
DD
and V
SS
(GND) - Positive and negative power supply
lines.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) utilized by the CA3282
is a serial synchronous bus for control and data transfers.
The Clock (SCK), which is generated by the microcomputer,
is active only during data transfers. In systems using
CDP68HC05 family microcomputers, the inactive clock
polarity is determined by the CPOL bit in the microcom-
puter's control register. The CPOL bit is used in conjunction
with the clock phase bit, CPHA to produce the desired clock
data relationship between the microcomputer and octal
driver. The CPHA bit in general selects the clock edge which
captures data and allows it to change states. For the
CA3282, the CPOL bit must be set to a logic zero and the
CPHA bit to a logic one. Configured in this manner, MISO
(output) data will appear with every rising edge SCK, and
MOSI (input) data will be latched into the shift register with
every falling edge of SCK. Also, the steady state value of the
inactive serial clock, SCK, will be at a low level. Timing dia-
grams for the serial peripheral interface are shown in Figure 1.
SPI Signal Descriptions
MOSI (Master Out/Slave In) - Serial data input. Data bytes
are shifted in at this pin, most significant bit (MSB) first. The
data is passed directly to the shift register which in turn con-
trols the latches and output drivers. A logic "0" on this pin will
program the corresponding output to be ON, and a logic "1"
will turn it OFF.
MISO (Master In/Slave Out) - Serial data output. Data bytes
are shifted out at this pin, most significant bit (MSB) first.
This pin is the serial output from the shift register and is
three stated when CE is high. A high for a data bit on this pin
indicates that the corresponding output is high. A low on this
pin for a data bit indicates that the output is low. Comparing
the serial output bits with the previous input bits, the micro-
computer implements the diagnostic data supplied by the
CA3282.
SCK - Serial clock input. This signal clocks the shift register
SCK and new MOSI (input) data will be latched into the shift
register on every falling edge of SCK. The SCK phase bit,
CPHA, and polarity bit, CPOL, must be set to 1 and 0,
respectively in the microcomputer's control register.
Functional Descriptions
The CA3282 is a low operating power, high voltage, high cur-
rent, octal power driver featuring eight channels of open
drain NDMOS output drivers. The drivers have low satura-
tion voltage and output short circuit protection, suited for
driving resistive or inductive loads such as lamps, relays and
solenoids. Data is transmitted to the device serially using the
Serial Peripheral Interface (SPI) protocol. Each channel is
independently controlled by an output latch and a common
RESET line that disables all eight outputs. Byte timing with
asynchronous reset is shown in Figure 4. The circuit
receives 8-bit serial data by means of the serial input
(MOSI), and stores this data in an internal register to control
the output drivers. The serial output (MISO) provides 8-bit
diagnostic data representing the voltage level at the driver
output. This allows the microcomputer to diagnose the con-
dition at the output drivers. The device is selected when the
chip enable (CE) line is low. When (CE) is high, the device is
deselected and the serial output (MISO) is placed in a three-
state mode. The device shifts serial data on the rising edge
of the serial clock (SCK), and latches data on the falling
edge. On the rising edge of chip enable (CE), new input data
from the shift register is latched in the output drivers. The
falling edge of chip enable (CE) transfers the output drivers
fault information back to the shift register. The output drivers
have low ON voltage at rated current, and are monitored by
a comparator for an out of saturation condition, in which
case the output driver with the fault becomes unlatched and
diagnostic data is sent to the microcomputer via the MISO
line. A typical microcomputer interface circuit is shown in
Figure 2. Also, the CA3282 may be cascaded with another
CA3282 octal driver.
Shift Register
The shift register has both serial and parallel inputs and out-
puts. Serial output and input data are simultaneously trans-
ferred to and from the SPI bus. The parallel outputs are
latched into the output latch in the CA3282 at the end of a
data transfer. The parallel inputs jam diagnostic data into the
shift register at the beginning of a data transfer cycle.
Output Latch
The output latch holds input data from the shift register
which is used to activate the outputs. The latch circuit may
be cleared by a fault condition (to protect the overloaded out-
puts), or by the RESET signal.
PORT
MOSI
MISO
SCK
MOSI
MISO
SCK
RESET
CDP68HC05C4
MICROCOMPUTER
CA3282
FIGURE 3. TYPICAL MICROCOMPUTER INTERFACE WITH
THE CA3282
CE
RESET
CA3282
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