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Part Number 5962F9853501VEC

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1
December 1997
ACTS138MS
Radiation Hardened
TTL Input, 3-to-8 Line Decoder/Demultiplexer
Features
· QML Qualified Per MIL-PRF-38535 Requirements
· 1.25Micron Radiation Hardened SOS CMOS
· Radiation Environment
- Latch-up Free Under any Conditions
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity . . . . . . . . . . . <1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm
2
)
· Input Logic Levels . . . . . . . . . . V
IL
= 0.8V, V
IH
= (Vcc/2)
· Output Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±
12mA
· Quiescent Supply Current. . . . . . . . . . . . . . . . . . . .20
µ
A
· Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
Applications
· Memory Decoding
· Data Routing
· Code Conversion
Description
The Radiation Hardened ACTS138MS is an Inverting 3-to-8
Line Decoder/Demultiplexer with three TTL level binary
select inputs (A
0
, A
1
and A
2
). If the device is enabled, these
inputs determine which one of the eight normally high out-
puts will go low.
Two active low and one active high enable inputs (E
1
, E
2
and
E
3
) are provided to make cascaded decoder designs easier
to implement.
The ACTS138MS is fabricated on a CMOS Silicon on Sap-
phire (SOS) process, which provides an immunity to Single
Event Latch-up and the capability of highly reliable perfor-
mance in any radiation environment. These devices offer
significant power reduction and faster performance when
compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACTS138 are
contained in SMD 5962-98535. A "hot-link" is provided
on our homepage with instructions for downloading.
http://www.intersil.com/data/sm/index.htm
Ordering Information
Pinouts
ACTS138 (SBDIP)
TOP VIEW
ACTS138 (FLATPACK)
TOP VIEW
SMD PART NUMBER
INTERSIL PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
CASE OUTLINE
5962F9853501VEC
ACTS138DMSR-02
-55 to 125
16 Ld SBDIP
CDIP2-T16
N/A
ACTS138D/Sample-02
25
16 Ld SBDIP
CDIP2-T16
5962F9853501VXC
ACTS138KMSR-02
-55 to 125
16 Ld Flatpack
CDFP4-F16
N/A
ACTS138K/Sample-02
25
16 Ld Flatpack
CDFP4-F16
N/A
ACTS138HMSR-02
25
Die
N/A
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A
0
A
1
A
2
E
1
E
2
E
3
GND
Y
7
V
CC
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
0
A
0
A
1
A
2
E
1
E
2
E
3
Y
7
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
File Number
4460
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
2
Die Characteristics
DIE DIMENSIONS:
Size: 2390
µ
m x 2390
µ
m (94 mils x 94 mils)
Thickness: 525
µ
m
±
25
µ
m (20.6 mils
±
1 mil)
Bond Pad: 110
µ
m x 110
µ
m (4.3 x 4.3 mils)
METALLIZATION: Al
Metal 1 Thickness: 0.7
µ
m
±
0.1
µ
m
Metal 2 Thickness: 1.0
µ
m
±
0.1
µ
m
SUBSTRATE POTENTIAL:
Unbiased Insulator
PASSIVATION
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30
µ
m
±
0.15
µ
m
SPECIAL INSTRUCTIONS:
Bond V
CC
First
ADDITIONAL INFORMATION:
Worst Case Density: <2.0 x 10
5
A/cm
2
Transistor Count: 256
Metallization Mask Layout
ACTS138MS
A
1
A
0
V
CC
Y
0
A
2
E
1
E
2
E
3
Y
1
Y
2
Y
3
Y
4
Y
7
GND
Y
6
Y
5
ACTS138MS
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