Cascades processor Electrical, Mechanical, and Thermal Specification (EMTS)
PENTIUM® III XEONTM PROCESSOR AT 700 MHz
and 900 MHz.
Datasheet
Product Features
Binary compatible with applications
running on previous members of
the Intel microprocessor family
Optimized for 32-bit applications
running on advanced 32-bit
operating systems
Dynamic Independent Bus
architecture: separate dedicated
external 100 MHz System Bus and
dedicated internal cache bus
operating at full processor core
speed
Power Management capabilities
System Management mode
Multiple low-power states
Single Edge Contact (S.E.C.)
cartridge packaging technology; the
S.E.C. cartridge delivers high
performance processing and bus
technology to mid range to high end
servers and workstations
100 MHz system bus speeds data
transfer between the processor and
the system
Integrated high performance16k
instruction and 16k data, non-
blocking, level-one cache
Available in 1MB (700 MHz) or 2MB
(900 MHz and 700 MHz) unified,
non-blocking level-two cache
Enables systems which are
scaleable up to two processors and
64GB of physical memory
SMBus interface to advanced
manageability features
Streaming SIMD Extensions for
enhanced video, sound and 3D
performance
The Intel® Pentium® III XeonTM Processor at 700 MHz with 1MB or 2MB L2 cache and 900 MHz with 2MB L2
cache is designed for mid-range to high-end servers and workstations, and is binary compatible with previous
Intel® Architecture processors. The Pentium® III XeonTM processor at 700 MHz and 900 MHz provides the
best performance available for applications running on advanced operating systems such as Microsoft*
Windows* 98, Microsoft* Windows* NT*, and UNIX*. The processor is scalable to four processors in a
multiprocessor system and extends the power of the Pentium® Pro processor with new features designed to
make this processor the right choice for powerful workstation, advanced server management, and mission-
critical applications. Pentium® III XeonTM processor at 700 MHz and 900 MHz-based workstations offer the
memory architecture required by the most demanding workstation applications and workloads. Specific
features of the processor address platform manageability to meet the needs of a robust IT environment,
maximize system up time and ensure optimal configuration and operation of servers. The Pentium® III
XeonTM processor at 700 MHz and 900 MHz enhances the ability of server platforms to monitor, protect, and
service the processor and its environment.
Order Number: 248711-002
March 2001
ii
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and
product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features
or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility
whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Pentium® III XeonTM processor may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product
order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
*Other names and brands may be claimed as the property of others..
Copyright © 2001, Intel Corporation
TABLE OF CONTENTS
2
TABLE OF CONTENTS
P
RODUCT
F
EATURES
............................................................................................................
I
1. INTRODUCTION ......................................................................................................................... 6
2. TERMINOLOGY .......................................................................................................................... 7
2.1 S.E.C. CARTRIDGE TERMINOLOGY.................................................................................... 7
2.2
S
TATE OF
D
ATA
................................................................................................................ 8
2.3
R
EFERENCES
.................................................................................................................... 8
3. ELECTRICAL SPECIFICATIONS............................................................................................... 9
3.1
S
YSTEM
B
US AND
VREF................................................................................................... 9
3.2
P
OWER AND
G
ROUND
P
INS
............................................................................................... 9
3.3
D
ECOUPLING
G
UIDELINES
............................................................................................... 11
3.3.1 VCC_CORE ................................................................................................................... 11
3.3.2
LEVEL 2 CACHE DECOUPLING............................................................................. 11
3.3.3
SYSTEM BUS AGTL+ DECOUPLING..................................................................... 11
3.4
C
LOCK
F
REQUENCIES AND
S
YSTEM
B
US
C
LOCK
R
ATIOS
.................................................. 11
3.4.2
MIXING PROCESSORS OF DIFFERENT FREQUENCIES ................................... 13
3.5
V
OLTAGE
I
DENTIFICATION
................................................................................................ 13
3.6
S
YSTEM
B
US
U
NUSED
P
INS AND
T
EST
P
INS
..................................................................... 16
3.7
S
YSTEM
B
US
S
IGNAL
G
ROUPS
........................................................................................ 16
3.7.2
ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS ............ 17
3.8
A
CCESS
P
ORT
(TAP) C
ONNECTION
................................................................................. 17
3.9
M
AXIMUM
R
ATINGS
......................................................................................................... 18
3.10
P
ROCESSOR
DC S
PECIFICATIONS
................................................................................... 18
3.11
AGTL+ S
YSTEM
B
US
S
PECIFICATIONS
............................................................................ 22
3.12
S
YSTEM
B
US
AC S
PECIFICATIONS
................................................................................... 24
4. SIGNAL QUALITY..................................................................................................................... 33
4.1 B
US
C
LOCK
S
IGNAL
Q
UALITY
S
PECIFICATIONS
......................................................................... 33
4.2
AGTL+ S
IGNAL
Q
UALITY
S
PECIFICATIONS
....................................................................... 34
4.2.2 AGTL+ Signal Quality Specifications .............................................................................. 34
4.2.3
AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES ............................................ 34
4.3 N
ON
-GTL+ S
IGNAL
Q
UALITY
S
PECIFICATIONS
.......................................................................... 37
4.3.1 2.5V Signal Overshoot/Undershoot Guidelines ............................................................. 38
4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications ........................................ 39
4.3.3 Measuring BCLK Overshoot/Undershoot........................................................................ 39
4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION ............................................ 40
4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE............................................ 40
5. PROCESSOR FEATURES........................................................................................................ 41
5.1 L
OW
P
OWER
S
TATES AND
C
LOCK
C
ONTROL
............................................................................. 41
5.1.1
NORMAL STATE -- STATE 1 ................................................................................. 41
5.1.2
AUTO HALT POWER DOWN STATE -- STATE 2 ................................................. 41
TABLE OF CONTENTS
3
5.1.3
STOP-GRANT STATE -- STATE 3......................................................................... 42
5.1.4
HALT/GRANT SNOOP STATE -- STATE 4 ........................................................... 42
5.1.5
SLEEP STATE -- STATE 5..................................................................................... 43
5.1.6
CLOCK CONTROL .................................................................................................. 43
5.2
S
YSTEM
M
ANAGEMENT
B
US
(SMB
US
) I
NTERFACE
........................................................... 43
5.2.1
PROCESSOR INFORMATION ROM....................................................................... 44
5.2.2
SCRATCH EEPROM ............................................................................................... 48
5.2.3
PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED
SMBUS TRANSACTIONS ....................................................................................................... 48
5.2.4
THERMAL SENSOR ................................................................................................ 49
5.2.5
THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS ............................. 50
5.2.6
THERMAL SENSOR REGISTERS .......................................................................... 51
5.2.7
SMBus Device Addressing....................................................................................... 53
6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS......................................... 55
6.1
T
HERMAL
S
PECIFICATIONS
.............................................................................................. 55
6.1.1
POWER DISSIPATION............................................................................................ 55
6.1.2
PLATE FLATNESS SPECIFICATION...................................................................... 57
6.2
P
ROCESSOR
T
HERMAL
A
NALYSIS
.................................................................................... 57
6.2.1
THERMAL SOLUTION PERFORMANCE ............................................................... 57
6.2.2
THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE............. 58
6.2.3
MEASUREMENTS FOR THERMAL SPECIFICATIONS......................................... 58
7. MECHANICAL SPECIFICATIONS ........................................................................................... 60
7.1 W
EIGHT
.................................................................................................................................. 64
7.2 C
ARTRIDGE TO
C
ONNECTOR
M
ATING
D
ETAILS
.......................................................................... 64
7.3 S
UBSTRATE
E
DGE
F
INGER
S
IGNAL
L
ISTING
............................................................................. 66
8. INTEGRATION TOOLS............................................................................................................. 76
8.1 I
N
-T
ARGET
P
ROBE
(ITP).......................................................................................................... 76
8.1.1 PRIMARY FUNCTION .................................................................................................... 76
8.1.2 DEBUG PORT CONNECTOR DESCRIPTION .............................................................. 76
8.1.3 KEEP OUT CONCERNS ................................................................................................ 77
8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS................................ 77
8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS ...................................................................... 77
8.1.6 DEBUG PORT SIGNAL NOTES..................................................................................... 80
8.1.7 Using the TAP to Communicate to the processor........................................................... 82
8.2 L
OGIC
A
NALYZER
I
NTERCONNECT
(LAI)
AND
T
RACE
C
APTURE
T
OOL
C
ONSIDERATIONS
.............. 82
8.2.1 LAI and Trace Capture Tool System Design Considerations ......................................... 82
8.2.2 LAI and Trace Capture tool Mechanical Keep Outs ....................................................... 82
9. BOXED PROCESSOR SPECIFICATIONS............................................................................... 83
9.1 I
NTRODUCTION
........................................................................................................................ 83
9.2 M
ECHANICAL
S
PECIFICATIONS
................................................................................................. 83
9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS ........................................................ 85
9.2.2 BOXED PROCESSOR HEATSINK WEIGHT ................................................................. 85
9.2.3 BOXED PROCESSOR RETENTION MECHANISM ...................................................... 85
9.3 T
HERMAL
S
PECIFICATIONS
....................................................................................................... 86
9.3.1 Boxed Processor Cooling Requirements ........................................................................ 86
9.3.2 Boxed Processor Passive Heatsink Performance .......................................................... 86
9.3.2 Optional auxiliary fan attachment.................................................................................... 87
10. APPENDIX............................................................................................................................... 90
TABLE OF CONTENTS
4
10.1 A
LPHABETICAL
S
IGNALS
R
EFERENCE
..................................................................................... 90
10.1.1 A[35:03]# (I/O)............................................................................................................... 90
10.1.2 A20M# (I) ...................................................................................................................... 90
10.1.3 ADS# (I/O)..................................................................................................................... 90
10.1.4 AERR# (I/O) .................................................................................................................. 90
10.1.5 AP[1:0]# (I/O) ................................................................................................................ 90
10.1.6 BCLK (I)......................................................................................................................... 90
10.1.7 BERR# (I/O) .................................................................................................................. 91
10.1.8 BINIT# (I/O) ................................................................................................................... 91
10.1.9 BNR# (I/O) .................................................................................................................... 91
10.1.10 BP[3:2]# (I/O) .............................................................................................................. 91
10.1.11 BPM[1:0]# (I/O) ........................................................................................................... 91
10.1.12 BPRI# (I) ..................................................................................................................... 91
10.1.13 BR0# (I/O), BR[3:1]# (I)............................................................................................... 91
10.1.15 CORE_AN_SENSE (O) .............................................................................................. 92
10.1.16 D[63:00]# (I/O) ............................................................................................................ 92
10.1.17 DBSY# (I/O) ................................................................................................................ 93
10.1.18 DEFER# (I).................................................................................................................. 93
10.1.19 DEP[7:0]# (I/O)............................................................................................................ 93
10.1.20 DRDY# (I/O)................................................................................................................ 93
10.1.21 FERR# (O) .................................................................................................................. 93
10.1.22 FLUSH# (I) .................................................................................................................. 93
10.1.23 HIT# (I/O), HITM# (I/O) ............................................................................................... 93
10.1.24 HV_EN# (O) ................................................................................................................ 93
10.1.25 IERR# (O) ................................................................................................................... 93
10.1.26 IGNNE# (I) .................................................................................................................. 94
10.1.27 INIT# (I) ....................................................................................................................... 94
10.1.28 INTR - see LINT[0] ...................................................................................................... 94
10.1.29 LINT[1:0] (I) ................................................................................................................. 94
10.1.30 LOCK# (I/O) ................................................................................................................ 94
10.1.31 L2_SENSE ................................................................................................................. 95
10.1.32 OCVR_EN (I) .............................................................................................................. 95
10.1.33 OCVR_OK(O) ............................................................................................................. 95
10.1.34 NMI - See LINT[1] ....................................................................................................... 95
10.1.35 PICCLK (I) ................................................................................................................... 95
10.1.36 PICD[1:0] (I/O) ............................................................................................................ 95
10.1.37 PRDY# (O) .................................................................................................................. 95
10.1.38 PREQ# (I).................................................................................................................... 95
10.1.39 PWREN[1:0] (I) ........................................................................................................... 95
10.1.40 PWRGOOD (I) ............................................................................................................ 95
10.1.41 REQ[4:0]# (I/O) ........................................................................................................... 97
10.1.42 RESET# (I).................................................................................................................. 98
10.1.43 RP# (I/O) ..................................................................................................................... 98
10.1.44 RS[2:0]# (I).................................................................................................................. 98
10.1.45 RSP# (I) ...................................................................................................................... 98
10.1.46 SA[2:0] (I) .................................................................................................................... 98
10.1.47 SELFSB0 (I) SELFSB1 (O)......................................................................................... 99
10.1.48 SLP# (I) ..................................................................................................................... 100
10.1.49 SMBALERT# (O)....................................................................................................... 100
10.1.50 SMBCLK (I) ............................................................................................................... 100
10.1.51 SMBDAT (I/O) ........................................................................................................... 101
10.1.52 SMI# (I) ..................................................................................................................... 101
10.1.53 STPCLK# (I).............................................................................................................. 101
10.1.54 TCK (I)....................................................................................................................... 101
Document Outline
PDF 
ZIP