Order Number: 245052-001

82443MX PCIset

Processor Host Bus Support

Optimized for the Intel®
Pentium® II and mobile
CeleronTM processors at 66 MHz

GTL+ Bus Driver Technology

Integrated DRAM Support

8 MB to 256 MB using 16-/64-
/128-Mb Technology

Standard and Registered
SDRAM (Synchronous) DRAM
Support (x-1-1-1 access at 66
MHz)

Enhanced Open Page
Arbitration SDRAM Paging
Scheme

PCI Bus Interface

PCI Rev. 2.2, 3.3V, 33 MHz
Interface Compliant

Integrated IDE Controller

-- 1 Channel Support for "Ultra

DMA/33" Synchronous DMA
Mode

System Peripheral Support

Enhanced DMA Controller
Support for Dual Cascaded
82C37 Controllers

Interrupt Controller based on
two 82C59 for up to 15
Interrupts

System Timer based on 82C54

Real Time Clock w/ 256 Bytes
Battery-backed RAM

X-bus Support for SIO, KBCX
and Flash

USB

AC'97 Link Controller

AC'97 Audio and Modem CODEC
Interface Support

USB 1.1 Port for Serial Transfers
at 12 or 1.5 Mbits/sec

Supports UHCI Design Guide

SMBus Support

Power Management Logic

Support for Power-on Suspend,
Suspend-to-SDRAM, and
Suspend-to-Disk

Support for Thermal Alarm

Full Support for ACPI Revision
1.0 Specification

31 GPIO Pins

1.65 W TDP

492 uBGA Package

The Intel® 82443MX PCIset integrates the traditional "North Bridge" and "South Bridge" into one device
reducing power and board space for Intel® Pentium® II and mobile CeleronTM processor-based designs.

The Intel 82443MX PCIset may contain design defects or errors know as errata which may cause the product
to deviate from published specifications. Current characterized errata are available upon request.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in
Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or
implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving or life sustaining applications.

Intel retains the right to make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them. Contact your local sales office or your distributor to obtain the latest specifications before placing your
product order.

Mobile CeleronTM (Micro-PGA and BGA) processors may contain design defects or errors known as errata, which may cause
the product to deviate from published specifications. Current characterized errata are available upon request.

Copies of documents that have an ordering number and are referenced in this document, or other Intel literature, may be
obtained by calling 1-800-548-4725 or by visiting Intel's web site at

http://www.intel.com

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of

the I

C bus/protocol and was developed by Intel. Implementations of the I

C bus/protocol or the SMBus bus/protocol may

require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

* Third party brands and names are the property of their respective owners.

82443MX PCIset

iii

CONTENTS

PAGE

INTRODUCTION ...................................................................................................................................... 1

1.1

82440MX Chipset Feature Summary .............................................................................................. 1

1.2

82440MX Chipset Features ............................................................................................................ 2

ARCHITECTURE OVERVIEW ................................................................................................................. 5

REFERENCES ......................................................................................................................................... 6

SIGNAL DESCRIPTION AND PIN STATES ............................................................................................. 7

4.1

Pin List ........................................................................................................................................... 7

4.1.1

Signal Description ............................................................................................................. 8

4.1.2

Power and Ground Pins .................................................................................................. 22

4.2

GPIO Definition............................................................................................................................. 23

4.3

Power Rail Overview .................................................................................................................... 26

4.4

Power-Up State Initial Value ......................................................................................................... 27

4.5

Power-On Reset Pin Values ......................................................................................................... 27

4.6

Power-Up/Reset Strap Options..................................................................................................... 35

4.7

CPU Reset ................................................................................................................................... 37

POWER PLANES................................................................................................................................... 38

5.1

Overview ...................................................................................................................................... 38

5.2

RTC Power Plane ......................................................................................................................... 38

5.3

Resume Power Plane ................................................................................................................... 38

SYSTEM ADDRESS MAP...................................................................................................................... 40

6.1

Addressable Memory Support ...................................................................................................... 40

6.2

Memory Map................................................................................................................................. 40

6.2.1

Compatibility Area........................................................................................................... 42

6.2.1.1

DOS Area (00000h-9FFFh; 0 - 640 KB) .................................................... 43

6.2.1.2

Video Buffer Area (A0000h-BFFFFh; 640 - 768 KB).................................. 43

6.2.1.3

Expansion Area (C0000h-DFFFFh; 768 - 896 KB) .................................... 43

6.2.1.4

Extended System BIOS Area (E0000h-EFFFFh; 896 - 960 KB)................ 43

6.2.1.5

System BIOS Area (F0000h-FFFFFh; 960 KB - 1 MB).............................. 43

6.2.2

Extended Memory Area .................................................................................................. 43

6.2.2.1

Main DRAM Address Range (0010_0000h to Top of Main Memory) ......... 44

6.2.2.2

Extended SMRAM Address Range (Top of Main Memory - TSEG_SZ to
Top of Main Memory) ................................................................................ 44

82443MX PCIset

6.2.2.3

PCI Memory Address Range (Top of Main Memory to 4 GB) .................... 44

6.2.2.4

High BIOS Area (FFC0_0000h - FFFF_FFFFh) ........................................ 44

6.3

System Management Mode (SMM) Memory Range ..................................................................... 44

6.4

Memory Shadowing ...................................................................................................................... 45

6.5

Decode Rules and Cross-Bridge Address Mapping ...................................................................... 45

6.5.1

PCI Interface Memory Decode Rules .............................................................................. 45

6.5.2

Legacy VGA Range ........................................................................................................ 45

6.6

I/O Address Space ....................................................................................................................... 45

6.6.1

Fixed I/O Address Ranges .............................................................................................. 46

6.6.2

Variable I/O Decode Ranges .......................................................................................... 50

FUNCTIONAL DESCRIPTION ............................................................................................................... 53

7.1

Mobile CeleronTM Processor / Pentium® II Processor Host Interface............................................ 53

7.1.1

Overview......................................................................................................................... 53

7.1.2

Host Bus Device Support ................................................................................................ 53

7.1.3

Special cycles ................................................................................................................. 55

7.1.4

Symmetric Multiprocessor (SMP) Configuration.............................................................. 56

7.1.5

In-Order Queue Pipelining .............................................................................................. 56

7.1.6

Frame Buffer Memory Support (USWC).......................................................................... 56

7.1.7

CPU Sideband Interface ................................................................................................. 57

7.1.7.1

A20M# ...................................................................................................... 57

7.1.7.2

FERR# / IGNNE# (Coprocessor Error) ...................................................... 57

7.1.7.3

INIT# ......................................................................................................... 58

7.1.7.4

Interrupt Signals ........................................................................................ 58

7.1.7.5

NMI ........................................................................................................... 58

7.1.7.6

SMI# ......................................................................................................... 58

7.1.7.7

STPCLK# .................................................................................................. 58

7.2

Memory Interface.......................................................................................................................... 59

7.2.1

DRAM Interface .............................................................................................................. 59

7.2.1.1

DRAM Interface Overview......................................................................... 59

7.2.2

DRAM Organization and Configuration ........................................................................... 59

7.2.2.1

Configuration Mechanism for DIMMs ........................................................ 61

7.2.3

SDRAM Cycle Encoding ................................................................................................. 63

7.2.4

DRAM Address Translation and Decoding ...................................................................... 68

7.2.5

SDRAMC Register Programming.................................................................................... 69

7.2.6

SDRAM Paging Policy .................................................................................................... 70

7.2.6.1

Overview ................................................................................................... 70

7.2.6.2

Open Page Arbitration Policies.................................................................. 70

82443MX PCIset

7.2.6.3

Selective Auto Precharge Policy ............................................................... 70

7.2.7

DRAM Power Throttling .................................................................................................. 71

7.2.7.1

Overview ................................................................................................... 71

7.2.7.2

Conceptual Description of Power Throttling............................................... 71

7.2.7.3

SDRAM Power Throttling Setting Sequence ............................................. 72

7.2.8

SDRAM Performance Description................................................................................... 73

7.2.9

SDRAM Optimizations .................................................................................................... 73

7.2.9.1

Dual and Quad Bank Support.................................................................... 73

7.3

System Memory Management ...................................................................................................... 73

7.3.1

SMRAM range overview ................................................................................................. 73

7.3.2

Compatible SMRAM (C_SMRAM) .................................................................................. 74

7.3.3

Extended SMRAM (E_SMRAM) ..................................................................................... 74

7.4

AC'97 Audio and Modem Controller.............................................................................................. 77

7.4.1

AC'97 Audio Controller....................................................................................................77

7.4.2

AC'97 Modem Controller................................................................................................ 78

7.4.3

AC'97 Overview .............................................................................................................. 78

7.4.4

System Initialization ........................................................................................................ 80

7.4.5

Clocking.......................................................................................................................... 80

7.4.6

Digital Interface............................................................................................................... 80

7.4.6.1

Multi-Point ACLink..................................................................................... 80

7.4.6.2

AC-link Digital Serial Interface Protocol..................................................... 81

7.5

PCI Interface ................................................................................................................................ 82

7.5.1

PCI Interface Overview ................................................................................................... 82

7.5.2

North Bridge/Cluster Functionality................................................................................... 83

7.5.2.1

North Bridge/Cluster as a PCI Target ........................................................ 83

7.5.2.2

North Bridge/Cluster as a PCI Initiator....................................................... 84

7.5.2.3

Delayed Transactions ............................................................................... 86

7.5.3

South Bridge/Cluster Functionality .................................................................................. 87

7.5.3.1

South Bridge/Cluster as a PCI Target ....................................................... 87

7.5.3.2

South Bridge/Cluster as a PCI Initiator ...................................................... 88

7.6

DMA Controller ............................................................................................................................. 89

7.6.1

Register Description........................................................................................................ 89

7.6.2

Functional Description ....................................................................................................89

7.6.2.1

DMA Transfer Modes ................................................................................ 90

7.6.2.2

DMA Transfer Types ................................................................................. 91

7.6.2.3

DMA Timings ............................................................................................ 92

7.6.2.4

X-bus / DMA Arbitration ............................................................................ 92

7.6.2.5

Part Number 82443MX