Key Features
x
Ultra-Fast response for Fast-20 SCSI applications
x
35MHz channel bandwidth
x
3.3V operation
x
Less than 3pF output capacitance
x
Sleep-mode current less than 275µA
x
Thermally self limiting
x
No external compensation capacitors
x
Implements 8-bit or 16-bit (wide) applications
x
Compatible with active negation drivers
(60mA/channel)
x
Compatible with passive and active terminations
x
Approved for use with SCSI 1, 2, 3 and UltraSCSI
x
Hot swap compatible
x
Pin-for-pin compatible with LX5211 and
UC5606 (IMP5111)
x
Pin-for-pin compatible with LX5212 and
UC5603/5613/5614 (IMP5112)
Block Diagrams
+
Current
Biasing
Circuit
Thermal
Limiting
Circuit
24mA Current
Limiting Circuit
Term Power
DATA OUTPUT
PIN DB (0)
1 of 9 Channels
DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
1.4V
2.85V
5111/5112_01.eps
9-Line SCSI T
9-Line SCSI T
er
er
minat
minat
or
or
35MHz Channel Bandwidt
35MHz Channel Bandwidt
h
h
The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family
of high-performance SCSI terminators that deliver true UltraSCSI per-
formance. The BiCMOS design offers superior performance over first
generation linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each
channel, thereby providing the fastest response possible - typically
35MHz, which is 100 times faster than the older linear regulator termi-
nator approach. The bandwidth of terminators based on the older
regulator/resistor terminator architecture is limited to 500kHz since a
large output stabilization capacitor is required. The IMP architecture
eliminates the external output compensation capacitor and the need
for transient output capacitors while maintaining pin compatibility
with first generation designs. Reduced component count is inherent
with the IMP5111/5112.
The IMP5111/5112 architecture tolerates marginal system designs. A key
improvement offered by the IMP5111/5112 lies in its ability to insure
reliable, error-free communications even in systems which do not adhere
to recommended SCSI hardware design guidelines, such as improper
cable lengths and impedance. Frequently, this situation is not controlled
by the peripheral or host designer.
For portable and configurable peripherals, the IMP5111/5112 can be
placed in a sleep mode with a disconnect signal. Quiescent current is less
than 275
µ
A when disabled. When disabled, the outputs are in a high
impedance state with output capacitance less than 3pF.
© 2002 IMP, Inc. 408-432-9100/www.impweb.com
1
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
D
ATA
C
OMMUNICATIONS
© 2002 IMP, Inc. 408-432-9100/www.impweb.com
1
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
D
ATA
C
OMMUNICATIONS
2
408-432-9100/www.impweb.com © 2002 IMP, Inc.
Pin Configuration
Ordering Information
Absolute Maximum Ratings
1
8
T2
1
T7
DW Package
9
T3
7
T1
10 T4
6
DISCONNECT*
11 V
TERM
5
GND
12 HEAT SINK/GND
4
HEAT SINK/GND
13 HEAT SINK/GND
3
T9
14 NC
2
T8
15 T5
16 T6
5111/5112__02.eps
IMP5111
IMP5112
* DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
SO-16
* DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
12
T2
1
T7
PW Package
13 T3
7
HEAT SINK/GND
18 HEAT SINK/GND
8
HEAT SINK/GND
17 HEAT SINK/GND
9
HEAT SINK/GND
16 NC
10
DISCONNECT*
15 V
TERM
11
T1
14 T4
6
HEAT SINK/GND
19 HEAT SINK/GND
5
GND
20 HEAT SINK/GND
4
NC
21 NC
3
T9
22 NC
2
T8
23 T5
24 T6
5111/5112_02a.eps
IMP5111
IMP5112
TSSOP-24
r
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b
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u
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n
a
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c
a
P
P
D
C
1
1
1
5
P
M
I
0°
5
2
1
o
t
C
°C
O
S
c
i
t
s
a
l
P
n
i
p
-
6
1
T
P
D
C
1
1
1
5
P
M
I
0°
5
2
1
o
t
C
°C
O
S
c
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p
-
6
1
,
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P
C
1
1
1
5
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M
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0°
5
2
1
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t
C
°C
P
O
S
S
T
c
i
t
s
a
l
P
n
i
p
-
4
2
T
P
W
P
C
1
1
1
5
P
M
I
0°
5
2
1
o
t
C
°C
P
O
S
S
T
c
i
t
s
a
l
P
n
i
p
-
4
2
,
l
e
e
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d
n
a
e
p
a
T
P
D
C
2
1
1
5
P
M
I
0°
5
2
1
o
t
C
°C
O
S
c
i
t
s
a
l
P
n
i
p
-
6
1
T
P
D
C
2
1
1
5
P
M
I
0°
5
2
1
o
t
C
°C
O
S
c
i
t
s
a
l
P
n
i
p
-
6
1
,
l
e
e
R
d
n
a
e
p
a
T
P
W
P
C
2
1
1
5
P
M
I
0°
5
2
1
o
t
C
°C
P
O
S
S
T
c
i
t
s
a
l
P
n
i
p
-
4
2
T
P
W
P
C
2
1
1
5
P
M
I
0°
5
2
1
o
t
C
°C
P
O
S
S
T
c
i
t
s
a
l
P
n
i
p
-
4
2
,
l
e
e
R
d
n
a
e
p
a
T
3
t
a
.
1
0
t
_
2
1
1
5
/
1
1
1
5
Thermal Data
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0V to +7V
Regulator Output Current . . . . . . . . . . . . . . . . . . 0.4A
Operating Junction Temperature
Plastic (DP, PWP Packages) . . . . . . . . . . . . . . . 150
°
C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
°
C to 150
°
C
Lead Temperature (Soldering, 10 seconds) . . . . . 300
°
C
DP Package:
Thermal Resistance Junction-to-Leads,
JL
. . . . . . . . 20
°
C/W
Thermal Resistance Junction-to-Ambient,
JA
. . . . . . 50
°
C/W
PW Package:
Thermal Resistance Junction-to-Leads,
JL
. . . . . . . . 27
°
C/W
Thermal Resistance Junction-to-Ambient,
JA
. . . . . . 100
°
C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
JA
).
The
JA
numbers are guidelines for the thermal performance of the
device/pc-board system. All of the ambient airflow is assumed.
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
© 2002 IMP, Inc.
Data Communications 3
Recommended Operating Conditions
2
r
e
t
e
m
a
r
a
P
l
o
b
m
y
S
n
i
M
p
y
T
x
a
M
s
t
i
n
U
e
g
a
t
l
o
V
r
w
P
m
r
e
T
V
M
R
E
T
3
.
3
5
.
5
V
e
g
a
t
l
o
V
t
u
p
n
I
e
l
b
a
n
E
l
e
v
e
L
h
g
i
H
1
1
1
5
P
M
I
V
H
I
2
V
M
R
E
T
V
2
1
1
5
P
M
I
0
8
.
0
e
g
a
t
l
o
V
t
u
p
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D
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w
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L
1
1
1
5
P
M
I
V
L
I
0
8
.
0
V
2
1
1
5
P
M
I
2
V
M
R
E
T
e
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n
a
R
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u
t
a
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e
p
m
e
T
n
o
i
t
c
n
u
J
g
n
i
t
a
r
e
p
O
0
5
2
1
C
°
.
l
a
n
o
i
t
c
n
u
f
s
i
e
c
i
v
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d
e
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t
h
c
i
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w
r
e
v
o
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g
n
a
r
e
h
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t
a
c
i
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n
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a
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p
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d
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m
m
o
c
e
R
.
2
:
e
t
o
N
s
p
e
.
2
0
t
_
2
1
1
5
/
1
1
1
5
Electrical Characteristics
Unless otherwise specified, these specifications apply at an ambient operating temperature of T
A
=
25
°
C. TermPwr = 4.75V. Low duty cycle
pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature.
r
e
t
e
m
a
r
a
P
l
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b
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S
s
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5
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.
2
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y
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=
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A
6
9
A
m
V
5
.
0
=
s
e
n
il
a
t
a
d
ll
A
5
1
2
5
2
2
1
1
1
5
P
M
I
T
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E
N
N
O
C
S
I
D
V
8
.
0
<
n
i
P
5
7
2
µ
A
2
1
1
5
P
M
I
T
C
E
N
N
O
C
S
I
D
V
0
.
2
>
n
i
P
5
7
2
t
n
e
r
r
u
C
t
u
p
t
u
O
I
T
U
O
V
T
U
O
V
5
.
0
=
1
2
3
2
4
2
A
m
T
C
E
N
N
O
C
S
I
D
t
n
e
r
r
u
C
t
u
p
n
I
1
1
1
5
P
M
I
I
N
I
T
C
E
N
N
O
C
S
I
D
V
5
7
.
4
=
n
i
P
0
1
A
n
T
C
E
N
N
O
C
S
I
D
V
0
=
n
i
P
0
9
µ
A
T
C
E
N
N
O
C
S
I
D
t
n
e
r
r
u
C
t
u
p
n
I
2
1
1
5
P
M
I
I
N
I
T
C
E
N
N
O
C
S
I
D
V
0
=
n
i
P
0
9
µ
A
T
C
E
N
N
O
C
S
I
D
V
5
7
.
4
=
n
i
P
0
1
A
n
t
n
e
r
r
u
C
e
g
a
k
a
e
L
t
u
p
t
u
O
1
1
1
5
P
M
I
I
L
O
T
C
E
N
N
O
C
S
I
D
V
,
V
8
.
0
<
n
i
P
O
V
5
.
0
=
0
1
A
n
2
1
1
5
P
M
I
T
C
E
N
N
O
C
S
I
D
V
,
V
0
.
2
>
n
i
P
O
V
5
.
0
=
0
1
n
i
e
c
n
a
t
i
c
a
p
a
C
T
C
E
N
N
O
C
S
I
D
e
d
o
M
C
T
U
O
V
T
U
O
z
H
M
1
=
y
c
n
e
u
q
e
r
F
,
V
0
=
3
F
p
h
t
d
i
w
d
n
a
B
l
e
n
n
a
h
C
W
B
5
3
z
H
M
l
e
n
n
a
h
C
r
e
p
,
t
n
e
r
r
u
C
k
n
i
S
n
o
i
t
a
n
i
m
r
e
T
I
K
N
I
S
V
T
U
O
V
4
=
0
6
A
m
s
p
e
.
3
0
t
_
2
1
1
5
/
1
1
1
5
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
4
408-432-9100/www.impweb.com © 2002 IMP, Inc.
Application Information
IMP5111/IMP5112 Maximizes Line Current
Cable transmission theory suggests to optimize signal speed and
quality, the termination should act both as an ideal voltage refer-
ence when the line is released (deasserted) and as an ideal
current source when the line is active (asserted). Common active
terminators which consist of linear regulators in series with resis-
tors (typically 110
) are a compromise. With coventional linear
terminators as the line voltage increases the amount of current
decreases linearly by the equation;
The IMP5111/5112, with their unique architecture, applies the
maximum amount of current regardless of line voltage until the
termination high threshold (2.85V) is reached.
Disable /Sleep Mode
The IMP5111 has an active LOW disconnect pin, and the IMP5112
has an active HIGH disconnect pin. The disable mode is entered
if the disconnect pin on either device is left open.
When disabled the termination lines are in a high impedance
state, and the power supply current drops to 275
µ
A typically. The
disable mode can be used to save power or completely eliminate
the terminator from the SCSI bus.
Disabled terminators appear as distributed capacitance on the
bus. The IMP5111/5112 have been optimized to have only 3pF of
capacitance per output when in the disabled mode.
The IMP5111/5112 are compatible with active negation drivers.
The devices will handle up to 60mA of sink current for drivers
which exceed the 2.85V output high level
.
V
V
R
I
REF
LINE
-
(
)
=
.
Figure 3.
5111/5112_03.eps
1 Meter, AWG 28
IMP5111
IMP5112
Receiver
Driver
IMP5111
IMP5112
Figure 1. Receiving Waveform 20MHz
Figure 2. Driving Waveform 20MHz
1
1
1
5
P
M
I
T
C
E
N
N
O
C
S
I
D
2
1
1
5
P
M
I
T
C
E
N
N
O
C
S
I
D
s
t
u
p
t
u
O
t
n
e
r
r
u
C
t
n
e
c
s
e
i
u
Q
H
L
d
e
l
b
a
n
E
A
m
6
L
H
e
c
n
a
d
e
p
m
I
h
g
i
H
/
d
e
l
b
a
s
i
D
5
7
2
µ
A
n
e
p
O
n
e
p
O
e
c
n
a
d
e
p
m
I
h
g
i
H
/
d
e
l
b
a
s
i
D
5
7
2
µ
A
s
p
e
.
a
4
0
t
_
2
1
1
5
/
1
1
1
5
Table 1. Power Up/ Power Down Function Table
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
© 2002 IMP, Inc.
Data Communications 5
s
e
h
c
n
I
s
r
e
t
e
m
i
ll
i
M
n
i
M
x
a
M
n
i
M
x
a
M
*
)
n
i
P
-
6
1
(
O
S
A
3
5
0
.
0
9
6
0
.
0
5
3
.
1
5
7
.
1
1
A
4
0
0
.
0
0
1
0
.
0
0
1
.
0
5
2
.
0
B
4
1
0
.
0
8
1
0
.
0
5
3
.
0
6
4
.
0
C
7
0
0
.
0
0
1
0
.
0
9
1
.
0
5
2
.
0
D
5
8
3
.
0
4
9
3
.
0
8
7
.
9
1
0
.
0
1
E
0
5
1
.
0
8
5
1
.
0
1
8
.
3
1
0
.
4
e
C
S
B
0
5
0
.
0
C
S
B
7
2
.
1
H
8
2
2
.
0
4
4
2
.
0
9
7
.
5
0
2
.
6
L
6
1
0
.
0
0
5
0
.
0
0
4
.
0
7
2
.
1
M
°
0
°
8
°
0
°
8
)
n
i
P
-
4
2
(
P
O
S
S
T
A
2
3
0
.
0
1
4
0
.
0
0
8
.
0
5
0
.
1
B
7
0
0
.
0
2
1
0
.
0
9
1
.
0
0
3
.
0
C
5
3
0
0
.
0
1
7
0
0
.
0
9
0
.
0
0
8
1
.
0
D
3
0
3
.
0
1
1
3
.
0
0
7
.
7
0
9
.
7
E
9
6
1
.
0
6
7
1
.
0
0
3
.
4
8
4
.
4
F
C
S
B
5
2
0
.
0
C
S
B
5
6
.
0
G
2
0
0
.
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16-Pin (SO).eps
SO (16-Pin)
3
2
1
E
P
D
SEATING PLANE B
G
A H
F
E
L
24-Pin (TSSOP).eps
C
M
TSSOP (24-Pin)
Package Dimensions
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
PDF 
ZIP