INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
1
JULY 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2000 Integrated Device Technology, Inc.
DSC-5227/2
FUNCTIONAL BLOCK DIAGRAM
R
D
Q
Q
0
R
D
Q
Q
1
R
D
Q
Q
2
R
D
Q
Q
3
R
D
Q
Q
4
R
D
Q
Q
5
R
D
Q
Q/2
Q
RST
0
1
1
0
/2
VCO
LOOP
FILTER
PHASE
DETECTOR
1
0
FREQ_SEL
REF_SEL
LOCK
FEEDBACK
SYNC
0
SYNC
1
PLL_EN
2xQ
QS5917T
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
DESCRIPTION
The QS5917T Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight
outputs are available: Q
0
-Q
4
, 2xQ, Q/2, Q
5
. Careful layout and design
insures < 500ps skew between the Q
0
-Q
4
, and Q/2 outputs. The QS5917T
includes an internal RC filter which provides excellent jitter characteris-
tics and eliminates the need for external components. In addition, TTL
level outputs reduce clock signal noise. Various combinations of feed-
back and a divide-by-2 in the VCO path allow applications to be custom-
ized for linear VCO operation over a wide range of input SYNC fre-
quencies. The VCO can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5917T is designed for use in
high-performance workstations, multi-board computers, networking hardware,
and mainframe systems. Several can be used in parallel or scattered
throughout a system for guaranteed low skew, system-wide clock distri-
bution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FEATURES:
· 5V operation
· 2xQ output, Q/2 output, Q output
· Outputs tri-state while RST low
· Internal loop filter RC network
· Low noise TTL level outputs
· < 500ps output skew, Q
0
-Q
4
· PLL disable feature for low frequency testing
· Balanced Drive Outputs ± 24mA
· 132MHz maximum frequency (2xQ output)
· Functional equivalent to Motorola MC88915
· ESD > 2000V
· Latch-up > 300mA
· Available in QSOP and PLCC packages
INDUSTRIAL TEMPERATURE RANGE
2
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, V
IN
= 0V)
Symbol
Rating
Max
Unit
Supply Voltage to Ground
0.5 to +7
V
DC Input Voltage V
IN
0.5 to +7
V
AC Input Voltage (pulse width
20ns)
3
V
Maximum Power Dissipation (T
A
= 85°C)
1.2
W
T
STG
Storage Temperature Range
65 to +150
°C
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
20
19
18
15
16
23
22
24
21
17
V
DD
GND
PLL_EN
GND
Q/2
Q
3
LOCK
V
DD
2xQ
Q
1
25
28
27
26
V
DD
Q
2
GND
Q
4
2
3
1
9
10
AV
DD
NC
RST
SYNC
0
FEEDBACK
AGND
5
6
7
4
8
Q
5
11
12
FREQ_SEL
SYNC
1
GND
V
DD
REF_SEL
13
14
Q
0
GND
QSOP
TOP VIEW
PLCC
TOP VIEW
R
S
T
V
D
D
Q
5
G
N
D
Q
4
V
D
D
2
x
Q
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
P
L
L
_
E
N
G
N
D
Q
1
V
D
D
Q
0
G
N
D
F
R
E
Q
_
S
E
L
FEEDBACK
REF_SEL
SYNC
0
AV
DD
NC
AGND
SYNC
1
28
4
3
2
1
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
QSOP
PLCC
Parameter
Typ.
Max.
Typ.
Max.
Unit
C
IN
3
4
4
6
pF
C
OUT
7
9
8
10
pF
INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
3
Pin Names
I/O
Description
SYNC
0
I
Reference clock input
SYNC
1
I
Reference clock input
REF_SEL
I
Reference clock select. When 1, selects SYNC
1
. When 0, selects SYNC
0
.
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
FEEDBACK
I
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Q
0
-Q
4
O
Clock outputs
Q
5
O
Clock output. Matched in frequency, but inverted with respect to Q.
2xQ
O
Clock output. Matched in phase, but frequency is double the Q frequency.
Q/2
O
Clock output. Matched in phase, but frequency is half the Q frequency.
LOCK
O
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs.
RST
I
Asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled (normal
operation).
PLL_EN
I
PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes).
N C
--
No Connection
PIN DESCRIPTION
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= 40°C to +85°C, AV
DD
/
V
DD
= 5V ± 5%
Symbol
Description
70
100
132
Units
F
2XQ
Max Frequency, 2xQ output
70
100
132
MHz
F
Q
Max Frequency, Q
0
- Q
4
, Q
5
outputs
35
50
66
MHz
F
Q/2
Max Frequency, Q/2
output
17.5
25
33
MHz
INDUSTRIAL TEMPERATURE RANGE
4
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
SYNC (MHz)
Output Used for
(allowable range)
Output Frequency Relationships
FREQ_SEL
Feedback
Min.
Max
Q/
2
Q
5
Q Outputs
2XQ
1
Q/2
14
F
2XQ
/ 4
SYNC
SYNC X 2
SYNC X 2
SYNC X 4
1
Q
0
-Q
4
28
F
2XQ
/ 2
SYNC / 2
SYNC
SYNC
SYNC X 2
1
Q
5
28
F
2XQ
/ 2
SYNC / 2
SYNC
SYNC
SYNC X 2
1
2xQ
56
F
2XQ (1)
SYNC / 4
SYNC / 2
SYNC / 2
SYNC
0
Q/2
7
F
2XQ
/ 8
SYNC
SYNC X 2
SYNC X 2
SYNC X 4
0
Q
0
-Q
4
14
F
2XQ
/ 4
SYNC / 2
SYNC
SYNC
SYNC X 2
0
Q
5
14
F
2XQ
/ 4
SYNC / 2
SYNC
SYNC
SYNC X 2
0
2xQ
28
F
2XQ
/ 2
SYNC / 4
SYNC / 2
SYNC / 2
SYNC
NOTE:
1. For the 132 speed grade, maximum input frequency is restricted to 100MHz.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage Level
Guaranteed Logic HIGH level
2
--
--
V
V
IL
Input LOW Voltage Level
Guaranteed Logic LOW level
--
--
0.9
V
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
=
-24mA
(1)
2.4
--
--
V
V
DD
= Min., I
OH
=
-100µA
3
--
--
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 24mA
(1)
--
--
0.55
V
V
DD
= Min., I
OL
= 100
µA
--
--
0.2
I
OZ
Output Leakage Current
V
OUT
= V
DD
or GND, V
DD
= Max.
--
--
±5
µA
I
IN
Input Leakage Current
V
IN
= AV
DD
or GND, AV
DD
= Max.
--
--
±5
µA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40°C to +85°C, A
VDD
/V
DD
= 5V ± 5%
NOTE:
1. I
OL
and I
OH
are 12mA and 12mA, respectively, for the LOCK output.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
Max.
Unit
I
CC
Input Power Supply Current per TTL Input HIGH
(2)
V
DD
= Max., V
IN
= 3.4V
0.4
1.5
mA
I
CCD
Dynamic Power Supply Current
V
DD
= Max
--
0.4
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. This specification does not apply to the PLL_EN input.
INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
5
INPUT TIMING REQUIREMENTS
Symbol
Description
Min.
Max.
Unit
t
R
, t
F
Maximum input rise and fall times, 0.8V to 2V
--
3
ns
F
I
Input Clock Frequency, SYNC
0
, SYNC
1 (1)
14
F
2XQ
MHz
t
PWC
Input clock pulse, HIGH or LOW
2
--
ns
D
H
Duty cycle, SYNC
0
, SYNC
1
25
75
%
NOTE:
1. The F
I
specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations.
SWITCHING CHARACTERISTICS
(1)
Symbol
Parameter
Min.
Max.
Unit
t
SKR
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(1)
--
350
ps
t
SKF
Output Skew Between Falling Edges, Q
0
-Q
4
(1)
--
350
ps
t
SKALL
Output Skew, All Outputs
(1)
--
500
ps
t
PW
Pulse Width, Q
5,
2xQ outputs
T
CY
/2
- 0.65
T
CY
/2 + 0.65
ns
t
PW
Pulse Width, Q
0
-Q
4
, Q/2
outputs
(1)
T
CY
/2
- 0.5
T
CY
/2 + 0.5
ns
t
J
Cycle-to-Cycle Jitter, 33MHz
(3)
--
0.25
ns
t
PD
SYNC Input to Feedback Delay, 28MHz
- 100
400
ps
t
PD
SYNC Input to Feedback Delay, 33MHz, 50
to 1.5V
- 100
400
ps
t
LOCK
SYNC to Phase Lock
--
10
ms
t
PZH
Output Enable Time, RST LOW to HIGH
(2)
0
7
ns
t
PZL
t
PHZ
Output Disable Time, RST HIGH to LOW
(2)
0
6
ns
t
PLZ
t
R,
t
F
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
ns
NOTES:
1. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
2. Measured in open loop mode PLL_EN = 0.
3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information
on proper FREQ_SEL level for specified input frequencies.
INDUSTRIAL TEMPERATURE RANGE
6
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30pF
7.0V
OUTPUT
300
20pF
V
DD
OUTPUT
160
68
TEST CIRCUIT 1
TEST CIRCUIT 2
TEST CIRCUIT 2 is used for output enable/disable parameters.
TEST CIRCUIT 1 is used for all other timing parameters.
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5917T provides
for replication of incoming SYNC clock signals. Any manipulation of that
signal, such as frequency multiplying or inversion is performed by digital
logic following the PLL (see the block diagram). The key advantage of the
SIMPLIFIED DIAGRAM OF QS5917T FEEDBACK
The phase difference between the output and the input frequencies feeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilize at the same frequency as the input. Hence, this is a true negative
feedback closed loop system. In most applications, the output will optimally
have zero phase shift with respect to the input. In fact, the internal loop filter
on the QS5917T typically provides within 150ps of phase shift between
input and output.
PLL circuit is to provide an effective zero propagation delay between the
output and input signals. In fact, adding delay circuits in the feedback path,
`propagation delay' can even be negative! A simplified schematic of the
QS5917T PLL circuit is shown below.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
be advanced by the amount of delay in the feedback path. All other outputs
will retain their proper relationships to that output.
Q
Q/
2
Q
VCO
/2
/2
PHASE
DETECTOR
INPUT
2xQ
TEST LOAD
INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
7
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
QS
X
Package
5917T
Low Skew CMOS PLL Clock Driver with Integrated
Loop Filter
XXXX
Device Type
X
Process
Blank
Q
J
Quarter Size Outline Package
Plastic Leaded Chip Carrier
Industrial (-40°C to +85°C)
XX
Speed
-70T
-100T
-132T
70MHz Max. Frequency
100MHz Max. Frequency
132MHz Max. Frequency
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