1
QS532806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2000
1999 Integrated Device Technology, Inc.
DSC-5783/-
c
QS532806/A
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The QS532806 clock driver/buffer circuit can be used for clock buffering
schemes where low skew is a key parameter. The QS532806 offers two
banks of five inverting outputs. Designed in IDT's proprietary CMOS
process, these devices provide low propagation delay buffering with on-
chip skew of 0.7ns for same-transition, same-bank signals.
The QS532806 has on-chip series termination resistors for lower noise
clock signals. The series resistor versions are recommended for driving
unterminated lines with capacitive loading and other noise sensitive clock
distribution circuits. These clock buffer products are designed for use in
high-performance workstations, embedded and personal computing sys-
tems. Several devices can be used in parallel or scattered throughout a
system for guaranteed low skew, system-wide clock distribution networks.
IN
A
IN
B
O E
A
O E
B
O B
5 -
O B
1
O A
5 -
O A
1
M O N
5
5
FEATURES:
-
JEDEC compatible LVTTL level
-
10 low skew clock outputs
-
Monitor output
-
Clock inputs are 5V tolerant
-
Pinout and function compatible with QS5806
-
25
on-chip resistors for low noise
-
Input hysteresis for better noise margin
-
Guaranteed low skew:
·
0.7ns output skew (same bank)
·
0.9ns output skew (different bank)
·
1ns part-to-part skew
-
Std. and A speed grades
-
Available in QSOP and SOIC packages
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INDUSTRIAL TEMPERATURE RANGE
QS532806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
PIN CONFIGURATION
QSOP/ SOIC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
O A
1
O A
2
O A
3
G ND
A
O A
4
O A
5
G NDQ
O E
A
IN
A
O B
1
O B
2
O B
3
G ND
B
O B
4
O B
5
M O N
O E
B
IN
B
V
C CA
V
C CB
SO 20-2
SO 20-8
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
Unit
V
TERM(2)
Supply Voltage to Ground
0.5 to +7
V
DC Output Voltage V
OUT
0.5 to Vcc+0.5
V
V
TERM(3)
DC Input Voltage V
IN
0.5 to +7
V
V
AC
AC Input Voltage (pulse width
20ns)
-3
V
I
OUT
DC Output Current V
IN
< 0
-20
mA
DC Output Current Max. Sink Current/Pin
120
mA
T
STG
Storage Temperature
65 to +150
°C
T
J
Junction Temperature
150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V, V
OUT
= 0V)
QSOP
SOIC
Pins
Typ.
Max.
(1)
Typ.
Max.
(1)
Unit
All Pins
4
6
5
7
pF
NOTE:
1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names
I/O
Description
OEA, OEB
I
Output Enable Inputs
INA, INB
I
Clock Inputs
OAn, OBn
O
Clock Outputs
MON
O
Monitor Outputs (non-disable)
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QS532806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH for Inputs
2
--
5.5
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW for Inputs
0.5
--
0.8
V
V
IC
Clamp Diode Voltage
(3)
Vcc = Min., I
IN
= -18mA
--
0.7
1.2
V
V
OH
Output HIGH Voltage
Vcc = Min., I
OH
= -100
µ
A
Vcc 0.2
--
--
V
Vcc = Min., I
OH
= -8mA
2.4
--
--
V
V
OL
Output LOW Voltage
Vcc = Min., I
OL
= 100
µ
A
--
--
0.2
V
Vcc = Min., I
OL
= 6mA
--
--
0.4
V
Vcc = Min., I
OL
= 8mA
--
--
0.5
V
I
IN
Input Leakage Current
Vcc = Max., V
IN
= Vcc or GND
--
--
±1
µ
A
I
OZ
Output Leakage Current
Vcc = Max., V
OUT
= Vcc or GND
--
--
±1
µ
A
I
OFF
Input Power Off Leakage
Vcc = 0V, V
IN
= Vcc or GND
--
--
±1
µ
A
I
ODH
Output HIGH Current
(2)
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
30
100
200
mA
I
ODL
Output LOW Current
(2)
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
30
100
200
mA
I
OS
Short Circuit Current
(2,3)
Vcc = Max., V
OUT
= GND
60
--
--
mA
R
OUT
Output Resistance
(4)
Vcc = Min
--
28
--
NOTES:
1. Typical values are at V
CC
= 3.3V, T
A
= 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
4. Output resistance represents the total output impedence of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
(3)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or Vcc
0.01
100
µ
A
I
CC
Supply Current per Input HIGH
V
CC
= Max., V
IN
= 3V
0.1
30
µ
A
I
CCD
Dynamic Power Supply Current per Output
(2)
V
CC
= Max.,
OEA = OEB = GND
Outputs Toggling at 50% duty cycle
65
100
µ
A/MHz
I
C
Total Power Supply Current Examples
(2,4)
V
CC
= Max.,
OEA = OEB = GND
V
IN
= GND or Vcc
3.5
5.2
mA
50% duty cycle, f
I
= 10MHz
five outputs
V
IN
= GND or 3V
3.5
5.2
mA
V
CC
= Max.,
OEA = OEB = GND
V
IN
= GND or Vcc
1.8
2.9
mA
50% duty cycle, f
I
= 2.5MHz
All outputs toggling
V
IN
= GND or 3V
1.8
2.9
mA
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. C
L
= 0pF.
3. Typical values are for reference only. Conditions are V
CC
= 3.3V, T
A
= 25°C.
4. I
C
= I
CC
+ (
I
CC
)(D
H
)(N
T
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input Duty Cycle
N
T
= Number of TTL HIGH inputs at D
H
(one or two)
f
O
= Output Frequency
N
O
= Number of outputs at f
O
(five or ten)
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INDUSTRIAL TEMPERATURE RANGE
QS532806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
C
LOAD
= 50pF (no resistor)
QS532806
QS532806A
Symbol
Parameter
(1)
Min.
Max.
Min.
Max.
Unit
t
SK(01)
Skew between all outputs, same transition, same bank
--
0.7
--
0.7
ns
t
SK(02)
Skew between two outputs, same transition, different banks
--
0.9
--
0.9
ns
t
SK(P)
Pulse Skew; skew between opposite transitions of the same output (t
PHL
- t
PLH
)
--
1.4
--
1.4
ns
t
SK(T)
Part-to-part skew
(2)
--
1.5
--
1
ns
NOTES:
1. This parameter is guaranteed but not production tested. Skew parameters apply to propagation delays only.
2. t
SK(T)
only applies to devices of the same transition, part type, temperature, power supply voltage, loading package, and speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
C
LOAD
= 50pF (no resistor)
QS53806
QS532806A
Symbol
Parameter
(1)
Min.
Max.
Min.
Max.
Unit
t
PLH
t
PHL
Propagation Delay
(2)
1.5
6.5
1.5
5.8
ns
t
R
Output Rise Time, 0.8V to 2V
(3)
--
2
--
2
ns
t
F
Output Fall Time, 2V to 0.8V
(3)
--
2
--
2
ns
t
PZL
t
PZH
Output Enable Time
1.5
8
1.5
8
ns
t
PLZ
t
PZH
Output Disable Time
1.5
7
1.5
7
ns
NOTES:
1. Minimums guaranteed but not production tested.
2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delays do not imply limit skew.
3. This parameter is guaranteed but not production tested.
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QS532806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
Pulse
Generator
500
500
V
CC
V
O UT
V
IN
DUT
50
50pF
6.0 V
Parameter
Tested
Switch
Position
All Others
Closed
Open
t
PLZ
, t
PZL
CONTROL
INPUT
ENABLE
DISABLE
3V
1.5V
0V
3V
0V
1.5V
1.5V
OUTPUT
NORM ALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
IN PUT
OUPUT 1
3V
1.5V
0V
1.5V
1.5V
OUPUT 2
INPUT
OUPUT
3V
1.5V
0V
1.5V
2.0V
0.8V
INPUT
PART 1 O UTPUT
3V
1.5V
0V
1.5V
1.5V
PART 2 O UTPUT
INPUT
OUPUT A
t
PLHA
3V
1.5V
0V
1.5V
1.5V
OUPUT B
INPUT
OUPUT
t
PLH
t
PHL
3V
1.5V
0V
V
O H
1.5V
V
OL
t
SK(p)
= t
PHL
- t
PLH
t
SK(02)
= t
PLHB
- t
PLHA
or t
PHLB
- t
PHLA
Pulse generator for all pulses: f
1.0MHz; t
F
2.5ns; t
R
2.5ns
V
O H
V
OL
V
O H
V
OL
t
PHLA
t
SK(02)
t
SK(02)
t
PLHB
t
PHLB
V
O H
V
OL
V
O H
V
OL
t
SK(01)
t
SK(01)
t
SK(01)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
t
PLH1
t
PHL1
t
PLH2
t
PHL2
V
O H
V
OL
V
OH
V
OL
t
PLH
t
PHL
t
R
t
F
OUTPUT
NORMALLY
HIG H
t
PZL
t
PLZ
t
PHZ
t
PZH
SWITCH
OPEN
t
PLH1
t
PHL1
t
SK(t)
t
SK(t)
t
PLH2
t
PHL2
t
SK(t)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
V
O H
V
OL
V
OL
V
O H
PROPAGATION DELAY
PULSE SKEW -- t
SK(P)
OUTPUT SKEW (SAME BANK) -- t
SK(O1)
TEST CIRCUITS AND WAVEFORMS
OUPUT SKEW (DIFFERENT BANKS) -- t
SK(O2)
ENABLE AND DISABLE TIMES
PART-TO-PART SKEW -- t
SK(T)
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INDUSTRIAL TEMPERATURE RANGE
QS532806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
2975 Stender Way
800-345-7015 or 408-727-6116
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
XXX XX
Device Type
XX
Package
Q
SO
532806
532806A
Quarter Size Small Outline Pacakge (SO20-8)
Small Outline IC (SO 20-2)
Guaranteed Low Skew 3.3V CMO S Clock Driver/Buffer
QS
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