1
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
AUGUST 2000
1999 Integrated Device Technology, Inc.
DSC-5480/-
c
QS52805T/AT
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
OE
A
IN
A
IN
B
OA
5
OA
1
5
5
M O N
OB
5
OB
1
OE
B
DESCRIPTION
The QS52805T clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of five non-inverting outputs. This device provides low propagation delay
buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
The QS52805T has on-chip series termination resistors for lower noise
clock signals. The QS52805T series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise sensitive
clock distribution circuits. These clock buffer products are designed for use
in high-performance workstations and in embedded and personal comput-
ing systems. Several devices can be used in parallel or scattered throughout
a system for guaranteed low skew, system-wide clock distribution networks.
The QS52805T is characterized for operation at -40°C to +85°C.
NOTE: This device has 25
series termination resistors on each clock output including monitor.
FEATURES:
-
10 output, low skew signal buffer
-
Guaranteed low skew:
·
0.7ns output skew (same bank)
·
0.9ns output skew (different bank)
·
1ns part-to-part skew
-
25
on-chip resistors available for low noise
-
Input hysteresis for better noise margin
-
Monitor output
-
Undershoot clamp diodes on all inputs
-
Std. and A speed grades
-
Available in QSOP and SOIC packages
2
INDUSTRIAL TEMPERATURE RANGE
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
PIN CONFIGURATION
QSOP/ SOIC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SO 20-2
SO 20-8
V
CC A
O A
1
O A
2
O A
3
G N D
A
O A
4
O A
5
G N DQ
O E
A
IN
A
V
CC B
O B
1
O B
2
O B
3
G N D
B
O B
4
O B
5
M O N
O E
B
IN
B
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
Unit
V
TERM(2)
Supply Voltage to Ground
0.5 to +7
V
DC Output Voltage V
OUT
0.5 to +7
V
V
TERM(3)
DC Input Voltage V
IN
0.5 to +7
V
V
AC
AC Input Voltage (pulse width
20ns)
-3
V
I
OUT
DC Input Diode Current V
IN
< 0
-20
mA
DC Output Current Max. Sink Current/Pin
120
mA
T
STG
Storage Temperature
65 to +150
°C
T
J
Junction Temperature
150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V)
Pins
Typ.
Max.
(1)
Unit
C
IN
4
6
pF
C
OUT
7
9
pF
NOTE:
1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names
I/O
Description
OEA, OEB
I
Output Enable Inputs
INA, INB
I
Clock Inputs
OAn, OBn
O
Clock Outputs
MON
O
Unbuffered Monitor Output
3
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH for All Inputs
2
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW for All Inputs
--
--
0.8
V
V
IC
Clamp Diode Voltage
(3)
Vcc = Min., I
IN
= -18mA
--
0.7
1.2
V
V
OH
Output HIGH Voltage
Vcc = Min., I
OH
= -12mA
2.4
--
--
V
V
OL
Output LOW Voltage
Vcc = Min., I
OL
= 12mA
--
--
0.5
V
I
IN
Input Leakage Current
Vcc = Max., V
IN
= Vcc or GND
--
--
±1
µ
A
I
OFF
Input/Output Power Off Leakage
Vcc = 0V, V
IN
or V
OUT
= Vcc or GND
--
--
±1
µ
A
I
OZ
Output Leakage Current
Vcc = Max., V
OUT
= Vcc or GND
--
--
±1
µ
A
I
OS
Short Circuit Current
(2,3)
Vcc = Max., V
OUT
= GND
60
--
250
mA
V
T
Input Hysteresis
V
TLH
- V
THL
for All Inputs
--
0.2
--
V
R
OUT
Output Resistance
Vcc = Min., I
OL
= 12mA
--
28
--
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
(3)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or Vcc
0.005
0.5
mA
I
CC
Supply Current per Input HIGH
V
CC
= Max., V
IN
= 3.4V, f
I
= 0MHz
1
2.5
mA
I
CCD
Dynamic Power Supply Current per Output
(2)
V
CC
= Max., V
IN
= GND or Vcc
Outputs Enabled, 50% duty cycle
0.08
0.18
mA/MHz
I
C
Total Power Supply Current Examples
(2,4)
V
CC
= Max.,
OEA = OEB = GND
V
IN
= GND or Vcc
6.6
9.5
mA
50% duty cycle, f
I
= 10MHz
Five outputs toggling
Unused inputs = GND or Vcc
V
IN
= GND or 3.4V
7.2
10.8
V
CC
= Max.,
OEA = OEB = GND
V
IN
= GND or Vcc
4.3
5.5
50% duty cycle, f
I
= 2.5MHz
All outputs toggling
V
IN
= GND or 3.4V
5.6
8
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. C
L
= 0pF.
3. Typical values are for reference only. Conditions are V
CC
= 5.0V, T
A
= 25°C.
4. I
C
= I
CC
+ (
I
CC
)(D
H
)(N
T
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input Duty Cycle
N
T
= Number of TTL HIGH inputs at D
H
(one or two)
f
O
= Output Frequency
N
O
= Number of outputs at f
O
4
INDUSTRIAL TEMPERATURE RANGE
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
C
LOAD
= 50pF (no resistor)
QS52805T
QS52805AT
Symbol
Parameter
(1)
Min.
Max.
Min.
Max.
Unit
t
SK(01)
Skew between two outputs, same transition, same bank
--
0.7
--
0.7
ns
t
SK(02)
Skew between two outputs, same transition, different banks
--
0.9
--
0.9
ns
t
SK(P)
Pulse Skew; opposite transition skew, same output (t
PHL
- t
PLH
)
--
1
--
1
ns
t
SK(T)
Part-to-part skew
(2)
--
1.5
--
1
ns
NOTES:
1. Skew parameters are guaranteed across temperature range, but not tested. Skew parameters apply to propagation delays only.
2. t
SK(T)
only applies to devices of the same transition, part type, temperature, power supply voltage, loading, package, and speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%
C
LOAD
= 50pF (no resistor)
QS52805T
QS52805AT
Symbol
Parameter
(1)
Min.
Max.
Min.
Max.
Unit
t
PLH
t
PHL
Propagation Delay
(2)
1.5
6.5
1.5
5.8
ns
t
PZL
t
PZH
Output Enable Time
1.5
8
1.5
8
ns
t
PLZ
t
PHZ
Output Disable Time
1.5
7
1.5
7
ns
t
R
Output Rise Time, 0.8V to 2V
(3)
--
1.5
--
1.5
ns
t
F
Output Fall Time, 2V to 0.8V
(3)
--
1.5
--
1.5
ns
NOTES:
1. Minimums guaranteed but not production tested.
2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delays do not imply limit skew.
3. This parameter is guaranteed but not tested.
5
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
Pulse
Generator
500
V
CC
V
OUT
V
IN
DUT
50
50pF
6.0 V
Parameter
Tested
Switch
Position
All Others
Closed
Open
t
PLZ
, t
PZL
CONTROL
INPUT
ENABLE
DISABLE
3V
1.5V
0V
3V
0V
1.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
INPUT
OUTPUT 1
3V
1.5V
0V
OUTPUT 2
INPUT
OUTPUT
3V
1.5V
0V
1.5V
2.0V
0.8V
INPUT
PART 1 OUTPUT
3V
1.5V
0V
PART 2 OUTPUT
INPUT
OUTPUT A
t
PLHA
3V
1.5V
0V
OUTPUT B
INPUT
OUTPUT
t
PLH
t
PHL
3V
1.5V
0V
V
O H
V
OL
t
SK(p)
= t
PHL
- t
PLH
t
SK(02)
= t
PLHB
- t
PLHA
or t
PHLB
- t
PHLA
Pulse generator for all pulses: f
1.0MHz; t
F
2.5ns; t
R
2.5ns
V
O H
V
OL
V
O H
V
OL
t
PHLA
t
SK(02)
t
SK(02)
t
PLHB
t
PHLB
V
O H
V
OL
V
O H
V
OL
t
SK(01)
t
SK(01)
t
SK(01)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
t
PLH1
t
PHL1
t
PLH2
t
PHL2
V
O H
V
OL
V
O H
V
OL
t
PLH
t
PHL
t
R
t
F
OUTPUT
NORMALLY
HIGH
t
PZL
t
PLZ
t
PHZ
t
PZH
SWITCH
OPEN
t
PLH1
t
PHL1
t
SK(t)
t
SK(t)
t
PLH2
t
PHL2
t
SK(t)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
V
O H
V
OL
V
OL
V
O H
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
500
PROPAGATION DELAY
PULSE SKEW -- t
SK(P)
OUTPUT SKEW (SAME BANK) -- t
SK(O1)
TEST CIRCUITS AND WAVEFORMS
OUPUT SKEW (DIFFERENT BANKS) -- t
SK(O2)
ENABLE AND DISABLE TIMES
PART-TO-PART SKEW -- t
SK(T)
6
INDUSTRIAL TEMPERATURE RANGE
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
2975 Stender Way
800-345-7015 or 408-727-6116
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
XX XX
Device Type
XX
Package
Q
SO
52805T
52805AT
Quarter Size Sm all Outline Package (SO20-8)
Sm all Outline IC (SO20-2)
Guaranteed Low Skew CM OS Clock Driver/Buffer
QS
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