1 of 25

April 10, 2001

2001 Integrated Device Technology, Inc.

DSC 9096

64-Bit RISC Microprocessor

Features

True 64-bit microprocessor

 64-bit integer operations

 64-bit floating-point operations

 64-bit registers

 64-bit virtual address space

High-performance microprocessor

 260 Dhrystone MIPS at 200MHz

 100 peak MFLOP/s at 200MHz

 Two-way set associative caches

 Simple 5-stage pipeline

High level of integration

 64-bit, 200 MHz integer CPU

 64-bit floating-point unit

 16KB instruction cache

 16KB data cache

 Flexible MMU with large, fully associative TLB

Low-power operation

 3.3V power supply, for the "RV" part

 5V power supply, for the "R" part

 Dynamic power management

 Standby mode reduces internal power

Fully software & pin-compatible with 40

Processor Family

Available in 179-pin PGA or 208-pin QFP

Available at 80-200MHz, with mode bit dependent output
clock frequencies

64GB physical address space

Processor family for a wide variety of embedded
applications

 LAN switches

 Routers

 Color printers

Description

The IDT79R4700 64-bit RISC Microprocessor is both software and

pin-compatible with the R4

XXX

processor family. With 64-bit processing

capabilities, the R4700 provides more computational power and data
movement bandwidth than is delivered to typical embedded systems by
32-bit processors.

The R4700 is upwardly software compatible with the IDT79R3000

microprocessor family, including the IDTRISController

79R3051

R3052

, R3041

, R3081

as well as the R4640

, R4650

, RC64474/

475

and R5000

. An array of development tools facilitates rapid

development of R4700-based systems, allowing a variety of customers
access to the MIPS Open Architecture philosophy.

Block Diagram

The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.

Read Buffer

Integer Register File

Integer/Address Adder

Data TLB Virtual

Shifter/Store Aligner

Logic Unit

Program Counter

PC Increm enter

Branch Adder

Load Aligner

Floating-point

Unpacker/Packer

Floating-point

Add/Sub/Cvt/Div/Sqrt

Integer Divide

Floating-point/Integer

Phase Lock Loop, Clocks

Instruction TLB Virtual

Joint TLB

Data Set A

Data Set B

Data Tag A

DTLB Physical

Address Buffer

Data Tag B

Instruction Tag A

Instruction Tag B

ITLB Physical

Store Buffer

Write Buffer

DVA

IVA

Instruction Set A

Instruction Set B

Multiply

l
oa

t
i
ng-

i
n

t
C

r
o

I
n

t
e

r
C
ont

r
o

SysAD

IBus

DBus

Coprocessor 0

System /Mem ory

Control

Tag

AuxTag

Instruction Select

Control

Instruction Register

Register File

IDT79R4700

2 of 25

April 10, 2001

IDT79R4700

This data sheet provides an overview of the R4700's CPU features

and architecture. A more detailed description of this processor is
provided in the IDT79R4700 RISC Processor Hardware User's Manual,
available from Integrated Device Technology (IDT). Information on
development support, applications notes and complementary products
is available on the IDT Web site www.idt.com or through your local IDT
sales representative.

Note: Throughout this data sheet and any other IDT materials for this

device, the R4700 indicates a 5V part; RV4700 designates a reduced
voltage (3V) part; and the RC4700 reflects either.

Figure 1 The RC4700 CPO Registers

Hardware Overview

The RC4700 processor family brings a high-level of integration

designed for high-performance computing. The R4700's key elements
are briefly described below. A more detailed explanation of each
subsystem is available in the user's manual.

Pipeline

The RC4700 uses a simple 5-stage pipeline, similar to the pipeline

structure implemented in the IDT79R32364. This pipeline's simplicity
allows the RC4700 to be lower cost and lower power than super-scalar
or super-pipelined processors. The pipeline stages are shown in Figure
3 on page 3.

Integer Execution Engine

The R4700 implements the MIPS-III Instruction Set architecture and

is upwardly compatible with applications that run on earlier generation
parts.

Implementation of the MIPS-III architecture results in 64-bit opera-

tions, better code density, greater multi-processing support, improved
performance for commonly used code sequences in operating system
kernels and faster execution of floating-point intensive applications. All

TLB

(entries protected

from TLB W R )

E ntryH i

10*

EntryLo0

E ntryLo1

PageMask

Wired

Random

Index

S tatus

12*

Cause

13*

E P C

14*

ErrorEPC

30*

C ount

Com pare

11*

C ontext

X C ontext

20*

P RId

15*

Config

16*

TagH i

29*

TagLo

28*

E C C

26*

CacheErr

27*

BadVAddr

LLA ddr

17*

* Register number

resource dependencies are made transparent to the programmer,
insuring transportability among implementations of the MIPS instruction
set architecture.

The MIPS integer unit implements a load/store architecture with

single cycle ALU operations (logical, shift, add, sub) and an autono-
mous multiply/divide unit. Register resources include:

32 general-purpose orthogonal integer registers

HI/LO result registers, for the integer multiply/divide unit

Program counter

Also, the on-chip floating-point co-processor adds 32 floating-point

registers and a floating-point control/status register.

The R4700 has 32 general-purpose registers (shown in Figure 2).

These registers are used for scalar integer operations and address
calculation. The register file consists of two read ports and one write
port and is fully bypassed to minimize operation latency in the pipeline.

ALU

The RC4700 ALU consists of the integer adder and logic unit. The

adder performs address calculations in addition to arithmetic operations,
and the logic unit performs all logical and shift operations. Each of these
units is highly optimized and can perform an operation in a single pipe-
line cycle.

Integer Multiply/Divide

To perform integer multiply and divide operations, the RC4700 uses

the floating-point unit. The results of the operation are placed in the HI
and LO registers. The values can then be transferred to the general
purpose register file using the MFHI/MFLO instructions. To prevent the

General Purpose Registers

Multiply/Divide Registers

·
·

Program Counter

r29

r30
r31

Figure 2 R4700 CPU Registers

4 of 25

April 10, 2001

IDT79R4700

occurrence of an interlock or stall, a required number of processor
internal cycles must occur between an integer multiply or divide and a
subsequent MFHI or MFLO operation.

Floating-Point Co-Processor

The RC4700 incorporates a complete floating-point co-processor on

chip and includes a floating-point register file and execution units. The
floating-point co-processor forms a "seamless" interface with the integer
unit, decoding and executing instructions in parallel with the integer unit.

Floating-Point Units

The RC4700 floating-point execution units support single and double

precision arithmetic, as specified in the IEEE Standard 754. The execu-
tion unit is separated into a multiply unit and a combined add/convert/
divide/square root unit. Overlap of multiplies and add/subtract is
supported. The multiplier is partially pipelined, allowing a new multiply to
begin every four cycles.

The RC4700 maintains fully precise floating-point exceptions while

allowing both overlapped and pipelined operations. Precise exceptions
are extremely important in mission-critical environments and highly
desirable for debugging in any environment.

The floating-point unit operation's set includes floating-point add,

subtract, multiply, divide, square root, conversion between fixed-point
and floating-point format, conversion among floating-point formats and
floating-point compare. These operations comply with the IEEE Stan-
dard 754.

Table 1 lists the latencies of some of the floating-point instructions in

internal processor cycles. Note that multiplies are pipelined so that a
new multiply can be initiated every four pipeline cycles

Floating-Point General Register File

The floating-point register file is made up of thirty-two 64-bit regis-

ters. With the LDC1 and SDC1 instructions the floating-point unit can
take advantage of the 64-bit wide data cache and issue a co-processor
load or store doubleword instruction in every cycle.

The floating-point control register space contains two registers: one

for determining configuration and revision information for the copro-
cessor and one for control and status information. These are primarily
involved with diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.

Operation

32-bit

64-bit

MULT

6 - 9

7 - 10

DIV

System Control Co-processor (CP0)

The system control co-processor in the MIPS architecture is respon-

sible for the virtual memory sub-system, the exception control system
and the diagnostics capability of the processor. In the MIPS architec-
ture, the system control co-processor (and thus the kernel software) is
implementation dependent.

System Control Co-Processor Registers

The RC4700 incorporates all system control co-processor (CP0)

registers, on-chip. These registers (shown in Figure 1 on page 2)
provide the path through which the virtual memory system's page
mapping is examined and changed, exceptions are handled and oper-
ating modes are controlled (kernel vs. user mode, interrupts enabled or
disabled, cache features). In addition, to aid in cache diagnostic testing
and assist in data error detection, the RC4700 includes registers to
implement a real-time cycle counting facility.

Virtual-to-Physical Address Mapping

To establish a secure environment for user processing, the RC4700

provides the user, supervisor, and kernel modes of virtual addressing,
available to system software. Bits in a status register determine which
virtual addressing mode is used.

While in user mode, the RC4700 provides a single, uniform virtual

address space of 256GB (2GB for 32-bit address mode). When oper-
ating in the kernel mode, four distinct virtual address spaces--totalling
1024GB (4GB in 32-bit address mode)--are simultaneously available
and are differentiated by the high-order bits of the virtual address.

Operation

Single

Precision

Double

Precision

ADD

SUB

MUL

DIV

SQRT

CMP

FIX

FLOAT

ABS

MOV

NEG

LWC1, LDC1

SWC1, SDC1

Table 1 RC4700 Instruction Latencies

5 of 25

April 10, 2001

IDT79R4700

The RC4700 processor also supports a supervisor mode in which the

virtual address space is 256.5GB (2.5GB in 32-bit address mode),
divided into three regions that are based on the high-order bits of the
virtual address. If the RC4700 is configured for 64-bit virtual addressing,
the virtual address space layout is an upwardly compatible extension of
the 32-bit virtual address space layout. Figure 4 on page 5 shows the
address space layout for the 32-bit virtual address operation.

Memory Management Unit (MMU)

The Memory management unit controls the virtual memory system

page mapping. It consists of an instruction address translation buffer
(the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the
JTLB), and co-processor registers used for the virtual memory mapping
sub-system.

Instruction TLB (ITLB)

The RC4700 also incorporates a two-entry instruction TLB. Each

entry maps a 4KB page. The instruction TLB improves performance by
allowing instruction address translation to occur in parallel with data
address translation. When a miss occurs on an instruction address
translation, the least-recently used ITLB entry is filled from the JTLB.
The operation of the ITLB is invisible to the user.

Data TLB (DTLB)

The RC4700 also incorporates a four-entry data TLB. Each entry

maps a 4KB page. The data TLB improves performance by allowing
data address translation to occur in parallel with instruction address
translation. When a miss occurs on a data address translation, the DTLB
is filled from the JTLB. The DTLB refill is pseudo-LRU: the least recently
used entry of the least recently used half is filled. The operation of the
DTLB is invisible to the user.

Joint TLB (JTLB)

For fast virtual-to-physical address decoding, the RC4700 uses a

large, fully associative TLB that maps 96 virtual pages to their corre-
sponding physical addresses. The TLB is organized as 48 pairs of even-
odd entries and maps a virtual address and address space identifier into
the large, 64GB physical address space.

Two mechanisms are provided to assist in controlling the amount of

mapped space and the replacement characteristics of various memory
regions. First, the page size can be configured, on a per-entry basis, to
map a page size of 4KB to 16MB (in multiples of 4). A CP0 register is
loaded with the page size of a mapping, and that size is entered into the
TLB when a new entry is written. Thus, operating systems can provide
special purpose maps; for example, a typical frame buffer can be
memory mapped using only one TLB entry.

The second mechanism controls the replacement algorithm, when a

TLB miss occurs. The RC4700 provides a random replacement algo-
rithm to select a TLB entry to be written with a new mapping; however,
the processor provides a mechanism whereby a system specific number

of mappings can be locked into the TLB and avoid being randomly
replaced. This facilitates the design of real-time systems, by allowing
deterministic access to critical software.

The joint TLB also contains information to control the cache coher-

ency protocol for each page. Specifically, each page has attribute bits to
determine whether the coherency algorithm is uncached, non-coherent
write-back, non-coherent write-through write-allocate or non-coherent
write-through no write-allocate. Non-coherent write-back is typically
used for both code and data on the RC4700; however, hardware-based
cache coherency is not supported.

Cache Memory

To keep the RC4700's high-performance pipeline full and operating

efficiently, the RC4700 incorporates on-chip instruction and data caches
that can be accessed in a single processor cycle. Each cache has its
own 64-bit data path and can be accessed in parallel.

Instruction Cache

The RC4700 incorporates a two-way set associative on-chip instruc-

tion cache. This virtually indexed, physically tagged cache is 16KB in
size and is protected with word parity.

0xFFFFFFFF

0xE0000000

Kernel virtual address space

(kseg3)

Mapped, 0.5GB

0xDFFFFFFF

Supervisor virtual address space

(sseg)

Mapped, 0.5GB

0xC0000000

0xBFFFFFFF

0xA0000000

Uncached kernel physical address space

(kseg1)

Unmapped, 0.5GB

0x9FFFFFFF

0x80000000

Cached kernel physical address space

(kseg0)

Unmapped, 0.5GB

0x7FFFFFF

0x00000000

User virtual address space

(useg)

Mapped, 2.0GB

Figure 4 Kernel Mode Virtual Addressing (32-bit Mode)

6 of 25

April 10, 2001

IDT79R4700

Because the cache is virtually indexed, the virtual-to-physical

address translation occurs in parallel with the cache access, further
increasing performance by allowing these two operations to occur simul-
taneously. The tag holds a 24-bit physical address and valid bit and is
parity protected.

The instruction cache is 64-bits wide and can be refilled or accessed

in a single processor cycle. For a peak instruction bandwidth of 800MB/
sec at 200MHz, instruction fetches require only 32 bits per cycle. To
reduce power dissipation, sequential accesses take advantage of the
64-bit fetch. To minimize the cache miss penalty, cache miss refill writes
use 64 bits-per-cycle, and to maximize cache performance, the line size
is eight instructions (32 bytes).

Data Cache

For fast, single cycle data access, the RC4700 includes a 16KB on-

chip data cache that is two-way set associative with a fixed 32-byte
(eight words) line size.

The data cache is protected with byte parity and its tag is protected

with a single parity bit. It is virtually indexed and physically tagged to
allow simultaneous address translation and data cache access

The normal write policy is writeback, which means that a store to a

cache line does not immediately cause memory to be updated. This
increases system performance by reducing bus traffic and eliminating
the bottleneck of waiting for each store operation to finish before issuing
a subsequent memory operation. Software can however select write-
through on a per-page basis when it is appropriate, such as for frame
buffers.

Associated with the data cache is the store buffer. When the RC4700

executes a Store instruction, this single-entry buffer gets written with the
store data while the tag comparison is performed. If the tag matches,
then the data is written into the data cache in the next cycle that the data
cache is not accessed (the next non-load cycle). The store buffer allows
the R4700 to execute a store instruction every processor cycle and to
perform back-to-back stores without penalty.

The data cache can provide 8 bytes each clock cycle, for a peak

bandwidth of 1.6 GB/sec.

Write Buffer

Writes to external memory--whether they are cache miss write-

backs, stores to uncached or write-through addresses--use the on-chip
write buffer. The write buffer holds a maximum of four 64-bit address and
64-bit data pairs. The entire buffer is used for a data cache writeback
and allows the processor to proceed in parallel with memory updates.

System Interface

The RC4700 supports a 64-bit system interface. This interface oper-

ates from two clocks--TClock[1:0] and RClock[1:0]--provided by the
RC4700, at some division of the internal clock.

The system interface consists of a 64-bit Address/Data bus with

eight check bits and a 9-bit command bus protected with parity. In addi-
tion, there are eight handshake signals and six interrupt inputs. The
interface has a simple timing specification and is capable of transferring
data between the processor and memory at a peak rate of 500MB/sec
with a 67MHz bus.

System Address/Data Bus

The 64-bit System Address Data (SysAD) bus is used to transfer

addresses and data between the RC4700 and the rest of the system. It
is protected with an 8-bit parity check bus, SysADC.

The system interface is configurable to allow easier interfacing to

memory and I/O systems of varying frequencies. The data rate and the
bus frequency at which the RC4700 transmits data to the system inter-
face are programmable via boot time mode control bits. Also, the rate at
which the processor receives data is fully controlled by the external
device. Therefore, either a low cost interface requiring no read or write
buffering or a faster, high performance interface can be designed to
communicate with the RC4700. Again, the system designer has the flex-
ibility to make these price/performance trade-offs.

System Command Bus

The RC4700 interface has a 9-bit System Command (SysCmd) bus.

The command bus indicates whether the SysAD bus carries an address
or data. If the SysAD carries an address, then the SysCmd bus also
indicates what type of transaction is to take place (for example, a read
or write). If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data word trans-
mitted, or the cache state of this data line is clean exclusive). The
SysCmd bus is bidirectional to support both processor requests and
external requests to the RC4700. Processor requests are initiated by
the RC4700 and responded to by an external device. External requests
are issued by an external device and require the RC4700 to respond.

The RC4700 supports one to eight byte and block transfers on the

SysAD bus. In the case of a sub-doubleword transfer, the low-order
three address bits give the byte address of the transfer, and the
SysCmd bus indicates the number of bytes being transferred.

Handshake Signals

There are six handshake signals on the system interface. Two of

these, RdRdy* and WrRdy* are used by an external device to indicate to
the RC4700 whether it can accept a new read or write transaction. The
RC4700 samples these signals before deasserting the address on read
and write requests.

ExtRqst* and Release* are used to transfer control of the SysAD and

SysCmd buses between the processor and an external device. When
an external device needs to control the interface, it asserts ExtRqst*.
The RC4700 responds by asserting Release* to release the system
interface to slave state.

7 of 25

April 10, 2001

IDT79R4700

ValidOut* and ValidIn* are used by the RC4700 and the external

device respectively to indicate that there is a valid command or data on
the SysAD and SysCmd buses. The RC4700 asserts ValidOut* when it
is driving these buses with a valid command or data, and the external
device drives ValidIn* when it has control of the buses and is driving a
valid command or data.

Non-overlapping System Interface

The RC4700 bus uses a non-overlapping system interface. This

means that only one processor request may be outstanding at a time
and that the request must be serviced by an external device before the
RC4700 issues another request. The RC4700 can issue read and write
requests to an external device, and an external device can issue read
and write requests to the RC4700.

For processor read transaction the RC4700 asserts ValidOut* and

simultaneously drives the address and read command on the SysAD
and SysCmd buses. If the system interface has RdRdy* asserted, then
the processor tristates its drivers and releases the system interface to
slave state by asserting Release*. The external device can then begin
sending the data.

Figure 5 on page 10 shows a processor block read request and the

external agent read response. The read latency is four cycles (ValidOut*
to ValidIn*), and the response data pattern is DDxxDD. Figure 6 on
page 10 shows a processor block write.

Write Reissue and Pipeline Write

The RC4700 implements additional write protocols that have been

designed to improve performance. This implementation doubles the
effective write bandwidth. The write re-issue has a high repeat rate of
two cycles per write. A write issues if WrRdy* is asserted two cycles
earlier and is still asserted at the issue cycle. If it is not still asserted, the
last write re-issues again. Pipelined writes have the same two cycle per
write repeat rate but can issue one additional write after WrRdy* de-
asserts. They still follow the issue rule as R4x00 mode for other writes.

External Requests

The RC4700 responds to requests issued by an external device. The

requests can take several forms. An external device may need to supply
data in response to an RC4700 read request or it may need to gain
control over the system interface bus to access other resources which
may be on that bus. It also may issue requests to the processor, such as
a request for the RC4700 to write to the RC4700 interrupt register. The
RC4700 supports Write, Null, and Read Response external requests.

Boot-Time Options

Fundamental operational modes for the processor are initialized by

the boot-time mode control interface. The boot-time mode control inter-
face is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization

information to be kept in a low-cost serial EEPROM; alternatively, the
20-or-so bits could be generated by the system interface ASIC or a
simple PAL.

Immediately after the V

CCOK

signal is asserted, the processor reads a

bit stream of 256 bits to initialize all fundamental operational modes.
After initialization is complete, the processor continues to drive the serial
clock output, but no further initialization bits are read.

JTAG Interface

The RC4700 supports the JTAG interface pins, with the serial input

connected to serial output. Boundary scan is not supported.

Boot-Time Modes

The boot-time serial mode stream is defined in Table 3. Bit 0 is the

first bit presented to the processor when V

CCOK

is asserted; bit 255 is the

last.

Power Management

1
1
1
1

CP0 is also used to control the power management for the RC4700.

This is the standby mode and can be used to reduce the power
consumption of the internal core of the CPU. Standby mode is entered
by executing the WAIT instruction with the SysAD bus idle and is exited
by an interrupt.

Standby Mode Operations

The RC4700 provides a means to reduce the amount of power

consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as "Standby Mode."

Entering Standby Mode

Executing the WAIT instruction enables interrupts and enters

Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, some of the input pin
clocks (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*), and the
output clocks--TClock[1:0], RClock[1:0] SyncOut, Modeclock and
MasterOut--will continue to run. If the conditions are not correct when
the WAIT instruction finishes the W pipe-stage (such as the SysAd bus
is not idle), the WAIT is treated as a NOP.

Once the CPU is in Standby Mode, any interrupt-- including the

internally generated timer interrupt--will cause the CPU to exit Standby
Mode.

The R4700 implements advanced power management, to substantially

reduce the average power dissipation of the device. This operation is described
in the R4700 Microprocessor Hardware User's Manual.

8 of 25

April 10, 2001

IDT79R4700

Thermal Considerations

The RC4700 uses special packaging techniques to improve the

thermal properties of high-speed processors. The RC4700 is packaged
using cavity down packaging in a 179-pin PGA package, and a 208-lead
QFP package. These packages effectively dissipate the power of the
CPU, increasing device reliability.

The R4700 is guaranteed in a case temperature range of 0

to +85

C. The type of package, speed (power) of the device, and airflow condi-
tions affect the equivalent ambient temperature conditions that will meet
this specification.

The equivalent allowable ambient temperature, T

, can be calculated

using the thermal resistance from case to ambient (

) of the given

package. The following equation relates ambient and case tempera-
tures:

= T

- P *

where P is the maximum power consumption at hot temperature,

calculated by using the maximum I

specification for the device.

Typical values for

at various airflows are shown in Table 2:.

Revision History

January 1996: Initial draft.
March 1997: Deleted data on 150MHz speed for 5V part only.
August 1997: Upgraded 80 to 175 MHz speed specs from "Prelimi-

nary" to "Final."

June 1999: Upgraded speed to 200MHz on 3V part specs. Package

change to DP.

June 29, 2000: Added back 175 and 200 MHz speeds.
April 10, 2001: In the Data Output category of the System Interface

Parameters tables, changed values in the Min column for all speeds
from 1.0 to 0.

Airflow (ft/min)

200

400

600

800

1000

PGA

2.5

QFP

Table 2:

Thermal Resistance (

CA) at Various Airflows

11 of 25

April 10, 2001

IDT79R4700

Pin Description

The table below provides a list of interface, interrupt and miscellaneous pins that are available on the RC4700. Note that signals marked with an

asterisk are active when low. Boundary scan is not supported.

Pin Name Type

Description

System Interface

ExtRqst*

External request
Signals that the system interface needs to submit an external request.

Release*

Release interface
Signals that the processor is releasing the system interface to slave state.

RdRdy*

Read Ready
Signals that an external agent can now accept a processor read.

WrRdy*

Write Ready
Signals that an external agent can now accept a processor write request.

ValidIn*

Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-
mand or data identifier on the SysCmd bus.

ValidOut*

Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or
data identifier on the SysCmd bus.

SysAD(63:0)

I/O

System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.

SysADC(7:0)

I/O

System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0)

I/O

System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.

SysCmdP

I/O

Reserved system command/data identifier bus parity
for the R4700 unused on input and zero on output.

Clock/Control Interface

MasterClock

Master clock
Master clock input at one half the processor operating frequency.

MasterOut

Master clock out
Master clock output aligned with MasterClock.

RClock(1:0)

Receive clocks
Two identical receive clocks at the system interface frequency.

TClock(1:0)

Transmit clocks
Two identical transmit clocks at the system interface frequency.

IOOut

Reserved for future output
Always HIGH.

IOIn

Reserved for future input
Should be driven HIGH.

SyncOut

Synchronization clock out
Must be connected to SyncIn through an interconnect that models the interconnect between MasterOut,
TClock, RClock, and the external agent.

SyncIn

Synchronization clock in
Synchronization clock input. See SyncOut.

Fault*

Fault
Always HIGH.

12 of 25

April 10, 2001

IDT79R4700

Absolute Maximum Ratings

Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Quiet V

for PLL

Quiet V

for the internal phase locked loop.

Quiet V

for PLL

Quiet V

for the internal phase locked loop.

Interrupt Interface

Int*(5:0)

Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI*

Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.

Initialization Interface

CCO

is OK

When asserted, this signal indicates to the R4700 that the power supply has been above the Vcc minimum
for more than 100 milliseconds and will remain stable. The assertion of V

CCO

k initiates the reading of the

boot-time-mode-control serial stream.

ColdReset*

Cold reset
This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock, and RClock
begin to cycle and are synchronized with the de-assertion edge of ColdReset. ColdReset must be de-
asserted synchronously with MasterOut.

Reset*

Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously
for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with
MasterOut.

ModeClock

Boot-mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.

ModeIn

Boot-mode data in
Serial boot-mode data input.

Symbol

Rating

RV4700

3.3V±5%

R4700

5.0V±5%

Unit

Commercial

TERM

Terminal Voltage with respect to GND

0.5

to +4.6

minimum = -2.0V for pulse width less than 15ns. V

should not exceed V

+0.5V.

0.5

to +7.0

Operating Temperature (case)

0 to +85

BIAS

Case Temperature Under Bias

55 to +125

STG

Storage Temperature

55 to +125

DC Input Current

When V

< 0.0V or V

OUT

DC Output Current

Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

Pin Name Type

Description

13 of 25

April 10, 2001

IDT79R4700

Recommended Operation Temperature and Supply Voltage

DC Electrical Characteristics--R4700

(

= 5.0

%, T

CASE

= 0

C to +85

Power Consumption--R4700

Grade

Temperature

GND

RV4700

R4700

Commercial

C to +85

C (Case)

3.3V±5%

5.0V±5%

Parameter

R4700 80 MHz

R4700 100MHz

R4700 133MHz

Conditions

Min

Max

Min

Max

Min

Max

0.1V

OUT

|= 20uA

- 0.1V

0.4V

OUT

|= 4mA

3.5V

0.5V

0.8V

0.5V

0.8V

0.5V

0.8V

2.0V

0.5V

2.0V

0.5V

2.0V

0.5V

±10uA

15pF

OUT

15pF

I/O

LEAK

20uA

Input/Output

Leakage

Parameter

R4700 80 MHz

R4700 100MHz

R4700 133MHz

Conditions

Typical

Max

Typical

Typical integer instruction mix and cache miss rates.

Max

Typical

Max

System

Condition:

80/20 MHz

100/25MHz

133/33MHz

standby

150mA

These are not tested. They are the result of engineering analysis and are provided for reference only.

175mA

225mA

= 0pF

Guaranteed by design.

215mA

250mA

325mA

= 50pF

active

750mA

850 mA

875mA

1000mA

1175mA

1300mA

= 0pF

No SysAd activity

850mA

1050mA

975mA

1200mA

1275mA

1500mA

= 50pF

R4x00 compatible writes
T

= 25

850mA

1250mA

975mA

1400mA

These are the specifications IDT tests to insure compliance.

1275mA

1675mA

= 50pF

Pipelined writes or write
re-issue
T

= 25

14 of 25

April 10, 2001

IDT79R4700

AC Electrical Characteristics--R4700

=5.0V

5%; T

CASE

= 0

C to +85

Clock Parameters--R4700

System Interface Parameters--R4700

Note:

Timings are measured from 1.5V of the clock to 1.5V of the signal.

Boot-Time Interface Parameters--R4700

Parameter

Symbol

Test

Conditions

R4700

80MHz

R4700

100MHz

R4700

133MHz

Units

Min

Max

Min

Max

Min

Max

MasterClock HIGH

MCHIGH

Transition

MCRise

MasterClock LOW

MCLOW

Transition

MCFall

MasterClock Frequency

Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.

MHz

MasterClock Period

MCP

Clock Jitter for MasterClock

JitterIn

Guaranteed by design.

±250

Clock Jitter for
MasterOut, SyncOut, TClock, RClock

JitterOut

±500

MasterClock Rise Time

MCRise

5.5

MasterClock Fall Time

MCFall

5.5

ModeClock Period

ModeCKP

256*t

MCP

256*t

MCP

256*t

MCP

JTAG Clock Period

JTAGCKP

4*t

MCP

4*t

MCP

4*t

MCP

SyncOut to SyncIn Delay

Sync

2,3

Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.

2*t

MCP

2*t

MCP

2*t

MCP

Parameter

Symbol

Test Conditions

R4700

80MHz

R4700

100MHz

R4700

133MHz

Units

Min

Max

Min

Max

Min

Max

Data Output

mode

14..13

= 10 (fastest)

Guaranteed by design.

mode

14..13

= 01 (slowest)

Input Data Setup

rise

= 5ns

fall

= 5ns

3.5

Input Data Hold

1.5

Parameter

Symbol

Test

Conditions

R4700

80MHz

R4700

100MHz

R4700

133MHz

Units

Min

Max

Min

Max

Min

Max

Mode Data Setup

Master ClockCycle

Mode Data Hold

Master ClockCycle

15 of 25

April 10, 2001

IDT79R4700

Capacitive Load Deration--R4700

AC Electrical Characteristics -- RV4700

=3.3V

5%; T

CASE

= 0

C to +85

Clock Parameters

Parameter

Symbol

R4700 80MHz

R4700 100MHz

R4700 133MHz

Units

Min

Max

Min

Max

Min

Max

Load Derate

ns/25pF

Parameter

Symbol

Test

Conditions

RV4700

100MHz

RV4700

133MHz

RV4700

150MHz

Units

Min

Max

Min

Max

Min

Max

MasterClock HIGH

MCHIGH

Transition

MCRise/Fall

MasterClock LOW

MCLOW

Transition

MCRise/Fall

MasterClock Frequency

Typical integer instruction mix and cache miss rates.

MHz

MasterClock Period

MCP

13.3

Clock Jitter for MasterClock

JitterIn

Guaranteed by Design.

±250

Clock Jitter for MasterOut,
SyncOut, TClock, RClock

JitterOut

±500

MasterClock Rise Time

MCRise

3.5

MasterClock Fall Time

MCFall

3.5

ModeClock Period

ModeCKP

256*t

MCP

256*t

MCP

256*t

MCP

SyncOut to SyncIn Delay

Sync

2, 3

Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.

2*t

MCP

2*t

MCP

2*t

MCP

Parameter

Symbol

Test Conditions

RV4700

175MHz

Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.

RV4700

200MHz

Units

Min

Max

Min

Max

MasterClock HIGH

MCHIGH

Transition

MCRise/Fall

MasterClock LOW

MCLOW

Transition

MCRise/Fall

MasterClock Frequency

Typical integer instruction mix and cache miss rates.

87.5

100

MHz

MasterClock Period

MCP

11.4

Clock Jitter for MasterClock

JitterIn

Guaranteed by design.

±250

Clock Jitter for MasterOut,
SyncOut, TClock, RClock

JitterOu

±500

MasterClock Rise Time

MCRise

3.5

MasterClock Fall Time

MCFall

3.5

ModeClock Period

ModeCKP

256*t

MCP

256*t

MCP

SyncOut to SyncIn Delay

Sync

3, 4

Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.

2*t

MCP

2*t

MCP

16 of 25

April 10, 2001

IDT79R4700

DC Electrical Characteristics--RV4700

= 3.3

%, T

CASE

= 0

C to +85

Parameter

RV4700 100MHz

RV4700 133MHz

Conditions

Min

Max

Min

Max

0.1V

OUT

|= 20uA

- 0.1V

0.4V

OUT

|= 4mA

2.4V

0.5V

0.2V

0.5V

0.2V

0.7V

+ 0.5V

0.7V

+ 0.5V

±10uA

15pF

OUT

15pF

I/O

LEAK

20uA

Input/Output Leakage

Parameter

RV4700 150MHz

RV4700 175MHz

RV4700 200MHz

Conditions

Min

Max

Min

Max

Min

Max

0.1V

OUT

|= 20uA

- 0.1V

0.4V

OUT

|= 4mA

2.4V

0.5V

0.2V

0.5V

0.2V

0.5V

0.2V

0.7V

+ 0.5V

0.7V

+ 0.5V

0.7V

+ 0.5V

±10uA

15pF

OUT

15pF

I/O

LEAK

20uA

Input/Output Leakage

17 of 25

April 10, 2001

IDT79R4700

System Interface Parameters--RV4700

Note: Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.

Boot-Time Interface Parameters--RV4700

Parameter

Symbol

Test Conditions

RV4700

100MHz

RV4700

133MHz

RV4700

150MHz

Units

Min

Max

Min

Max

Min

Max

Data Output

Timings are measured from 1.5V of the clock to 1.5V of the signal.

= Min

= Max

mode

14..13

= 10 (fastest)

mode

14..13

= 01 (slowest)

Input Data Setup

rise

= 3ns

fall

= 3ns

3.5

Input Data Hold

1.5

Parameter

Symbol

Test Conditions

RV4700

175MHz

RV4700

200MHz

Units

Min

Max

Min

Max

Data Output

Capacitive load for all output timings is 50pF.

= Min

= Max

mode

14..13

= 10 (fastest)

mode

14..13

= 01 (slowest)

Input ata Setup

rise

= 3ns

fall

= 3ns

3.5

Input Data Hold

1.5

Parameter

Symbol

Test

Conditions

RV4700 100MHz RV4700 133MHz RV4700 150MHz

Units

Min

Max

Min

Max

Min

Max

Mode Data Setup

Master Clock Cycle

Mode Data Hold

Master Clock Cycle

Parameter

Symbol

Test

Conditions

RV4700 175MHz

RV4700 200MHz

Units

Min

Max

Min

Max

Mode Data Setup

Master Clock Cycle

Mode Data Hold

Master Clock Cycle

18 of 25

April 10, 2001

IDT79R4700

Power Consumption--RV4700

Parameter

RV4700 100MHz RV4700 133MHz RV4700 150MHz

Conditions

Typical

Typical integer instruction mix and cache miss rates.

Max Typical

Max

System

Condition

100/25MHz

133/33MHz

150/38MHz

standby

125mA

These are not tested. They are the result of engineering analysis and are provided for reference only.

175mA

200mA

= 0pF

Guaranteed by design.

175mA

225mA

250mA

= 50pF

active

575mA

875mA

775mA

1150mA

875mA

1300mA

= 0pF,

No SysAd activity

650mA

1100mA

850mA

1375mA

950mA

1550mA

= 50pF R4x00 compatible writes, T

= 25

650mA

1275mA

These are the specifications IDT tests to insure compliance.

850mA

1525mA

950mA

1725mA

= 50pF Pipelined writes or write re-issue, T

= 25

Parameter

RV4700 175MHz

RV4700 200MHz

Conditions

Typical

Typical integer instruction mix and cache miss rates.

Max

Typical

Max

System Condition

175/44MHz

200/50MHz

standby

200mA

These are not tested. They are the result of engineering analysis and are provided for reference only.

200mA

= 0pF

Guaranteed by design.

250mA

= 50pF

active

1025mA

1500mA

1025mA

1500mA

= 0pF,

No SysAd activity

1200mA

1800mA

1200mA

1800mA

= 50pF R4x00 compatible writes, T

= 25

1200mA

2000mA

These are the specifications IDT tests to insure compliance.

1200mA

2000mA

= 50pF Pipelined writes or write re-issue, T

= 25

19 of 25

April 10, 2001

IDT79R4700

RC4700 QFP Package Pin-Out

Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.

Function

N.C.

105

N.C.

157

N.C.

106

N.C.

158

N.C.

VSS

SysCmd2

107

N.C.

159

RClock0

VCC

SysAD36

108

N.C.

160

RClock1

SysAD45

SysAD4

109

VCC

161

SyncOut

SysAD13

SysCmd1

110

VSS

162

SysAD30

Fault*

VSS

111

SysAD21

163

VCC

SysAD44

VCC

112

SysAD53

164

VSS

SysAD35

113

RdRdy*

165

SysAD62

VCC

SysAD3

114

ModeIn

166

MasterOut

SysAD12

SysCmd0

115

SysAD22

167

SysAD31

SysCmdP

SysAD34

116

SysAD54

168

SysAD63

SysAD43

VSS

117

VCC

169

VCC

SysAD11

VCC

118

VSS

170

VSS

N.C.

119

Release*

171

VCCOK

VCC

N.C.

120

SysAD23

172

SysADC3

SysCmd8

SysAD2

121

SysAD55

173

SysADC7

SysAD42

Int5*

122

NMI*

174

VCC

SysAD10

SysAD33

123

VCC

175

VSS

SysCmd7

SysAD1

124

VSS

176

N.C.

VSS

125

SysADC2

177

N.C.

VCC

126

SysADC6

178

N.C.

SysAD41

Int4*

127

VCC

179

N.C.

SysAD9

SysAD32

128

SysAD24

180

N.C.

SysCmd6

SysAD0

129

VCC

181

VCCP

SysAD40

Int3*

130

VSS

182

VSSP

N.C.

VSS

131

SysAD56

183

N.C.

VCC

132

N.C.

184

N.C.

VSS

Int2*

133

SysAD25

185

MasterClock

VCC

SysAD16

134

SysAD57

186

VCC

SysAD8

SysAD48

135

VCC

187

VSS

SysCmd5

Int1*

136

VSS

188

SyncIn

SysADC4

VSS

137

IOOut

189

VCC

SysADC0

VCC

138

SysAD26

190

VSS

SysAD17

139

SysAD58

191

N.C.

VCC

SysAD49

140

IOIn

192

SysADC5

SysCmd4

Int0*

141

VCC

193

SysADC1

SysAD39

SysAD18

142

VSS

194

JTDI

SysAD7

VSS

143

SysAD27

195

VCC

SysCMD3

VCC

144

SysAD59

196

VSS

SysAD50

145

ColdReset*

197

SysAD47

VCC

ValidIn*

146

SysAD28

198

SysAD15

SysAD38

SysAD19

147

VCC

199

JTDO

SysAD6

SysAD51

148

VSS

200

SysAD46

ModeClock

VSS

149

SysAD60

201

VCC

WrRdy*

VCC

150

Reset*

202

VSS

SysAD37

ValidOut*

151

SysAD29

203

SysAD14

SysAD5

100

SysAD20

152

SysAD61

204

N.C.

VSS

101

SysAD52

153

VCC

205

TClock0

VCC

102

ExtRqst*

154

VSS

206

TClock1

N.C.

103

N.C.

155

N.C.

207

N.C.

104

N.C.

156

N.C.

208

N.C.

22 of 25

April 10, 2001

IDT79R4700

RC4700 PGA Package Pin-Out

Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.

Function

ColdReset*

T14

SysAD36

VCC

B18

ExtRqst*

SysAD37

VCC

Fault*

B16

SysAD38

VCC

D18

Reserved O (NC)

U10

SysAD39

VCC

Reserved I (Vcc)

SysAD40

C10

VCC

G18

IOIn

T13

SysAD41

C11

VCC

IOOut

U12

SysAD42

B13

VCC

J18

Int0

SysAD43

A15

VCC

Int1

SysAD44

C15

VCC

L18

Int2

SysAD45

B17

VCC

Int3

SysAD46

E17

VCC

N18

Int4

SysAD47

F17

VCC

Int5

SysAD48

VCC

T18

MasterClock

J17

SysAD49

VCC

MasterOut

P17

SysAD50

VCC

ModeClock

SysAD51

VCC

ModeIn

SysAD52

VCC

NMI

SysAD53

VCC

V10

RClock0

T17

SysAD54

VCC

V12

RClock1

R16

SysAD55

VCC

V14

RdRdy*

SysAD56

T10

VCC

V17

Release

SysAD57

T11

VSS

Reset*

U16

SysAD58

U13

VSS

SyncIn

J16

SysAD59

V15

VSS

SyncOut

P16

SysAD60

T15

VSS

A10

SysAD0

SysAD61

U17

VSS

A12

SysAD1

SysAD62

N16

VSS

A14

SysAD2

SysAD63

N17

VSS

A17

SysAD3

SysADC0

VSS

A18

SysAD4

SysADC1

G17

VSS

SysAD5

SysADC2

VSS

C18

SysAD6

SysADC3

L16

VSS

SysAD7

SysADC4

VSS

F18

SysAD8

SysADC5

H16

VSS

SysAD9

B11

SysADC6

VSS

H18

SysAD10

C12

SysADC7

L17

VSS

SysAD11

B14

SysCmd0

VSS

K18

SysAD12

B15

SysCmd1

VSS

SysAD13

C16

SysCmd2

VSS

M18

SysAD14

D17

SysCmd3

VSS

SysAD15

E18

SysCmd4

VSS

P18

SysAD16

SysCmd5

VSS

R18

SysAD17

SysCmd6

B10

VSS

SysAD18

SysCmd7

B12

VSS

U18

SysAD19

SysCmd8

C13

VSS

SysAD20

SysCmdP

C14

VSS

Part Number IDT79R4700

Document Outline