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2001 Integrated Device Technology, Inc.

DSC-4512/1

APRIL 2001

3.3 VOLT CMOS SuperSync FIFOTM
32,768 X 18
65,536 X 18

IDT72V275
IDT72V285

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

.EATURES:

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Choose among the following memory organizations:

IDT72V275

32,768 x 18

IDT72V285

65,536 x 18

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Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs

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10ns read/write cycle time (6.5ns access time)

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Fixed, low first word data latency time

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Auto power down minimizes standby power consumption

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Master Reset clears entire FIFO

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Partial Reset clears data, but retains programmable
settings

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Retransmit operation with fixed, low first word data
latency time

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Empty, Full and Half-Full flags signal FIFO status

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Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets

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Program partial flags by either serial or parallel means

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Select IDT Standard timing (using

EF and FF

FF flags) or First Word

Fall Through timing (using

OR and IR

IR flags)

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Output enable puts data outputs into high impedance state

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Easily expandable in depth and width

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Independent Read and Write clocks (permit reading and writing
simultaneously)

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Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin

Slim Thin Quad Flat Pack (STQFP)

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High-performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

DESCRIPTION:

The IDT72V275/72V285 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:

The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs, RCLK
or WCLK, is running at the higher frequency.

The period required by the retransmit operation is now fixed and short.

The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period
found on previous SuperSync devices has been eliminated on this
SuperSync family.)

SuperSync FIFOs are particularly appropriate for network, video, telecom-
munications, data communications and other applications that need to buffer
large amounts of data.

.UNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

32,768 x 18
65,536 x 18

FLAG

LOGIC

PAF

PAE

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN

WCLK

-D

MRS

REN

RCLK

-Q

OFFSET REGISTER

PRS

FWFT/SI

SEN

4512 drw 01

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

PIN CON.IGURATIONS

TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)

TOP VIEW

DESCRIPTION (Continued)

PIN 1

WEN

SEN

(1)

GND

D17

D16

D15

D14

D13

D12

D11

D10

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q17

Q16

GND

Q15

Q14

Q13

Q12

Q11

GND

Q10

GND

WCLK

PRS

MRS

FWFT/SI

GND

PAF

PAE

RCLK

REN

GND

4512 drw 02

The input port is controlled by a Write Clock (WCLK) input and a Write Enable

(

WEN) input. Data is written into the FIFO on every rising edge of WCLK when

WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (

REN) input. Data is read from the FIFO on every rising

edge of RCLK when

REN is asserted. An Output Enable (OE) input is provided

for three-state control of the outputs.

The frequencies of both the RCLK and the WCLK signals may vary from 0

to f

MAX

with complete independence. There are no restrictions on the frequency

of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT

Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear

on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating

REN and enabling a rising RCLK edge,

will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly

to the data output lines after three transitions of the RCLK signal. A

REN does

not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on

REN for access. The state of

the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO

can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.

NOTE:
1. DC = Don't Care. Must be tied to GND or V

, cannot be left open.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

DESCRIPTION (Continued)

Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO

DATA OUT (Q

- Q

)

DATA IN (D

- D

)

MASTER RESET (

MRS

)

READ CLOCK (RCLK)

READ ENABLE (

REN

)

OUTPUT ENABLE (

)

EMPTY FLAG/OUTPUT READY (

)

PROGRAMMABLE ALMOST-EMPTY (

PAE

)

WRITE CLOCK (WCLK)

WRITE ENABLE (

WEN

)

LOAD (

)

FULL FLAG/INPUT READY (

)

PROGRAMMABLE ALMOST-FULL (

PAF

)

IDT

72V275
72V285

PARTIAL RESET (

PRS

)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

RETRANSMIT (

)

4512 drw 03

HALF-FULL FLAG (

)

SERIAL ENABLE(

SEN

)

These FIFOs have five flag pins,

EF/OR (Empty Flag or Output Ready),

FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and

PAF (Programmable Almost-Full flag). The EF and

FF functions are selected in IDT Standard mode. The IR and OR functions
are selected in FWFT mode.

HF, PAE and PAF are always available for

use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point

in memory. (See Table 1 and Table 2.) Programmable offsets determine the
flag switching threshold and can be loaded by two methods: parallel or serial.
Two default offset settings are also provided, so that

PAE can be set to switch

at 127 or 1,023 locations from the empty boundary and the

PAF threshold can

be set at 127 or 1,023 locations from the full boundary. These choices are made
with the

LD pin during Master Reset

For serial programming,

SEN together with LD on each rising edge of

WCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming,

WEN together with LD on each rising edge of WCLK, are used

to load the offset registers via D

REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Q

regardless of whether

serial or parallel offset loading has been selected.

During Master Reset (

MRS) the following events occur: The read and write

pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The

LD pin selects either a partial flag default

setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.

The Partial Reset (

PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode, partial flag programming
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect.

PRS is useful for resetting a device in mid-operation, when

reprogramming partial flags would be undesirable.

The Retransmit function allows data to be reread from the FIFO more than

once. A LOW on the

RT input during a rising RCLK edge initiates a retransmit

operation by setting the read pointer to the first location of the memory array.

If, at any time, the FIFO is not actively performing an operation, the chip will

automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.

The IDT72V275/72V285 are fabricated using IDT's high speed submicron

CMOS technology.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

PIN DESCRIPTION

Symbol

Name

I/O

Description

Data Inputs

Data inputs for a 18-bit bus.

MRS

Master Reset

MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.

PRS

Partial Reset

PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.

Retransmit

RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the

EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb

the write pointer, programming method, existing timing mode or programmable flag
settings.

RT is useful to reread data from the first physical location of the FIFO.

FWFT/SI

First Word Fall

During Master Reset, selects First Word Fall Through or IDT Standard mode.

Through/Serial In

After Master Reset, this pin functions as a serial input for loading offset registers

WCLK

Write Clock

When enabled by

WEN, the rising edge of WCLK writes data into the FIFO and

offsets into the programmable registers for parallel programming, and when
enabled by

SEN, the rising edge of WCLK writes one bit of data into the

programmable register for serial programming.

WEN

Write Enable

WEN enables WCLK for writing data into the FIFO memory and offset registers.

RCLK

Read Clock

When enabled by

REN, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

REN

Read Enable

REN enables RCLK for reading data from the FIFO memory and offset registers.

Output Enable

OE controls the output impedance of Q

SEN

Serial Enable

SEN enables serial loading of programmable flag offsets.

Load

During Master Reset,

LD selects one of two partial flag default offsets (127 or 1,023

and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers

Don't Care

This pin must be tied to either V

or GND and must not toggle after Master

Reset.

FF/IR

Full Flag/

In the IDT Standard mode, the

FF function is selected. FF indicates whether or

Input Ready

not the FIFO memory is full. In the FWFT mode, the

IR function is selected. IR

indicates whether or not there is space available for writing to the FIFO memory.

EF/OR

Empty Flag/

In the IDT Standard mode, the

EF function is selected. EF indicates whether or

Output Ready

not the FIFO memory is empty. In FWFT mode, the

OR function is selected.

OR indicates whether or not there is valid data available at the outputs.

PAF

Programmable

PAF goes LOW if the number of words in the FIFO memory is more than

Almost-Full Flag

total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.

PAE

Programmable

PAE goes LOW if the number of words in the FIFO memory is less than offset n,

Almost-Empty Flag

which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.

Half-Full Flag

HF indicates whether the FIFO memory is more or less than half-full.

Data Outputs

Data outputs for an 18-bit bus.

Power

+3.3 Volt power supply pins.

GND

Ground

Ground pins.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72V275/72V285

Symbol

Rating

Commercial

Unit

TERM

Terminal Voltage

0.5 to +4.6

with respect to GND

STG

Storage

55 to +125

° C

Temperature

OUT

DC Output Current

50 to +50

NOTES:
1. With output deselected, (

2. Characterized values, not currently tested.

DC ELECTRICAL CHARACTERISTICS

(Commercial: V

= 3.3V ± 0.3V, T

= 0

C to +70

C; Industrial: V

CC =

3.3V

0.3V, TA = -40

C to +85

Symbol

Parameter

(1)

Conditions

Max.

Unit

(2)

Input

= 0V

Capacitance

OUT

(1,2)

Output

OUT

= 0V

Capacitance

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage(Com'l & Ind'l)

3.0

3.3

3.6

GND

Supply Voltage(Com'l & Ind'l)

Input High Voltage
(Com'l & Ind'l)

2.0

+ 0.5

(1)

Input Low Voltage
(Com'l & Ind'l)

0.8

Operating Temperature

Commercial

Operating Temperature

-40

Industrial

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

IDT72V275L
IDT72V285L

Com''l & Ind'l

(1)

CLK

= 10, 15, 20 ns

Symbol

Parameter

Min.

Max.

Unit

(2)

Input Leakage Current

µ A

(3)

Output Leakage Current

µA

Output Logic "1" Voltage, I

= 2 mA

2.4

Output Logic "0" Voltage, I

= 8 mA

0.4

CC1

(4,5,6)

Active Power Supply Current

CC2

(4,7)

Standby Current

NOTES

Industrial temperature range product for the 15ns is available as a standard device.

2. Measurements with 0.4

IH,

0.4

OUT

CC.

4. Tested with outputs open (I

OUT

= 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical I

CC1

= 11 + 1.65*f

+ 0.02*C

(in mA) with V

= 3.3V, t

= 25

C, f

= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f

/2, C

= capacitive load (in pF).

7. All Inputs = V

- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

ABSOLUTE MAXIMUM RATINGS

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING

CONDITIONS

CAPACITANCE

= +25

C, f = 1.0MHz)

Part Number IDT72V285