1
DECEMBER 2003
DSC-5995/8
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5 VOLT HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION
16,384 x 40, 32,768 x 40,
65,536 x 40, 131,072 x 40
IDT72T4088, IDT72T4098
IDT72T40108, IDT72T40118
FEATURES
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·
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·
·
Choose among the following memory organizations:
IDT72T4088
16,384 x 40
IDT72T4098
32,768 x 40
IDT72T40108
65,536 x 40
IDT72T40118
131,072 x 40
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Up to 250MHz Operation of Clocks
- 4ns read/write cycle time, 3.2ns access time
·
Users selectable input port to output port data rates, 500Mb/s
Data Rate
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
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User selectable HSTL or LVTTL I/Os
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Read Enable & Read Clock Echo outputs aid high speed operation
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2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
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·
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3.3V Input tolerant
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Mark & Retransmit, resets read pointer to user marked position
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Write Chip Select (
WCS) input enables/disables Write
Operations
·
Read Chip Select (
RCS) synchronous to RCLK
·
Programmable Almost-Empty and Almost-Full flags, each flag
FUNCTIONAL BLOCK DIAGRAM
can default to one of four preselected offsets
·
Dedicated serial clock input for serial programming of flag offsets
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User selectable input and output port bus sizing
-x40 in to x40 out
-x40 in to x20 out
-x40 in to x10 out
-x20 in to x40 out
-x10 in to x40 out
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Auto power down minimizes standby power consumption
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Master Reset clears entire FIFO
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Partial Reset clears data, but retains programmable settings
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Empty and Full flags signal FIFO status
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Select IDT Standard timing (using
EF and FF flags) or First
Word Fall Through timing (using
OR and IR flags)
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Output enable puts data outputs into High-Impedance state
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JTAG port, provided for Boundary Scan function
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208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
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Easily expandable in depth and width
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Independent Read and Write Clocks (permit reading and writing
simultaneously)
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High-performance submicron CMOS technology
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Industrial temperature range (-40
°°
°°
°C to +85°°°°°C) is available
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
16,384 x 40,
32,768 x 40
65,536 x 40
131,072 x 40
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D
0
-D
n
(x40, x20, x10)
SREN
MRS
REN
RCLK
OE
Q
0
-Q
n
(x40, x20, x10)
OFFSET REGISTER
PRS
FWFT
SEN
RT
5995 drw01
BUS
CONFIGURATION
OW
FSEL0
FSEL1
IW
MARK
SCLK
RCS
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TMS
TDO
TDI
TRST
RSDR
WCS
ERCLK
EREN
HSTL I/0
CONTROL
Vref
HSTL
BM
WSDR
SI
SO
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
DESCRIPTION
The IDT72T4088/72T4098/72T40108/72T40118 are exceptionally deep,
extremely high speed, CMOS First-In-First-Out (FIFO) memories with the ability
to read and write data on both rising and falling edges of clock. The device has
a flexible x40/x20/x10 Bus-Matching mode and the option to select single or
double data rates for input and output ports. These FIFOs offer several key user
benefits:
·
Flexible x40/x20/x10 Bus-Matching on both read and write ports
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Ability to read and write on both rising and falling edges of a clock
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User selectable Single or Double Data Rate of input and output ports
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A user selectable MARK location for retransmit
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User selectable I/O structure for HSTL or LVTTL
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The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is fixed and short.
·
High density offerings up to 5Mbit
·
High speed operation of up to 250MHz
Bus-Matching Double Data Rate FIFOs are particularly appropriate for
network, video, telecommunications, data communications and other applica-
tions that require fast data transfer on both rising and falling edges of the clock.
This is a great alternative to increasing data rate without extending the width of
the bus or the speed of the device. They are also effective in applications that
need to buffer large amounts of data and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 40-bit, 20-bit, or a 10-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(
WEN) input. Data present on the Dn data inputs can be written into the FIFO
on every rising and falling edge of WCLK when
WEN is asserted and Write
Single Data Rate (
WSDR) pin held HIGH. Data can be selected to write only
on the rising edges of WCLK if
WSDR is asserted. To guarantee functionality
of the device,
WEN must be a controlled signal and not tied to ground. This is
important because
WEN must be HIGH during the time when the Master Reset
(
MRS) pulse is LOW. In addition, the WSDR pin must be tied HIGH or LOW.
It is not a controlled signal and cannot be changed during FIFO operation.
Write operations can be selected for either Single or Double Data Rate mode.
For Single Data Rate operation, writing into the FIFO requires the Write Single
Data Rate (
WSDR) pin to be asserted. Data will be written into the FIFO on the
rising edge of WCLK when the Write Enable (
WEN) is asserted. For Double
Data Rate operations, writing into the FIFO requires
WSDR to be deasserted.
Data will be written into the FIFO on both rising and falling edge of WCLK when
WEN is asserted.
The output port is controlled by a Read Clock (RCLK) input and a Read
Enable (
REN) input. Data is read from the FIFO on every rising and falling edge
of RCLK when
REN is asserted and Read Single Data Rate (RSDR) pin held
HIGH. Data can be selected to read only on the rising edges of RCLK if
RSDR
is asserted. To guarantee functionality of the device,
REN must be a controlled
signal and not tied to ground. This is important because
REN must be HIGH
during the time when the Master Reset (
MRS) pulse is LOW. In addition, the
RSDR pin must be tied HIGH or LOW. It is not a controlled signal and cannot
be changed during FIFO operation.
Read operations can be selected for either Single or Double Data Rate mode.
Similar to the write operations, reading from the FIFO in single data rate requires
the Read Single Data Rate (
RSDR) pin to be asserted. Data will be read from
the FIFO on the rising edge of RCLK when the Read Enable (
REN) is asserted.
For Double Data Rate operations, reading into the FIFO requires
RSDR to be
deasserted. Data will be read out of the FIFO on both rising and falling edge
of RCLK when and
REN is asserted.
Both the input and output port can be selected for either 2.5V LVTTL or HSTL
operation. This can be achieved by tying the HSTL signal LOW for LVTTL or
HIGH for HSTL voltage operation. When the read port is setup for HSTL mode,
the Read Chip Select (
RCS) input also has the benefit of disabling the read port
inputs, providing additional power savings.
There is the option of selecting different data rates on the input and output ports
of the device. There are a total of four combinations to choose from, Double Data
Rate to Double Data Rate (DDR to DDR), DDR to Single Data Rate (DDR to
SDR), SDR to DDR, and SDR to SDR. The rates can be set up using the
WSDR
and
RSDR pins. For example, to set up the input to output combination of DDR
to SDR,
WSDR will be HIGH and RSDR will be LOW. Read and write operations
are initiated on the rising edge of RCLK and WCLK respectively, never on the
falling edge. If
REN or WEN is asserted after a rising edge of clock, no read or
write operations will be possible on the falling edge of that same pulse.
An Output Enable (
OE) input is provided for high-impedance control of the
outputs. A read Chip Select (
RCS) input is also provided for synchronous
enable/disable of the read port control input,
REN. The RCS input is synchro-
nized to the read clock, and also provides high-impedance controls to the Qn
data outputs. When
RCS is disabled, REN will be disabled internally and the
data outputs will be in High-Impedance. Unlike the Read Chip Select signal
however,
OE is not synchronous to RCLK. Outputs are high-impedanced
shortly after a delay time when the
OE transitions from LOW to HIGH.
The Echo Read Enable (
EREN) and Echo Read Clock (ERCLK) outputs
are used to provide tighter synchronization between the data being transmitted
from the Qn outputs and the data being received by the input device. These
output signals from the read port are required for high-speed data communi-
cations. Data read from the read port is available on the output bus with respect
to
EREN and ERCLK, which is useful when data is being read at high-speed
operations where synchronization is important.
The frequencies of both the RCLK and WCLK signals may vary from 0 to fMAX
with complete independence. There are no restrictions on the frequency of one
clock input with respect to another.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines. Be aware that
in Double Data Rate (DDR) mode only the IDT Standard mode is available.
In FWFT mode, the first word written to an empty FIFO is clocked directly to
the data output lines after three transitions of RCLK. A read operation does not
have to be performed to access the first word written to the FIFO. However,
subsequent words written to the FIFO do require a LOW on
REN for access.
The state of the FWFT input during Master Reset determines the timing mode
in use.
For applications requiring more data storage capacity than a single FIFO can
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have four flag pins,
EF/OR (Empty Flag or Output Ready), FF/
IR (Full Flag or Input Ready), PAE (Programmable Almost-Empty flag), and
PAF (Programmable Almost-Full flag). The EF and FF functions are selected
in IDT Standard mode. The
IR and OR functions are selected in FWFT mode.
PAE and PAF are always available for use, irrespective of timing mode.
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
DESCRIPTION (CONTINUED)
PAE and PAF flags can be programmed independently to switch at any point
in memory. Programmable offsets mark the location within the internal memory
that activates the
PAE and PAF flags and can only be programmed serially. To
program the offsets, set
SEN active and data can be loaded via the Serial Input
(SI) pin at the rising edge of SCLK. To read out the offset registers serially, set
SREN active and data can be read out via the Serial Output (SO) pin at the rising
edge of SCLK. Four default offset settings are also provided, so that
PAE can
be marked at a predefined number of locations from the empty boundary and
the
PAF threshold can also be marked at similar predefined values from the full
boundary. The default offset values are set during Master Reset by the state
of the FSEL0 and FSEL1 pins.
During Master Reset (
MRS), the following events occur: the read and write
pointers are set to the first location of the internal FIFO memory, the FWFT pin
selects IDT Standard mode or FWFT mode, the bus width configuration of the
read and write port is determined by the state of IW and OW, and the default offset
values for the programmable flags are set.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode and the values stored in the
programmable offset registers before Partial Reset remain unchanged. The
flags are updated according to the timing mode and offsets in effect.
PRS is useful
for resetting a device in mid-operation, when reprogramming programmable
flags would be undesirable.
The timing of the
PAE and PAF flags are synchronous to RCLK and WCLK,
respectively. The
PAE flag is asserted upon the rising edge of RCLK only and
not WCLK. Similarly the
PAF is asserted and updated on the rising edge of
WCLK only and not RCLK.
This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and
RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at the point will be marked. Any
subsequent retransmit operation (when
RT goes LOW), will reset the read
pointer to this "marked" location.
The device can be configured with different input and output bus widths as
previously stated. These rates are: x40 to x40, x40 to x20,x40 to x10, x20 to
x40, and x10 to x40.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
A JTAG test port is provided, here the FIFO has fully functional boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The Double Data Rate FIFO has the capability of operating in either LVTTL
or HSTL mode. HSTL mode can be selected by enabling the HSTL pin. Both
input and output ports will operate in either HSTL or LVTTL mode, but cannot
be selected independent of one another.
The IDT72T4088/72T4098/72T40108/72T40118 are fabricated using
IDT's high-speed submicron CMOS technology.
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