Integrated Device Technology, Inc.

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

SEPTEMBER 1997

1997 Integrated Device Technology, Inc.

DSC-2679/7

IDT7200L

IDT7201LA
IDT7202LA

CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9, 1,024 x 9

The IDT logo is a trademark of Integrated Device Technology, Inc.

FEATURES:

First-In/First-Out dual-port memory

256 x 9 organization (IDT7200)

512 x 9 organization (IDT7201)

1,024 x 9 organization (IDT7202)

Low power consumption
-- Active: 770mW (max.)
--Power-down: 2.75mW (max.)

Ultra high speed--12ns access time

Asynchronous and simultaneous read and write

Fully expandable by both word depth and/or bit width

Pin and functionally compatible with 720X family

Status Flags: Empty, Half-Full, Full

Auto-retransmit capability

High-performance CEMOS

technology

Military product compliant to MIL-STD-883, Class B

Standard Military Drawing #5962-87531, 5962-89666,
5962-89863 and 5962-89536 are listed on this function

Industrial temperature range (40

C to +85

C) is

available (plastic packages only)

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT7200/7201/7202 are dual-port memories that load

and empty data on a first-in/first-out basis. The devices use
Full and Empty flags to prevent data overflow and underflow
and expansion logic to allow for unlimited expansion capability
in both word size and depth.

The reads and writes are internally sequential through the

use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (

) and Read (

) pins.

The devices utilize a 9-bit wide data array to allow for

control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (

) capability

that allows for reset of the read pointer to its initial position
when

is pulsed low to allow for retransmission from the

beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.

These FIFOs are fabricated using IDT's high-speed CMOS

technology. They are designed for those applications requir-
ing asynchronous and simultaneous read/writes in multiproc-
essing and rate buffer applications. Military grade product is
manufactured in compliance with the latest revision of MIL-
STD-883, Class B.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

WRITE

CONTROL

READ

CONTROL

FLAG

LOGIC

EXPANSION

LOGIC

WRITE

POINTER

RAM

ARRAY

256 x 9
512 x 9

1,024 x 9

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-
STATE
BUFFERS

DATA OUTPUTS

(D D

)

(Q Q

)

2679 drw 01

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

GND

2679 drw 02a

Reference

Order

Identifier

Code

PLASTIC DIP

(1)

P28-1

PLASTIC THIN DIP

P28-2

CERDIP

(1)

D28-1

THIN CERDIP

D28-3

SOIC

SO28-3

CERPAK

(1)

E28-2

TOP VIEW

CAPACITANCE

= +25

C, f = 1.0 MHz)

Symbol

Parameter

(1)

Condition

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

NOTE:

2679 tbl 02

1. This parameter is sampled and not 100% tested.

RS
EF
XO

32 31 30

14 15 16 17 18 19 20

GND

INDEX

2679 drw 02b

Reference

Order

Identifier

Code

LCC

(1)

L32- 1

PLCC

J32-1

TOP VIEW

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

Com'l & Ind'l

Mil.

Unit

TERM

Terminal Voltage

0.5 to +7.0

with Respect
to GND

STG

Storage

55 to +125

65 to +155

Temperature

OUT

DC Output

50 to +50

Current

NOTE:

2679 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.

RECOMMENDED OPERATING
CONDITIONS

Symbol

Parameter

Min.

Typ.

Max. Unit

CCM

Military Supply

4.5

5.0

5.5

Voltage

CCC

Commercial Supply

4.5

5.0

5.5

Voltage

GND

Supply Voltage

(1)

Input High Voltage

2.0

Commercial

(1)

Input High Voltage

2.2

Military

(2)

Input Low Voltage

0.8

Commercial and
Military

Operating Temperature

Commercial

Operating Temperature

Industrial

Operating Temperature

125

Military

NOTES:

2679 tbl 03

1. V

= 2.6V for

input (commercial).

= 2.8V for

input (military).

2. 1.5V undershoots are allowed for 10ns once per cycle.

NOTE:
1. The 600-mil-wide DIP (P28-1 and D28-1), CERPACK and LCC are not available for the 7200.

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(Commercial: V

= 5V

10%, T

= 0

C to +70

C; Industrial: V

= 5V

10%, T

= 40

C to +85

C; Military: V

= 5V

10%, T

= 55

C to +125

IDT7200L

IDT7201LA

IDT7202LA

Com'l & Ind'l

(1)

Military

= 12, 15, 20, 25, 35 ns

= 20, 30, 40 ns

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

(2)

Input Leakage Current (Any Input)

(3)

Output Leakage Current

Output Logic "1" Voltage I

= 2mA

2.4

Output Logic "0" Voltage I

= 8mA

0.4

CC1

(4,5,6)

Active Power Supply Current

125

140

CC2

(4,6,7)

Standby Current (

)

CC3

(L)

(4,6,7)

Power Down Current

0.5

0.9

2679 tbl 04

NOTES:

2679 tbl 05

1. Industrial temperature range product for the 25 ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4

, 0.4

OUT

4. Tested with outputs open (I

OUT

= 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. I

measurements are made with outputs open.

7. All Inputs = V

- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

IDT7200L

IDT7201LA

IDT7202LA

Commercial

Military

= 50 ns

= 50, 65, 80, 120 ns

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

(2)

Input Leakage Current (Any Input)

(3)

Output Leakage Current

Output Logic "1" Voltage I

= 2mA

2.4

Output Logic "0" Voltage I

= 8mA

0.4

CC1

(4,5,6)

Active Power Supply Current

100

CC2

(4,6,7)

Standby Current (

)

CC3

(L)

(4,6,7)

Power Down Current

0.5

0.9

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 1

2679 tbl 08

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: V

= 5V

10%, T

= 0

C to +70

C; Industrial: V

= 5V

10%, T

= 40

C to +85

C; Military: V

= 5V

10%, T

= 55

C to +125

Commercial

Com'l & Mil. Com'l & Ind'l

(2)

Military

Com'l

7200L12

7200L15

7200L20

7200L25

7200L30

7200L35

7201LA12 7201LA15

7201LA20

7201LA25

7201LA30 7201LA35

7202LA12 7202LA15

7202LA20

7202LA25

7202LA30 7202LA35

Symbol

Parameter

Min. Max. Min. Max.

Min.

Max.

Min.

Max.

Min. Max. Min. Max. Unit

Shift Frequency

33.3

28.5

22.2 MHz

Read Cycle Time

Access Time

Read Recovery Time

RPW

Read Pulse Width

(3)

RLZ

Read Pulse Low to Data Bus at Low Z

(4)

WLZ

Write Pulse High to Data Bus at Low Z

(4,5)

Data Valid from Read Pulse High

RHZ

Read Pulse High to Data Bus at High Z

(4)

Write Cycle Time

WPW

Write Pulse Width

(3)

Write Recovery Time

Data Set-up Time

Data Hold Time

RSC

Reset Cycle Time

Reset Pulse Width

(3)

RSS

Reset Set-up Time

(4)

RSR

Reset Recovery Time

RTC

Retransmit Cycle Time

Retransmit Pulse Width

(3)

RTS

Retransmit Set-up Time

(4)

RTR

Retransmit Recovery Time

EFL

Reset to Empty Flag Low

HFH,FFH

Reset to Half-Full and Full Flag High

RTF

Retransmit Low to Flags Valid

REF

Read Low to Empty Flag Low

RFF

Read High to Full Flag High

RPE

Read Pulse Width after

High

WEF

Write High to Empty Flag High

WFF

Write Low to Full Flag Low

WHF

Write Low to Half-Full Flag Low

RHF

Read High to Half-Full Flag High

WPF

Write Pulse Width after

High

XOL

Read/Write to

Low

XOH

Read/Write to

High

Pulse Width

(3)

XIR

Recovery Time

XIS

Set-up Time

NOTES:

2679 tbl 06

1. Timings referenced as in AC Test Conditions.

3. Pulse widths less than minimum value are not allowed.

2. Industrial temperature range is available by special order for

4. Values guaranteed by design, not currently tested.

speed grades faster than 25ns.

5. Only applies to read data flow-through mode.

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Continued)

(Commercial: V

= 5V

10%, T

= 0

C to +70

C; Industrial: V

= 5V

10%, T

= 40

C to +85

C; Military: V

= 5V

10%, T

= 55

C to +125

Military

Com'l & Mil.

Military

(2)

7200 L40

7200L50

7200L65

7200L80

7200L120

7201LA40

7201LA50

7201LA65

7201LA80

7201LA120

7202LA40

7202LA50

7202LA65

7202LA80

7202LA120

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Shift Frequency

12.5

MHz

Read Cycle Time

100

140

Access Time

120

Read Recovery Time

RPW

Read Pulse Width

(3)

120

RLZ

Read Pulse Low to Data Bus at Low Z

(4)

WLZ

Write Pulse High to Data Bus at Low Z

(4, 5)

Data Valid from Read Pulse High

RHZ

Read Pulse High to Data Bus at High Z

(4)

Write Cycle Time

100

140

WPW

Write Pulse Width

(3)

120

Write Recovery Time

Data Set-up Time

Data Hold Time

RSC

Reset Cycle Time

100

140

Reset Pulse Width

(3)

120

RSS

Reset Set-up Time

(4)

120

RSR

Reset Recovery Time

RTC

Retransmit Cycle Time

100

140

Retransmit Pulse Width

(3)

120

RTS

Retransmit Set-up Time

(4)

120

RTR

Retransmit Recovery Time

EFL

Reset to Empty Flag Low

100

140

HFH,FFH

Reset to Half-Full and Full Flag High

100

140

RTF

Retransmit Low to Flags Valid

100

140

REF

Read Low to Empty Flag Low

RFF

Read High to Full Flag High

RPE

Read Pulse Width after

High

120

WEF

Write High to Empty Flag High

WFF

Write Low to Full Flag Low

WHF

Write Low to Half-Full Flag Low

100

140

RHF

Read High to Half-Full Flag High

100

140

WPF

Write Pulse Width after

High

120

XOL

Read/Write to

Low

120

XOH

Read/Write to

High

120

Pulse Width

(3)

120

XIR

Recovery Time

XIS

Set-up Time

NOTES:

2679 tbl 07

1. Timings referenced as in AC Test Conditions

4. Values guaranteed by design, not currently tested.

2. Speed grades 65, 80 and 120 not available in the CERPACK

5. Only applies to read data flow-through mode.

3. Pulse widths less than minimum value are not allowed.

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

ongoing write operations. After Read Enable (

) goes high,

the Data Outputs (Q

) will return to a high impedance

condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (

) will go low,

allowing the "final" read cycle but inhibiting further read
operations with the data outputs remaining in a high imped-
ance state. Once a valid write operation has been accom-
plished, the Empty Flag (

) will go high after t

WEF

and a valid

Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from

so external changes in

will not

affect the FIFO when it is empty.

FIRST LOAD/RETRANSMIT (

)

This is a dual-purpose input. In the Depth Expansion Mode,

this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (

The IDT7200/7201A/7202A can be made to retransmit

data when the Retransmit Enable control (

) input is pulsed

low. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. Read
Enable (

) and Write Enable (

) must be in the high state

during retransmit. This feature is useful when less than 256/
512/1,024 writes are performed between resets. The retrans-
mit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (

), depending on the

relative locations of the read and write pointers.

EXPANSION IN (

)

This input is a dual-purpose pin. Expansion In (

) is

grounded to indicate an operation in the single device mode.
Expansion In (

) is connected to Expansion Out (

) of the

previous device in the Depth Expansion or Daisy Chain Mode.

OUTPUTS:

FULL FLAG (

)

The Full Flag (

) will go low, inhibiting further write

operation, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (

), the Full-Flag (

) will go

low after 256 writes for IDT7200, 512 writes for the IDT7201A
and 1,024 writes for the IDT7202A.

EMPTY FLAG (

)

The Empty Flag (

) will go low, inhibiting further read

operations, when the read pointer is equal to the write pointer,
indicating that the device is empty.

EXPANSION OUT/HALF-FULL FLAG (

)

This is a dual-purpose output. In the single device mode,

when Expansion In (

) is grounded, this output acts as an

indication of a half-full memory.

After half of the memory is filled and at the falling edge of

the next write operation, the Half-Full Flag (

) will be set low

and will remain set until the difference between the write

2679 drw 03

30pF*

1.1K

OUTPUT

680

or equivalent circuit

Figure 1. Output Load

* Includes scope and jig capacitances.

SIGNAL DESCRIPTIONS

INPUTS:

DATA IN (D

 D

)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (

)

Reset is accomplished whenever the Reset (

) input is

taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
Read Enable (

) and Write Enable (

) inputs must be in

the high state during the window shown in Figure 2, (i.e.,
t

RSS

before the rising edge of

) and should not change

until t

RSR

after the rising edge of

. Half-Full Flag (

)

will be reset to high after Reset (

WRITE ENABLE (

)

A write cycle is initiated on the falling edge of this input if the

Full Flag (

) is not set. Data set-up and hold times must be

adhered to with respect to the rising edge of the Write Enable
(

). Data is stored in the RAM array sequentially and

independently of any on-going read operation.

After half of the memory is filled and at the falling edge of

the next write operation, the Half-Full Flag (

) will be set to

low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (

) is then

reset by the rising edge of the read operation.

To prevent data overflow, the Full Flag (

) will go low,

inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (

) will go high after t

RFF

allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from

, so external changes

will not affect the FIFO when it is full.

READ ENABLE (

)

A read cycle is initiated on the falling edge of the Read

Enable (

) provided the Empty Flag (

) is not set. The data

is accessed on a First-In/First-Out basis, independent of any

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (

) is then

reset by using rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (

) is con-

nected to Expansion Out (

) of the previous device. This

output acts as a signal to the next device in the Daisy Chain

by providing a pulse to the next device when the previous
device reaches the last location of memory.

DATA OUTPUTS (Q

 Q

)

Data outputs for 9-bit wide data. This data is in a high

impedance condition whenever Read (

) is in a high state.

RSC

RSS

RSR

EFL

HFH

, t

FFH

2679 drw 04

NOTES:
1.

may change status during Reset, but flags will be valid at t

RSC

and

= V

around the rising edge of

Figure 2. Reset

LAST WRITE

IGNORED

WRITE

FIRST READ

ADDITIONAL

READS

FIRST

WRITE

WFF

RFF

2679 drw 06

Figure 4. Full Flag From Last Write to First Read

DATA OUT VALID

RPW

RLZ

RHZ

WPW

DATA IN VALID

2679 drw 05

Figure 3. Asynchronous Write and Read Operation

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

RHF

2679 drw 11

HALF-FULL OR LESS

MORE THAN HALF-FULL

HALF-FULL OR LESS

WHF

Figure 9. Half-Full Flag Timing

2679 drw 12

WRITE TO

LAST PHYSICAL

LOCATION

XOL

XOH

READ FROM

LAST PHYSICAL

LOCATION

XOL

XOH

Figure 10. Expansion Out

WRITE TO

FIRST PHYSICAL

LOCATION

XIS

READ FROM

FIRST PHYSICAL

LOCATION

XIS

XIR

2679 drw 13

Figure 11. Expansion In

OPERATING MODES:

Care must be taken to assure that the appropriate flag is

monitored by each system (i.e.

is monitored on the device

where

is used;

is monitored on the device where

used). For additional information, refer to Tech Note 8:

Oper-

ating FIFOs on Full and Empty Boundary Conditions

and

Tech Note 6:

Designing with FIFOs.

Single Device Mode

A single IDT7200/7201A/7202A may be used when the

application requirements are for 256/512/1,024 words or less.
These devices are in a Single Device Configuration when the
Expansion In (

) control input is grounded (see Figure 12).

Depth Expansion

The IDT7200/7201A/7202A can easily be adapted to appli-

cations when the requirements are for greater than 256/512/
1,024 words. Figure 14 demonstrates Depth Expansion using
three IDT7200/7201A/7202As. Any depth can be attained by

adding additional IDT7200/7201A/7202As. These FIFOs
operate in the Depth Expansion mode when the following
conditions are met:

1. The first device must be designated by grounding the First

Load (

) control input.

2. All other devices must have

in the high state.

3. The Expansion Out (

) pin of each device must be tied

to the Expansion In (

) pin of the next device. See Figure

14.

4. External logic is needed to generate a composite Full Flag

(

) and Empty Flag (

). This requires the ORing of all

s and ORing of all

s (i.e. all must be set to generate

the correct composite

). See Figure 14.

5. The Retransmit (

) function and Half-Full Flag (

) are

not available in the Depth Expansion Mode.

For additional information, refer to Tech Note 9:

Cascad-

ing FIFOs or FIFO Modules.

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the

corresponding input control signals of multiple devices. Sta-
tus flags (

and

) can be detected from any one

device. Figure 13 demonstrates an 18-bit word width by using
two IDT7200/7201A/7202As. Any word width can be attained
by adding additional IDT7200/7201A/7202As (Figure 13).

Bidirectional Operation

Applications which require data buffering between two

systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7200/7201A/7202As as shown
in Figure 16. Both Depth Expansion and Width Expansion
may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read

flow-through and write flow-through mode. For the read flow-
through mode (Figure 17), the FIFO permits a reading of a

single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (t

WEF

+ t

) ns after the rising

edge of

, called the first write edge, and it remains on the

bus until the

line is raised from low-to-high, after which the

bus would go into a three-state mode after t

RHZ

ns. The

line

would have a pulse showing temporary deassertion and then
would be asserted.

In the write flow-through mode (Figure 18), the FIFO

permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The

line causes

the

to be deasserted but the

line being low causes it to

be asserted again in anticipation of a new data word. On the
rising edge of

, the new word is loaded in the FIFO. The

line must be toggled when

is not asserted to write new data

in the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can be

applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).

IDT

7200/

7201A/

7202A

DATA

WRITE (

)

FULL FLAG (

)

RESET (

)

(D)

READ (

)

EMPTY FLAG (

)

RETRANSMIT (

)

DATA

(Q)

OUT

IDT

7200/

7201A/

7202A

Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode

WRITE (

)

DATA IN (D)

FULL FLAG (

)

RESET (

)

READ (

)

DATA OUT (Q)

EMPTY FLAG (

)

RETRANSMIT (

)

EXPANSION IN (

)

(

)

IDT

7200/

7201A/

7202A

(HALFFULL FLAG)

2679 drw 14

Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO

2679 drw 15

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

TABLE I--RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Reset

Location Zero

Retransmit

Location Zero

Unchanged

Read/Write

Increment

(1)

Increment

(1)

NOTE:

2679 tbl 09

1. Pointer will increment if flag is High.

Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion)

IDT

7200/

7201A/

7202A

FULL

EMPTY

IDT

7200/

7201A/

7202A

IDT

7200/

7201A/

7202A

TABLE II--RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Reset First Device

(1)

Location Zero

Reset All Other Devices

(1)

Location Zero

Read/Write

(1)

NOTE:

2679 tbl 10

is connected to

of previous device. See Figure 14.

= Reset Input,

= First Load/Retransmit,

= Empty Flag Output,

= Flag Full Output,

= Expansion Input,

= Half-Full Flag Output

2679 drw 16

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

IDT7200/

IDT7201A/

IDT7202A

DEPTH

EXPANSION

BLOCK

· · ·

-D

(N-8)

-D

(N-8)

-D

(N-8)

-Q

(N-8)

-Q

IDT7200/

IDT7201A/

IDT7202A

DEPTH

EXPANSION

BLOCK

IDT7200/

IDT7201A/

IDT7202A

DEPTH

EXPANSION

BLOCK

2679 drw 17

Figure 15. Compound FIFO Expansion

NOTES:
1. For depth expsansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.

Figure 17. Read Data Flow-Through Mode

DATA

RPE

DATA

OUT

WLZ

WEF

REF

DATA VALID

OUT

2679 drw 19

Figure 16. Bidirectional FIFO Mode

IDT

7201A

SYSTEM A

SYSTEM B

B 0-8

A 0-8

IDT

7200/

7201A/

7202A

A 0-8

IDT

7200/

7201A/

7202A

2679 drw 18

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

DATA

OUT

WFF

RFF

WPF

DATA

VALID

DATA

OUT

VALID

2679 drw 20

Figure 18. Write Data Flow-Through Mode

NOTES:
1. Industrial temperature range is available for plastic packages by special order for speed grades faster than 25 ns.
2. "A" to be included for 7201 and 7202 ordering part number.

IDT

XXXX

Device Type

XXX

Speed

Power

Package

Process/

Temperature

Range

Blank
I
B

7200
7201
7202

12
15
20
25
30
35
40
50
65
80
120

Commercial (0

C to +70

Industrial (40

C to +85

Military (55

C to +125

Compliant to MIL-STD-883, Class B

256 x 9-Bit FIFO
512 x 9-Bit FIFO
1,024 x 9-Bit FIFO

Commercial Only
Commercial Only

Commercial and Industrial
Military Only
Commercial Only
Military Only

Low Power

P
TP
D
TD
J
SO
L
XE

Plastic DIP
Plastic Thin DIP
CERDIP
Thin CERDIP
Plastic Leaded Chip Carrier
SOIC
Leadless Chip Carrier
CERPACK

Access Time (t

)

Speed in Nanoseconds

2679 drw 21

Military only--
except XE
package

Blank
I
B

(1)

P28-1
P28-2
D28-1
D28-3
J32-1
SO28-3
L32-1
E28-2

PLCC

LCC

(7201 & 7202 Only)

(7201 & 7202 Only)
(7201 & 7202 Only)

(2)

ORDERING INFORMATION

Part Number IDT7200L