Integrated
Circuit
Systems, Inc.
ICS9248- 143
Block Diagram
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM
II
/
III
TM
& K6
9248-143 Rev C 7/26/00
Pin Configuration
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
CLK_STOP#
PCI_STOP#
CPU2.5_3.3#
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK_F
CPUCLK [2:0]
SDRAM [7:0]
PCICLK [5:0]
PCICLK_F
PCICLK_E
SDRAM_F
X1
X2
BUFFER IN
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
STOP
SDATA
SCLK
PD#
FS(0:3)
SEL24_48#
Control
Logic
Config.
Reg.
/ 2
REF[1:0]
LATCH
POR
2
3
8
6
4
4
VDDREF
*SPREAD/REF0
GNDREF
X1
X2
VDDPCI
*CPU2.5_3.3#/PCICLK_F
*FS3/PCICLK0
GNDPCI
*SEL24_48#/PCICLK1
*SELPCIE_6#/PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GNDPCI
PCICLK5
PCICLK6/
VDDCOR
PCI_STOP#
*PD#
GND48
SDATA
SCLK
PCICLK_E
REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*
ICS9248-143
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Recommended Application:
440BX, MX, VIA Apollo Pro 133, Apollo Pro Media
or MVP4 style chip set, for Note book applications.
Output Features:
4 - CPUs @ 2.5V/3.3V
including 1 free running CPUCLK_F
9 - SDRAM @ 3.3V
7 - PCI @ 3.3V, including 1 free running PCICLK_F
1 - PCI Early @ 3.3V
1 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Up to 137MHz frequency support
97MHz to support high-end AMD processor.
Support power management: CLK, PCI, stop and Power
down Mode from I
2
C programming.
Spread spectrum for EMI control
(±.25% & 0 to -0.5% down spread).
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU Output Jitter @ 2.5V: <300ps
CPU Output Jitter @ 3.3V: <250ps
PCI Output Jitter @ 3.3V: <250ps
CPU Output Skew @ 2.5V: <175ps
CPU Output Skew @ 3.3V: <175ps
PCI Output Skew @ 3.3V: <500ps
PCI Early to PCI Skew @ 3.3V: typ = 3ns
Functionality
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ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
3
ICS9248-143
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Notes:
1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011.
2, PWD = Power-Up Default
The ICS9248-143 is the single chip clock solution for Notebook designs using thE 440BX, MX, VIA Apollo Pro 133, Apollo Pro
Media or MVP4 style chip set. It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-143 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
General Description
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4
ICS9248-143
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
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Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
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Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
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5
ICS9248-143
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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