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Part Number ICS9248yF-90-T

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Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9248-90
Block Diagram
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9248-90 Rev C 4/19/00
Pin Configuration
·
3.3V outputs: SDRAM, PCI, REF, 48/24MHz
·
2.5V outputs: CPU, IOAPIC
·
20 ohm CPU clock output impedance
·
20 ohm PCI clock output impedance
·
Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.
·
No external load cap for C
L
=18pF crystals
·
±175 ps CPU clock skew
·
250ps (cycle to cycle) CPU jitter
·
Smooth frequency switch, with selections from 66.8
to 133 MHz CPU.
·
I
2
C interface for programming
·
3ms power up clock stable time
·
Clock duty cycle 45-55%.
·
48 pin 300 mil SSOP package
·
3.3V operation, 5V tolerant inputs (with series R)
·
<5ns propagation delay SDRAM from Buffer Input
48-Pin SSOP
Power Groups
VDDREF = REF (0:1), X1, X2
VDDPCI = PCICLK_F, PCICLK(0:4)
VDDSDR = SDRAM (0:12), supply for PLL core
VDD48 = 24MHz, 48MHz
VDDLIOAPIC = IOAPIC
VDDLCPU = CPUCLK 1, CPUCLK_F
* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND
The ICS9248-90 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
Features include two CPU, six PCI and thirteen SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.25% modulation to reduce the EMI.
Serial programming I
2
C interface allows changing functions,
stop clock programing and Frequency selection. Additionally,
the device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up. It is not recommended to use I/O dual function pin
for the slots (ISA, PIC, CPU, DIMM). The add on card might
have a pull up or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF and 24 and
48 MHz clock outputs typically provide better than 0.5V/ns
slew rates into 20pF.
CPU_STOP#
PCI_STOP#
PLL2
PLL1
Spread
Spectrum
48MHz
24MHz
IOAPIC
CPUCLK_F
CPUCLK 1
SDRAM (0:11)
PCICLK (0:4)
PCICLKF
SDRAM_F
X1
X2
BUFFER IN
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
STOP
STOP
SDATA
SCLK
FS(0:3)
MODE
Control
Logic
Config.
Reg.
/2
REF(0:1)
LATCH
POR
2
12
5
4
4
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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2
ICS9248-90
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
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3
ICS9248- 90
Functionality
V
DD
= 3.3V±5%, V
DDL
= 2.5V±5% TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
Mode Pin - Power Management Input Control
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0
0
0
1
7
0
.
3
9
2
0
.
1
3
1
0
0
1
0
0
0
.
4
9
3
3
.
1
3
1
0
0
1
1
0
0
.
5
9
6
6
.
1
3
1
0
1
0
0
0
0
.
6
9
9
9
.
1
3
1
0
1
0
1
1
0
.
7
9
3
3
.
2
3
1
0
1
1
0
1
0
.
8
9
7
6
.
2
3
1
0
1
1
1
9
9
.
8
9
9
9
.
2
3
1
1
0
0
0
3
2
.
0
0
1
1
4
.
3
3
1
1
0
0
1
2
0
.
2
0
1
1
0
.
4
3
1
1
0
1
0
0
0
.
4
0
1
6
6
.
4
3
1
1
0
1
1
0
0
.
6
0
1
3
3
.
5
3
1
1
1
0
0
1
0
.
8
0
1
0
0
.
6
3
1
1
1
0
1
9
9
.
9
0
1
6
6
.
6
3
1
1
1
1
0
0
0
.
4
2
1
9
9
.
0
3
1
1
1
1
1
9
9
.
2
3
1
5
2
.
3
3
background image
4
ICS9248-90
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
t
i
B
n
o
i
t
p
i
r
c
s
e
D
D
W
P
t
i
B
)
4
:
7
,
2
(
)
4
:
7
,
2
(
t
i
B
K
L
C
U
P
C
z
H
M
K
L
C
I
C
P
z
H
M
X
X
X
1
e
t
o
N
0
0
0
0
0
2
8
.
6
6
0
4
.
3
3
0
0
0
0
1
1
0
.
8
6
0
0
.
4
3
0
0
0
1
0
9
9
.
1
7
9
9
.
5
3
0
0
0
1
1
0
0
.
5
7
9
4
.
7
3
0
0
1
0
0
0
0
.
8
7
9
9
.
8
3
0
0
1
0
1
0
0
.
0
8
9
9
.
9
3
0
0
1
1
0
0
0
.
2
8
0
0
.
1
4
0
0
1
1
1
0
0
.
3
8
0
5
.
1
4
0
1
0
0
0
0
0
.
4
8
9
9
.
1
4
0
1
0
0
1
1
0
.
5
8
0
5
.
2
4
0
1
0
1
0
1
9
.
5
8
5
9
.
2
4
0
1
0
1
1
9
9
.
6
8
9
4
.
3
4
0
1
1
0
0
0
0
.
8
8
9
9
.
3
4
0
1
1
0
1
1
0
.
9
8
0
5
.
4
4
0
1
1
1
0
0
0
.
0
9
9
9
.
4
4
0
1
1
1
1
9
9
.
0
9
9
4
.
5
4
1
0
0
0
0
9
9
.
1
9
6
6
.
0
3
1
0
0
0
1
7
0
.
3
9
2
0
.
1
3
1
0
0
1
0
0
0
.
4
9
3
3
.
1
3
1
0
0
1
1
0
0
.
5
9
6
6
.
1
3
1
0
1
0
0
0
0
.
6
9
9
9
.
1
3
1
0
1
0
1
1
0
.
7
9
3
3
.
2
3
1
0
1
1
0
1
0
.
8
9
7
6
.
2
3
1
0
1
1
1
9
9
.
8
9
9
9
.
2
3
1
1
0
0
0
3
2
.
0
0
1
1
4
.
3
3
1
1
0
0
1
2
0
.
2
0
1
1
0
.
4
3
1
1
0
1
0
0
0
.
4
0
1
6
6
.
4
3
1
1
0
1
1
0
0
.
6
0
1
3
3
.
5
3
1
1
1
0
0
1
0
.
8
0
1
0
0
.
6
3
1
1
1
0
1
9
9
.
9
0
1
6
6
.
6
3
1
1
1
1
0
0
0
.
4
2
1
9
9
.
0
3
1
1
1
1
1
9
9
.
2
3
1
5
2
.
3
3
3
t
i
B
s
t
u
p
n
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d
e
h
c
t
a
l
,
t
c
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r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
2
,
4
:
7
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
e
l
b
a
n
e
m
u
r
t
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e
p
s
d
a
e
r
p
S
-
1
1
0
t
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B
g
n
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R
-
0
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t
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t
s
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T
-
1
0
background image
5
ICS9248- 90
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
7
1
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
I
C
P
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
4
1
1
)
t
c
a
n
I
/
t
c
A
(
4
K
L
C
I
C
P
3
t
i
B
2
1
1
)
t
c
a
n
I
/
t
c
A
(
3
K
L
C
I
C
P
2
t
i
B
1
1
1
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
I
C
P
1
t
i
B
0
1
1
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
I
C
P
0
t
i
B
8
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
I
C
P
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
X
#
2
S
F
d
e
h
c
t
a
L
6
t
i
B
-
X
#
4
S
F
d
e
h
c
t
a
L
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
0
4
1
)
t
c
a
n
I
/
t
c
A
(
2
1
M
A
R
D
S
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
3
4
1
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
U
P
C
0
t
i
B
4
4
1
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
U
P
C
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
X
#
E
D
O
M
6
t
i
B
-
X
#
0
S
F
d
e
h
c
t
a
L
5
t
i
B
6
2
1
)
t
c
a
n
I
/
t
c
A
(
z
H
M
8
4
4
t
i
B
5
2
1
)
t
c
a
n
I
/
t
c
A
(
z
H
M
4
2
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
7
1
,
8
1
,
0
2
,
1
2
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
)
1
1
:
8
(
M
A
R
D
S
1
t
i
B
8
2
,
9
2
,
1
3
,
2
3
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
)
7
:
4
(
M
A
R
D
S
0
t
i
B
4
3
,
5
3
,
7
3
,
8
3
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
)
3
:
0
(
M
A
R
D
S