ICS9248-146
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Block Diagram
9248-146 RevA- 4/23/01
Recommended Application:
Single chip clock solution for SIS630S chipsets.
Output Features:
·
3- CPUs @ 2.5V
·
13 - SDRAM @ 3.3V
·
6- PCI @3.3V,
·
2 - AGP @ 3.3V
·
1- 48MHz, @3.3V fixed.
·
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
·
2- REF @3.3V, 14.318MHz.
Features:
·
Up to 166MHz frequency support
·
Support FS0-FS3 trapping status bit for I
2
C read back.
·
Support power management: CPU, PCI, SDRAM stops
and Power down Mode form I
2
C programming.
·
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
·
Uses external 14.318MHz crystal
Skew Specifications:
·
CPU - CPU: < 175ps
·
SDRAM - SDRAM < 250ps (except SDRAM12)
·
PCI - PCI: < 500ps
·
CPU (early) - PCI: 1-4ns (typ. 2ns)
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1
These are double strength.
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
VDDA
(AGPSEL)REF0
*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
1
*
VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
ICS9248-146
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
SDRAM (12:0)
PCICLK (4:0)
AGP (1:0)
PCICLK_F
2
5
13
3
2
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/ 2
REF(1:0)
AGP
DIVDER
0
0
0
0
66.67
66.67
33.33
66.67
50.00
0
0
0
1
100.00 100.00
33.33
66.67
50.00
0
0
1
0
166.67 166.67
33.33
66.66
55.56
0
0
1
1
133.33 133.33
33.33
66.67
50.00
0
1
0
0
66.67
100.00
33.33
66.67
50.00
0
1
0
1
100.00
66.67
33.33
66.67
50.00
0
1
1
0
100.00 133.33
33.33
66.67
50.00
0
1
1
1
133.33 100.00
33.33
66.67
50.00
1
0
0
0
112.00 112.00
33.60
67.20
56.00
1
0
0
1
124.00 124.00
31.00
62.00
46.50
1
0
1
0
138.00 138.00
34.50
69.00
51.75
1
0
1
1
150.00 150.00
30.00
60.00
50.00
1
1
0
0
66.67
133.33
33.33
66.67
50.00
1
1
0
1
100.00 150.00
30.00
60.00
50.00
1
1
1
0
150.00 100.00
30.00
60.00
50.00
1
1
1
1
160.00 120.00
30.00
60.00
48.00
FS3 FS2 FS1 FS0 CPU
SDRAM PCICLK
AGP SEL
= 0
AGP SEL
= 1
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248-146
Third party brands and names are the property of their respective owners.
The ICS9248-146 is the single chip clock solution for
Desktop/Notebook designs using the SIS 630S style chipset.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-146
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
General Description
Pin Configuration
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
E
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2
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1
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A
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9
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A
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8
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S
1
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A
R
D
S
#
D
P
MODE Pin Power Management Control Input
PIN N U MB ER
PIN N A ME
TY PE
D ES C R IPTION
1, 7, 15, 22, 25,
35, 43
V D D
P WR
3.3V P ow er supply for SD RA M output buffers, PCI output buffers,
reference output buffers and 48M H z output
A G P S EL
IN
A G P frequency select pin.
REF0
O U T
14.318 M H z reference clock.
F S3
IN
F requency select pin.
REF1
O U T
14.318 M H z reference clock.
4, 14, 18, 19, 29,
32, 39, 44
G N D
P WR
G round pin for 3V outputs.
5
X 1
IN
C rystal input,nominally 14.318M H z.
6
X 2
O U T
C rystal output, nominally 14.318M H z.
F S1
IN
F requency select pin.
PCIC LK _F
O U T
P CI clock output, not affected by P CI_STO P #
F S2
IN
F requency select pin.
PCIC LK 0
O U T
P CI clock output.
13, 12, 11, 10
PCICLK (4:1)
O U T
P CI clock outputs.
17, 16,
A G P (1:0)
O U T
A G P outputs defined as 2X PC I. These may not be stopped.
F S0
IN
F requency select pin.
48M H z
O U T
48M H z output clock
M O D E
IN
P in 27, 28, 30, & 31 function select pins
0=D esktop 1=M obile mode
24_48M H z
O U T
C lock output for super I/O /U S B default is 24M H z
23
SD A TA
I/O
D ata pin for I
2
C circuitry 5V tolerant
24
S CLK
IN
C lock pin of I
2
C circuitry 5V tolerant
CP U _S TO P #
IN
S tops all PCICLK s besides the PCICLK _F clocks at logic 0 level, w hen input
is low and M O D E pin is in M obile mode
SD RA M 11
O U T
S D RA M clock output
PCI_STO P #
IN
S tops all CPU CLK s clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
SD RA M 10
O U T
S D RA M clock output
S D R A M 9
O U T
S D RA M clock output
S D RA M _STO P #
IN
S tops all SD RA M clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
P D #
IN
A synchronous active low input pin used to pow er dow n the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the pow er dow n w ill not be greater than 3ms.
S D R A M 8
O U T
S D RA M clock output
26 33, 34, 36, 37,
38, 40, 41, 42
SD RA M (12, 7:0)
O U T
S D RA M clock outputs
45, 46, 47
CP U C LK (2:0)
O U T
C PU clock outputs.
48
V D D L
P WR
P ow er pin for the CP U CLK s. 2.5V
31
20
2
8
9
21
3
30
27
28
3
ICS9248-146
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I
2
C is a trademark of Philips Corporation
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r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
0
1
0
0
.
5
0
1
0
0
.
0
4
1
0
0
.
5
3
0
0
.
0
7
0
5
.
2
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
1
0
0
0
.
5
0
1
0
5
.
7
5
1
0
5
.
1
3
0
0
.
3
6
0
5
.
2
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
1
1
3
3
.
5
3
1
0
5
.
1
0
1
3
8
.
3
3
7
6
.
7
6
5
7
.
0
5
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
-
/
+
3
t
i
B
s
t
u
p
n
I
d
e
h
c
t
a
L
,t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
4
:
7
2
,
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
1
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
l
l
a
e
t
a
t
s
i
r
T
-
1
0
4
ICS9248-146
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
3
1
1
4
K
L
C
I
C
P
4
t
i
B
2
1
1
3
K
L
C
I
C
P
3
t
i
B
1
1
1
2
K
L
C
I
C
P
2
t
i
B
0
1
1
1
K
L
C
I
C
P
1
t
i
B
9
1
0
K
L
C
I
C
P
0
t
i
B
8
1
F
_
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
1
2
1
z
H
M
8
4
_
4
2
5
t
i
B
0
2
1
z
H
M
8
4
4
t
i
B
6
2
1
2
1
M
A
R
D
S
3
t
i
B
7
2
1
1
1
M
A
R
D
S
2
t
i
B
8
2
1
0
1
M
A
R
D
S
1
t
i
B
0
3
1
9
M
A
R
D
S
0
t
i
B
1
3
1
8
M
A
R
D
S
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
3
S
F
6
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
2
S
F
5
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
1
S
F
4
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
0
S
F
3
t
i
B
2
1
1
F
E
R
2
t
i
B
3
1
0
F
E
R
1
t
i
B
7
1
1
1
K
L
C
P
G
A
0
t
i
B
6
1
1
0
K
L
C
P
G
A
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
3
3
1
7
M
A
R
D
S
6
t
i
B
4
3
1
6
M
A
R
D
S
5
t
i
B
6
3
1
5
M
A
R
D
S
4
t
i
B
7
3
1
4
M
A
R
D
S
3
t
i
B
8
3
1
3
M
A
R
D
S
2
t
i
B
0
4
1
2
M
A
R
D
S
1
t
i
B
1
4
1
1
M
A
R
D
S
0
t
i
B
2
4
1
0
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
8
4
_
4
2
l
e
S
)
z
H
M
8
4
:
0
,
z
H
M
4
2
:
1
(
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
7
4
1
0
K
L
C
U
P
C
2
t
i
B
6
4
1
1
K
L
C
U
P
C
1
t
i
B
5
4
1
2
K
L
C
U
P
C
0
t
i
B
-
1
d
e
v
r
e
s
e
R
5
ICS9248-146
Third party brands and names are the property of their respective owners.
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
0
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
0
d
e
v
r
e
s
e
R
1
t
i
B
-
0
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
3
,
2
0
X
2
=
1
,
X
1
=
0
h
t
g
n
e
r
t
s
F
E
R
6
t
i
B
5
4
0
l
o
r
t
n
o
C
-
p
o
t
S
-
2
K
L
C
U
P
C
,
2
K
L
C
U
P
C
l
o
r
t
n
o
c
l
l
i
w
#
P
O
T
S
_
U
P
C
=
0
w
o
l
s
i
#
P
O
T
S
_
U
P
C
f
i
n
e
v
e
g
n
i
n
n
u
r
e
e
r
f
s
i
2
K
L
C
U
P
C
=
1
5
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
L
E
S
P
G
A
4
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
E
D
O
M
3
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
U
P
C
2
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
I
C
P
1
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
#
P
O
T
S
_
M
A
R
D
S
0
t
i
B
-
0
e
l
g
g
o
T
d
e
e
p
S
P
G
A
,
g
n
i
t
t
e
s
t
u
p
n
i
h
c
t
a
l
y
b
d
e
n
i
m
r
e
t
e
d
e
b
l
l
i
w
)
2
n
i
p
(
L
E
S
P
G
A
=
0
g
n
i
t
t
e
s
t
u
p
n
i
h
c
t
a
l
f
o
e
t
i
s
o
p
p
o
e
b
l
l
i
w
L
E
S
P
G
A
=
1
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