Integrated
Circuit
Systems, Inc.
ICS9248-141
Third party brands and names are the property of their respective owners.
Block Diagram
9248-141 Rev B 01/18/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KX133 style chipset
Output Features:
·
1 - Differential pair open drain CPU clocks
·
1 - Single-ended open drain CPU clock
·
13 - SDRAM @ 3.3V
·
6 - PCI @3.3V,
·
1 - 48MHz, @3.3V fixed.
·
1 - 24/48MHz @ 3.3V
·
2 - REF @3.3V, 14.318MHz.
Features:
·
Up to 166MHz frequency support
·
Support power management: CPU stop and Power down
Mode from I
2
C programming.
·
Spread spectrum for EMI control
(± 0.25% center spread).
·
Uses external 14.318MHz crystal
AMD - K7
TM
System Clock Chip
* Internal Pull-up Resistor of 120K to VDD
VDDREF
REF0/CPU_STOP#*
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDATA
SCLK
REF1/FS2*
GND
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24/48MHz/FS1*
ICS9248-141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL24_48#
BUFFER IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (11:0)
PCICLK (4:0)
PCICLK_F
SDRAM_OUT
CPUCLKT (1:0)
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
SDRAM
DRIVER
3
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ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
2
ICS9248-141
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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3
ICS9248-141
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-141 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks
required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-141
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
7
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Power Groups
VDD48 = 48MHz, PLL2
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
VDDPCI = PCI
VDDSDR = SDRAM
4
ICS9248-141
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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t
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e
C
%
5
2
.
0
±
0
0
1
0
1
0
0
.
3
0
1
3
3
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
0
1
1
0
0
0
.
5
0
1
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
0
1
1
1
0
0
.
0
0
1
3
3
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
0
0
0
0
0
.
7
0
1
7
6
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
0
0
1
0
0
.
9
0
1
3
3
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
0
1
0
0
0
.
0
1
1
7
6
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
0
1
1
0
0
.
1
1
1
0
0
.
7
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
1
0
0
0
0
.
3
1
1
7
6
.
7
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
1
0
1
0
0
.
5
1
1
3
3
.
8
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
1
1
0
0
0
.
7
1
1
0
0
.
9
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
0
1
1
1
1
0
3
.
3
3
1
3
3
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
0
0
0
0
0
.
0
2
1
0
0
.
0
4
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
0
0
1
0
0
.
5
2
1
5
2
.
1
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
0
1
0
0
0
.
0
3
1
0
5
.
2
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
0
1
1
3
7
.
3
3
1
3
4
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
1
0
0
0
0
.
5
3
1
5
7
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
1
0
1
0
0
.
7
3
1
5
2
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
1
1
0
0
0
.
9
3
1
5
7
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
0
1
1
1
0
0
.
0
0
1
3
3
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
0
0
0
0
0
.
0
4
1
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
0
0
1
0
0
.
3
4
1
5
7
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
0
1
0
0
0
.
5
4
1
5
2
.
6
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
0
1
1
0
0
.
8
4
1
0
0
.
7
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
1
0
0
0
0
.
0
5
1
0
5
.
7
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
1
0
1
0
0
.
5
5
1
5
7
.
8
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
1
1
0
6
6
.
6
6
1
7
6
.
1
4
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
1
1
1
1
1
3
3
.
3
3
1
3
3
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
3
t
i
B
s
t
u
p
n
I
d
e
h
c
t
a
L
,t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
4
:
7
,
2
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
1
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
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o
l
l
a
e
t
a
t
s
i
r
T
-
1
0
5
ICS9248-141
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
2
S
F
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
X
#
3
S
F
3
t
i
B
0
4
1
T
U
O
_
M
A
R
D
S
2
t
i
B
-
X
#
)
#
8
4
_
4
2
L
E
S
(
1
t
i
B
4
4
,
3
4
1
h
t
o
b
(
e
l
b
a
n
e
0
K
L
C
U
P
C
d
n
a
"
e
u
r
T
"
.
r
i
a
p
l
a
i
t
n
e
r
e
f
f
i
d
)
"
y
r
a
t
n
e
m
i
l
p
m
o
C
0
t
i
B
6
4
1
e
l
b
a
n
e
T
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
0
S
F
6
t
i
B
7
1
F
_
K
L
C
I
C
P
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
3
1
1
4
K
L
C
I
C
P
3
t
i
B
2
1
1
3
K
L
C
I
C
P
2
t
i
B
1
1
1
2
K
L
C
I
C
P
1
t
i
B
0
1
1
1
K
L
C
I
C
P
0
t
i
B
8
1
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
8
2
1
7
M
A
R
D
S
6
t
i
B
9
2
1
6
M
A
R
D
S
5
t
i
B
1
3
1
5
M
A
R
D
S
4
t
i
B
2
3
1
4
M
A
R
D
S
3
t
i
B
4
3
1
3
M
A
R
D
S
2
t
i
B
5
3
1
2
M
A
R
D
S
1
t
i
B
7
3
1
1
M
A
R
D
S
0
t
i
B
8
3
1
0
M
A
R
D
S
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
X
#
E
D
O
M
3
t
i
B
-
X
#
1
S
F
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
8
4
1
1
F
E
R
0
t
i
B
2
1
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
6
2
1
z
H
M
8
4
4
t
i
B
5
2
1
z
H
M
8
4
_
4
2
3
t
i
B
7
1
1
1
1
M
A
R
D
S
2
t
i
B
8
1
1
0
1
M
A
R
D
S
1
t
i
B
0
2
1
9
M
A
R
D
S
0
t
i
B
1
2
1
8
M
A
R
D
S
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