Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9248- 127
Block Diagram
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9248-127 Rev C 8/18/00
Pin Configuration
·
Up to 124MHz frequency support.
·
Spread Spectrum for EMI control 0 to -0.5% down
spread and ±0.25% center spread
·
Serial I
2
C interface for Power Management,
Frequency Select, Spread Spectrum.
·
Provides the following system clocks
- 4-CPUs @ 3.3V, up to 124MHz.
- 13-SDRAMs @3.3V, up to 124MHz
(including SDRAM_F)
- 6-PCI (including 1 free running, PCICLK_F)
@3.3V, CPU/2 or CPU/3.
- 1-24MHz @3.3V fixed.
- 1-48MHz @3.3V fixed.
- 2-REF @3.3V, 14.318MHz.
·
Efficient Power management scheme through PCI
and STOP CLOCKS.
48-Pin SSOP
Power Groups
VDDCPU, GNDCPU = CPUCLKS, CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS, SDRAM_F
VDDPCI, GNDPCI = PCICLKS, PCICLK_F
VDD48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
* Internal Pull-up Resistor of 240K to VDD
The ICS9248-127 is the single chip clock solution for Desktop
designs using the VIA MVP4 and Aladdin 7 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-
127 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
VDDREF
*PCI_STOP#/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDATA
SCLK
REF1/FS2*
VDDCPU
CPUCLK_F
CPUCLK0
GND
CPUCLK1
CPUCLK2
CLK_STOP#
GND
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24MHz/FS1*
ICS9248-127
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK_STOP#
PCI_STOP#
PLL2
PLL1
Spread
Spectrum
48MHz
24MHz
CPUCLK_F
CPUCLK (2:0)
SDRAM (11:0)
PCICLK (4:0)
PCICLK_F
SDRAM_F
X1
X2
BUFFER IN
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
STOP
SDATA
SCLK
FS(3:0)
MODE
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
LATCH
POR
2
3
12
5
4
4
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
4
ICS9248-127
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default.
Note 1. Default at Power-up will be for latched logic inputs to define frequency.
I
2
C readback of the power up default indicate the revision ID code in bit 2,
6:4 as shown.
I
2
C is a trademark of Philips Corporation
t
i
B
n
o
i
t
p
i
r
c
s
e
D
D
W
P
7
t
i
B
n
o
i
t
a
l
u
d
o
M
m
u
r
t
c
e
p
S
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
-
0
n
o
i
t
a
l
u
d
o
M
m
u
r
t
c
e
p
S
d
a
e
r
p
S
n
w
o
D
%
5
.
0
-
o
t
0
-
1
1
t
i
B
]
4
:
6
,
2
[
]
4
:
6
,
2
[
t
i
B
K
L
C
U
P
C
)
z
H
M
(
K
L
C
I
C
P
)
z
H
M
(
1
e
t
o
N
0
1
0
,
0
0
0
0
0
0
0
.
4
2
1
3
3
.
1
4
1
0
0
0
0
0
.
0
2
1
0
0
.
0
4
0
1
0
0
9
9
.
4
1
1
3
3
.
8
3
1
1
0
0
9
9
.
9
0
1
6
6
.
6
3
0
0
1
0
0
0
.
5
0
1
0
0
.
5
3
1
0
1
0
1
3
.
3
8
5
6
.
1
4
0
1
1
0
0
0
.
0
8
0
0
.
0
4
1
1
1
0
0
0
.
5
7
0
5
.
7
3
0
0
0
1
0
0
.
0
0
1
3
3
.
3
3
1
0
0
1
9
1
.
5
9
3
7
.
1
3
0
1
0
1
1
3
.
3
8
7
7
.
7
2
1
1
0
1
0
0
.
7
9
3
3
.
2
3
0
0
1
1
0
0
.
0
9
0
0
.
0
3
1
0
1
1
0
0
.
0
7
0
0
.
5
3
0
1
1
1
2
8
.
6
6
1
4
.
3
3
1
1
1
1
0
0
.
0
6
0
0
.
0
3
3
t
i
B
s
t
u
p
n
i
d
e
h
c
t
a
l
,
t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
]
4
:
6
,
2
[
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
2
e
t
o
N
1
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
l
l
a
e
t
a
t
s
i
r
T
-
1
0
Note 2. To ensure normal operation, Bit 7 needs to be "0" when in non - spread spectrum
mode (Bit 1 = 0).
5
ICS9248- 127
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
X
#
0
S
F
d
e
h
c
t
a
L
6
t
i
B
7
1
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
I
C
P
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
3
1
1
)
t
c
a
n
I
/
t
c
A
(
4
K
L
C
I
C
P
3
t
i
B
2
1
1
)
t
c
a
n
I
/
t
c
A
(
3
K
L
C
I
C
P
2
t
i
B
1
1
1
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
I
C
P
1
t
i
B
0
1
1
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
I
C
P
0
t
i
B
8
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
I
C
P
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
X
#
2
S
F
d
e
h
c
t
a
L
6
t
i
B
6
4
1
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
U
P
C
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
9
3
1
)
t
c
a
n
I
/
t
c
A
(
F
_
M
A
R
D
S
2
t
i
B
2
4
1
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
U
P
C
1
t
i
B
3
4
1
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
U
P
C
0
t
i
B
5
4
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
U
P
C
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
7
1
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
1
M
A
R
D
S
6
t
i
B
8
1
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
1
M
A
R
D
S
5
t
i
B
0
2
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
9
M
A
R
D
S
4
t
i
B
1
2
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
8
M
A
R
D
S
3
t
i
B
8
2
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
7
M
A
R
D
S
2
t
i
B
9
2
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
M
A
R
D
S
1
t
i
B
1
3
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
M
A
R
D
S
0
t
i
B
2
3
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
M
A
R
D
S
PDF 
ZIP
