Integrated
Circuit
Systems, Inc.
ICS9248-171
Third party brands and names are the property of their respective owners.
Block Diagram
9248-171 Rev - 12/29/00
Functionality
Pin Configuration
48-Pin 300mil SSOP &
240mil TSSOP package
Recommended Application:
ALI 1647 style chipset
Output Features:
·
1 - Differential pair open drain CPU clocks
·
1 - Single-ended open drain CPU clock
·
13 - SDRAM @ 3.3V
·
7 - PCI @3.3V
·
2 - AGP @ 3.3V
·
1 - 48MHz, @3.3V
·
1 - REF @3.3V, (selectable strength) through I
2
C
Features:
·
Up to 147MHz frequency support
·
Support power management: DG stop, PCI stop and
Power down Mode from I
2
C programming.
·
Spread spectrum for EMI control (0 to -0.5% down
spread, ± 0.25% center spread).
·
Uses external 14.318MHz crystal
Skew Specifications:
·
CPUT - CPUC: <250ps
·
PCI - PCI: <500ps
·
CPU - SDRAM: <350ps
·
SDRAM - SDRAM: <250ps
·
AGP - AGP: <250ps
·
PCI - AGP: <350ps
·
CPU - PCI: <3ns
AMD - K7TM System Clock Chip
*DG_STOP#
*PD#
GND
X1
X2
AVDD
**FS0/REF0
VDD
**FS1/AGP0
AGP1
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDD
*MODE/PCICLK3
PCICLK4
PCICLK5
AVDD48
**FS3/48MHz
GND
SCLK
GND
CPUCLKT0
CPUCLKC0
CPUCLKT1
SDATA
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
GND
SDRAM6
SDRAM7
SDRAM8
SDRAM9
GND
VDD
SDRAM10(PCI_STOP#)*
SDRAM11
SDRAM12
ICS9248-171
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
PLL2
PLL1
Spread
Spectrum
48MHz
CPUCLKT (1:0)
SDRAM (12:0)
PCICLK (5:0)
AGP (1:0)
2
6
13
2
PCICLK_F
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
DG_STOP#
MODE
Control
Logic
Config.
Reg.
REF0
Notes:
REF0 could be 1X or 2X strength controlled by I
2
C.
* Internal Pull-up Resistor of 120K to VDD
** Internal pull-down of 120K to GND.
Power Groups
AVDD = Xtal, Core PLL
AVDD48 = 48MHz, Fixed PLL
FS3
FS2
FS1
FS0
CPU
SDRAM
0
0
0
0
66.66
66.66
0
0
0
1
66.66
100.00
0
0
1
0
100.00
66.66
0
0
1
1
100.00
100.00
0
1
0
0
100.00
133.33
0
1
0
1
120.00
120.00
0
1
1
0
133.33
100.00
0
1
1
1
133.33
133.33
1
0
0
0
90.00
90.00
1
0
0
1
101.00
101.00
1
0
1
0
100.00
66.66
1
0
1
1
100.00
100.00
1
1
0
0
100.00
133.33
0
1
0
1
126.00
126.00
1
1
1
0
133.33
100.00
1
1
1
1
133.33
133.33
2
ICS9248-171
Advance Information
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Internal pull-down resistor of 120K to GND.
3:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
DG_STOP#
1
IN
DG_STOP halts SDRAM and/or AGP clocks at logic "0" when driven low.
The stops selection can be programed through I
2
C.
2
PD#
1
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
4
X1
IN
Crystal input,nominally 14.318M Hz.
5
X2
OUT
Crystal output, nominally 14.318MHz.
3, 11, 16, 23, 29,
34, 41, 48
GND
PWR
Ground pins
8, 17, 28, 35, 40
VDD
PWR
Power supply pins, nominal 3.3V
6
AVDD
PWR
Analog power supply pin, nominal 3.3V
FS0
2, 3
IN
Frequency select pin.
REF0
OUT
14.318 M Hz reference clock.
FS1
2, 3
IN
Frequency select pin.
AGP0
OUT
AGP outputs defined as 2X PCI. These may not be stopped.
10
AGP1
OUT
AGP outputs defined as 2X PCI. These may not be stopped.
PCICLK_F
OUT
Free running PCICLK not stoped by PCI_STOP#
FS2
1, 3
IN
Frequency select pin.
20, 19, 15, 14, 13
PCICLK
(5:4) (2:0)
OUT
PCI clock outputs.
PCICLK3
OUT
PCI clock output.
M ODE
1, 3
IN
Function select pin, 1=Desktop M ode, 0=M obile M ode.
21
AVDD48
PWR
Analog power supply pin, nominal 3.3V
FS3
2, 3
IN
Frequency select pin.
48MHz
OUT
48MHz output clock
24
SCLK
IN
Clock input of I
2
C input, 5V tolerant input
PCI_STOP#
1
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM 10
OUT
SDRAM clock output.
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
SDRAM
(12:11, 9:0 )
OUT
SDRAM clock outputs.
44
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
45, 47
CPUCLKT (1:0)
OUT
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
46
CPUCLKC0
OUT
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
9
7
27
12
22
18
3
ICS9248-171
Advance Information
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-171 is a main clock synthesizer chip for AMD-K7 based systems with ALI 1647 style chipset. This provides all
clocks required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-171
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
8
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ICS9248-171
Advance Information
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I
2
C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
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e
r
p
S
-
1
0
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
t
u
o
l
l
a
e
t
a
t
s
i
r
T
-
1
0
5
ICS9248-171
Advance Information
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
E
D
O
M
6
t
i
B
0
2
1
5
K
L
C
I
C
P
5
t
i
B
9
1
1
4
K
L
C
I
C
P
4
t
i
B
8
1
1
3
K
L
C
I
C
P
3
t
i
B
5
1
1
2
K
L
C
I
C
P
2
t
i
B
4
1
1
1
K
L
C
I
C
P
1
t
i
B
3
1
1
0
K
L
C
I
C
P
0
t
i
B
2
1
1
F
_
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
l
l
i
w
#
P
O
T
S
_
G
D
1
0
=
)
6
:
7
(
t
i
B
t
i
B
s
k
c
o
l
c
P
G
A
&
M
A
R
D
S
p
o
t
s
p
o
t
s
l
l
i
w
#
P
O
T
S
_
G
D
0
1
=
)
6
:
7
(
=
)
6
:
7
(
t
i
B
y
l
n
o
s
k
c
o
l
c
M
A
R
D
S
P
G
A
p
o
t
s
l
l
i
w
#
P
O
T
S
_
G
D
1
1
y
l
n
o
s
k
c
o
l
c
6
t
i
B
-
1
5
t
i
B
9
3
1
2
M
A
R
D
S
4
t
i
B
8
3
1
3
M
A
R
D
S
3
t
i
B
7
3
1
4
M
A
R
D
S
2
t
i
B
6
3
1
5
M
A
R
D
S
1
t
i
B
3
3
1
6
M
A
R
D
S
0
t
i
B
2
3
1
7
M
A
R
D
S
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
0
S
F
6
t
i
B
-
X
#
1
S
F
5
t
i
B
-
X
#
2
S
F
4
t
i
B
1
3
1
8
M
A
R
D
S
3
t
i
B
0
3
1
9
M
A
R
D
S
2
t
i
B
7
2
1
0
1
M
A
R
D
S
1
t
i
B
6
2
1
1
1
M
A
R
D
S
0
t
i
B
5
2
1
2
1
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
3
S
F
6
t
i
B
0
1
1
1
P
G
A
5
t
i
B
9
1
0
P
G
A
4
t
i
B
2
2
1
z
H
M
8
4
3
t
i
B
3
4
1
0
M
A
R
D
S
2
t
i
B
7
1
X
2
r
o
X
1
-
0
F
E
R
X
1
=
1
=
t
l
u
a
f
e
d
1
t
i
B
6
4
,
7
4
1
0
C
K
L
C
U
P
C
,
0
T
K
L
C
U
P
C
0
t
i
B
5
4
1
1
T
K
L
C
U
P
C
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
2
4
1
1
M
A
R
D
S
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