Integrated
Circuit
Systems, Inc.
ICS9248-168
Third party brands and names are the property of their respective owners.
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KT133 style chipset
Output Features:
·
1 - Differential pair open drain CPU clocks
·
1 - CPU clock @ 3.3V
·
7 - SDRAM @ 3.3V
·
8 - PCI @ 3.3V,
·
1 - 48MHz, @ 3.3V fixed.
·
1 - 24/48MHz @ 3.3V
·
3 - REF @ 3.3V, 14.318MHz.
Features:
·
Up to 153MHz frequency support
·
Support power management: CPU stop and Power down
Mode from I
2
C programming.
·
Spread spectrum for EMI control
(± 0.25% to ± 0.6% center, or 0 to -0.5% or -1.0% down
spread).
·
Uses external 14.318MHz crystal
AMD - K7
TM
Clock Generator for Mobile System
* Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
2
These outputs can be set to 1.5X strength through I
2
C
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
REF0
REF
REF2
GND
GND
VDD
CPUCLK
CPUCLKT0
CPUCLKC0
CPU_STOP#*
PD#*
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
1
2
2
2
1
ICS9248-168
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
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28
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26
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SEL24_48#
SDATA
SCLK
FS (2:0)
PD#
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (5:0)
PCICLK (6:0)
PCICLK_F
SDRAM_F
CPUCLKT0
CPUCLK
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Stop
Stop
Control
Logic
Config.
Reg.
/ 2
REF (2:0)
SDRAM
DRIVER
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
9248-168 Rev B 01/09/01
2
ICS9248-168
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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3
ICS9248-168
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-168 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides
all clocks required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-168
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
4
ICS9248-168
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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n
e
C
%
5
2
.
0
-
/
+
0
1
0
0
0
0
3
.
0
0
1
3
4
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
0
1
0
0
1
3
7
.
3
3
1
3
4
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
0
1
0
1
0
0
3
.
0
0
1
3
4
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
0
6
.
0
-
/
+
0
1
0
1
1
3
7
.
3
3
1
3
4
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
0
6
.
0
-
/
+
0
1
1
0
0
0
0
.
1
0
1
7
6
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
0
1
1
0
1
6
6
.
4
3
1
7
6
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
0
1
1
1
0
0
0
.
2
0
1
0
0
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
0
1
1
1
1
0
0
.
6
3
1
0
0
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
0
0
0
0
0
.
3
0
1
3
3
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
0
0
1
3
3
.
7
3
1
3
3
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
0
1
0
0
0
.
4
0
1
7
6
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
0
1
1
6
6
.
8
3
1
7
6
.
4
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
1
0
0
0
0
.
5
0
1
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
1
0
1
0
0
.
0
4
1
0
0
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
1
1
0
0
0
.
7
0
1
7
6
.
5
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
0
1
1
1
6
6
.
2
4
1
7
6
.
5
3
d
a
e
r
p
S
r
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C
%
5
3
.
0
-
/
+
1
1
0
0
0
0
0
.
0
1
1
7
6
.
6
3
d
a
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r
p
S
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C
%
5
3
.
0
-
/
+
1
1
0
0
1
6
6
.
6
4
1
7
6
.
6
3
d
a
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r
p
S
r
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t
n
e
C
%
5
3
.
0
-
/
+
1
1
0
1
0
0
0
.
5
1
1
3
3
.
8
3
d
a
e
r
p
S
r
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t
n
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C
%
5
3
.
0
-
/
+
1
1
0
1
1
3
3
.
3
5
1
3
3
.
8
3
d
a
e
r
p
S
r
e
t
n
e
C
%
5
3
.
0
-
/
+
1
1
1
0
0
0
0
.
0
0
1
3
3
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
0
5
.
0
-
/
+
1
1
1
0
1
3
3
.
3
3
1
3
3
.
3
3
d
a
e
r
p
S
r
e
t
n
e
C
%
0
5
.
0
-
/
+
1
1
1
1
0
0
0
.
0
0
1
3
3
.
3
3
d
a
e
r
p
S
n
w
o
D
%
0
.
1
-
o
t
0
1
1
1
1
1
3
3
.
3
3
1
3
3
.
3
3
d
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r
p
S
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w
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D
%
0
.
1
-
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t
0
3
t
i
B
s
t
u
p
n
I
d
e
h
c
t
a
L
,
t
c
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l
e
s
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r
a
w
d
r
a
h
y
b
d
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t
c
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l
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s
s
i
y
c
n
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q
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r
F
-
0
4
:
7
,
2
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
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u
q
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r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
d
a
e
r
p
S
r
e
t
n
e
C
%
5
2
.
0
±
d
e
l
b
a
n
E
m
u
r
t
c
e
p
S
d
a
e
r
p
S
-
1
1
0
t
i
B
g
n
i
n
n
u
R
-
0
s
t
u
p
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l
a
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t
a
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s
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T
-
1
0
5
ICS9248-168
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
2
2
1
0
S
F
6
t
i
B
5
1
1
S
F
5
t
i
B
4
1
2
S
F
4
t
i
B
2
4
1
X
1
=
1
X
5
.
1
=
0
K
L
C
U
P
C
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
0
4
,
1
4
1
X
1
=
1
X
5
.
1
=
0
C
/
T
K
L
C
U
P
C
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
2
4
1
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
4
1
F
_
K
L
C
I
C
P
6
t
i
B
5
1
1
6
K
L
C
I
C
P
5
t
i
B
2
1
1
5
K
L
C
I
C
P
4
t
i
B
1
1
1
4
K
L
C
I
C
P
3
t
i
B
0
1
1
3
K
L
C
I
C
P
2
t
i
B
9
1
2
K
L
C
I
C
P
1
t
i
B
8
1
1
K
L
C
I
C
P
0
t
i
B
5
1
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
7
2
1
F
_
M
A
R
D
S
5
t
i
B
8
2
1
5
M
A
R
D
S
4
t
i
B
9
2
1
4
M
A
R
D
S
3
t
i
B
2
3
1
3
M
A
R
D
S
2
t
i
B
3
3
1
2
M
A
R
D
S
1
t
i
B
6
3
1
1
M
A
R
D
S
0
t
i
B
7
3
1
0
M
A
R
D
S
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
3
2
1
#
8
4
_
4
2
L
E
S
5
t
i
B
2
2
1
z
H
M
8
4
4
t
i
B
3
2
1
z
H
M
8
4
_
4
2
3
t
i
B
8
4
1
0
F
E
R
2
t
i
B
7
4
1
1
F
E
R
1
t
i
B
6
4
1
2
F
E
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
0
d
e
v
r
e
s
e
R
4
t
i
B
-
0
d
e
v
r
e
s
e
R
3
t
i
B
-
0
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
0
d
e
v
r
e
s
e
R
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