Integrated
Circuit
Systems, Inc.
ICS9248-150
Third party brands and names are the property of their respective owners.
9248-150 Rev B 06/12/01
Pin Configuration
48-Pin SSOP and TSSOP
Recommended Application:
ServerWorks Grand Champion Systems.
Output Features:
·
8 - Differential CPU Clock Pairs @ 3.3V
·
1 - 3V 33MHz PCI clocks
·
1 - 48MHz clock
·
1 - Inverted 48MHz clock
·
1 - 14.318 reference output
Features:
·
Up to 200MHz frequency support
·
Support power management: Power Down Mode
·
Supports Spread Spectrum modulation: 0 to -0.5% down
spread.
·
Uses external 14.318MHz crystal
·
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum.
·
External resistor for current reference
·
FS pins for frequency select
Key Specifications:
·
PCI Output jitter <500ps
·
CPU Output jitter <200ps
·
48MHz Output jitter <350ps
·
REF Output jitter < 1000ps
Frequency Generator for Multi - Processor Servers
Functionality
/
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Block Diagram
PCICLK
VDD48
FS0/48MHz
FS1/48MHz#
GND48
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT3
CPUCLKC3
VDDCPU
REF
SPREAD#
GNDREF
X1
X2
VDDREF
SEL100/133
GNDPCI
VDDA
GNDA
PD#
VDDCPU
CPUCLKT4
CPUCLKC4
GNDCPU
CPUCLKT5
CPUCLKC5
VDDCPU
CPUCLKT6
CPUCLKC6
GNDCPU
CPUCLKT7
CPUCLKC7
VDDCPU
MULTSEL0
MULTSEL1
GND
GNDI REF
I REF
VDDI REF
ICS9248-150
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
I REF
PLL2
PLL1
Spread
Spectrum
48MHz
PCICLK
48MHz#
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
PD#
SPREAD#
MULTSEL(1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
REF
8
8
CPUCLKT (7:0)
CPUCLKC (7:0)
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
Analog Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
Digital Power Group
VDDREF, GNDREF = REF, Xtal
2
ICS9248-150
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
The ICS9248-150 is a main clock for ServerWorks Grand Champion Systems.
Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-150 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and temperature variations.
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ICS9248-150
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
µ
A
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
µ
A
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
Operating Supply
Current
I
DD3.3OP
C
L
= 0 pF; Select @ 100 MHz
181
250
mA
Powerdown Current
I
DD3.3PD
C
L
= 0 pF; Input address to VDD or GND
52
60
mA
Input Frequency
F
i
V
DD
= 3.3 V
14.318
MHz
Pin Inductance
L
pin
7
nH
C
IN
Logic Inputs
5
pF
C
OUT
Output pin capacitance
6
pF
C
INX
X1 & X2 pins
27
45
pF
Transition time
1
T
trans
To 1st crossing of target frequency
3
ms
Settling time
1
T
s
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency
3
ms
t
PZH
,t
PZL
Output enable delay (all outputs)
1
10
ns
t
PHZ
,t
PLZ
Output disable delay (all outputs)
1
10
ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
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