85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
1
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
CC
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
V
EE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
SEL1
SEL0
V
CC
Q0
nQ0
V
CC
nc
nc
V
EE
ICS85357-01
20-Lead TSSOP
4.40mm x 6.50mm x 0.90mm body package
G Package
Top View
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
Q0
nQ0
00
11
01
10
SEL1 SEL0
G
ENERAL
D
ESCRIPTION
The ICS85357-01 is a 4:1 or 2:1 Differential-to-
3.3V LVPECL / ECL clock multiplexer which can
operate up to 750MHz and is a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS85357-01 has 4
selectable clock inputs. The CLK, nCLK pair can accept most
standard differential input levels. The device can operate
using a 3.3V LVPECL (V
EE
= 0V, V
CC
= 3.135V to 3.465V) or
3.3V ECL (V
CC
= 0V, V
EE
= -3.135V to -3.465V). The fully dif-
ferential architecture and low propagation delay make it
ideal for use in clock distribution circuits. The select pins have
internal pulldown resistors. Leaving one input unconnected
(pulled to logic low by the internal resistor) will transform
the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins
will select the same numbered data input (i.e., 00
selects CLK0, nCLK0).
F
EATURES
·
High speed differential multiplexer. The device can be
configured as either a 4:1 or 2:1 multiplexer
·
1 differential 3.3V LVPECL output
·
4 selectable CLK, nCLK inputs
·
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
·
Maximum output frequency up to 750MHz
·
Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLKx input
·
Part-to-part skew: 150ps (maximum)
·
Propagation delay: 1.5ns (maximum)
·
LVPECL mode operating voltage supply range:
V
CC
= 3.135V to 3.465V, V
EE
= 0V
·
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.135V to -3.465V
·
0°C to 70°C ambient operating temperature
·
Industrial temperature information available upon request
HiPerClockSTM
,&6
85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
2
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
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85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
3
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
l
o
b
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S
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DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
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=
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5
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µ
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CC
+ 0.5V
Package Thermal Impedance,
JA
73.2°C/W (0lfpm)
Storage Temperature, T
STG
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
4
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
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4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
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2
-
85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
5
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
1 - O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
= 2.0V
V
CC
V
EE
= -1.3V
±
0.135V
F
IGURE
2 - D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
CLKx
nCLKx
V
EE
V
CC
Q0
nQ0
85357AG-01
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REV. A JULY 16, 2001
6
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
F
IGURE
3- P
ART
-
TO
-P
ART
S
KEW
Q0
nQ0
Q0
nQ0
PART 1
PART 2
F
IGURE
4 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
F
IGURE
5 - P
ROPAGATION
D
ELAY
CLKx
nCLKx
Q0
nQ0
F
IGURE
6 - odc & t
P
ERIOD
CLKx, Q0
nCLKx, nQ0
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
t
PD
Clock Inputs
and Outputs
20%
80%
20%
80%
t
R
t
F
V
S W I N G
tsk(pp)
85357AG-01
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REV. A JULY 16, 2001
7
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 7 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
F
IGURE
7 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
85357AG-01
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REV. A JULY 16, 2001
8
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85357-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85357-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
·
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 35mA = 121.3mW
·
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.25mW + 120.8mW = 151.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.151W * 66.6°C/W = 80.06°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6. Thermal Resistance
q
JA
for 20-pin TSSOP, Forced Convection
85357AG-01
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REV. A JULY 16, 2001
9
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 8.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
)
·
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
Using V
CC_MAX
= 3.465, this results in V
OH_MAX
= 2.465V
·
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
Using V
CC_MAX
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50
] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50
] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
Figure 8 - LVPECL Driver Circuit and Termination
85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
10
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85357-01 is: 400
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
11
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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85357AG-01
www.icst.com/products/hiperclocks.html
REV. A JULY 16, 2001
12
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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