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Part Number ICS843001

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843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
1
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS843001 is a Fibre Channel Clock Generator
and a member of the HiPerClocks
TM
family of high
performance devices from ICS. The ICS843001
uses either a 26.5625MHz or a 23.4375 crystal to
synthesize 106.25MHz, 187.5MHz or 212.5MHz,
using the FREQ_SEL pin. The ICS843001 has excellent <1ps
phase jitter performance, over the 637KHz ­ 10MHz integration
range. The ICS843001 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
F
EATURES
· 1 differential 3.3V LVPECL output
· Crystal oscillator interface designed for 23.4375MHz or
26.5625MHz, 18pF parallel resonant crystal
· Selectable 106.25MHz, 187.5MHz or 212.5MHz
output frequency
· VCO range: 560MHz - 680MHz
· RMS phase jitter @ 106.255MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.74ps (typical)
· RMS phase noise at 106.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -95.2 dBc/Hz
1KHz .............. -118.7 dBc/Hz
10KHz .............. -129.1 dBc/Hz
100KHz .............. -129.6 dBc/Hz
· 3.3V operating supply
· -30°C to 85°C ambient operating temperature
HiPerClockSTM
ICS
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1
F
UNCTION
T
ABLE
ICS843001
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
V
CCA
V
EE
XTAL_OUT
XTAL_IN
1
2
3
4
V
CC
Q0
nQ0
FREQ_SEL
8
7
6
5
OSC
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
M = ÷24 (fixed)
1
0
÷6
÷3
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
XTAL_IN
XTAL_OUT
nQ0
Q0
FREQ_SEL
(Pulldown)
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
2
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
3
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -30°C
TO
85°C
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3C. LVPECL DC C
HARACTERISTICS
,
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CC
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= -30°C
TO
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BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
101.7°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -30°C
TO
85°C
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µ
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
4
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -30°C
TO
85°C
l
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m
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843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
5
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
212.5MH
Z
212.5MHz
RMS Phase Noise Jitter
637K to 10MHz = 0.67ps (typical)
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.74ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
6
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
187.5MH
Z
187.5MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.52ps (typical)
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
Raw Phase Noise Data
10 Gigabit Ethernet Filter
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
7
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V ± 0.165V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0
nQ0
V
EE
V
CC
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
8
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843001 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF par-
allel resonant crystal and were chosen to minimize the ppm er-
ror. The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843001 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
CC
, and V
CCA
should
b e i n d i v i d u a l l y c o n n e c t e d t o t h e p o w e r s u p p l y
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
µF
.01
µF
3.3V
.01
µF
V
CC
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
9
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
F
IGURE
3A. ICS843001 S
CHEMATIC
E
XAMPLE
L
AYOUT
G
UIDELINE
Figure 3A shows a schematic example of the ICS843001. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
parallel resonant crystal is used. The C1 = 27pF and C2 = 33pF
are recommended for frequency accuracy. The C1 and C2 val-
ues may be slightly adjusted for optimizing frequency accuracy.
F
IGURE
3B. ICS843001 PC B
OARD
L
AYOUT
E
XAMPLE
VCCA
C1
27pF
nQ
C4
0.01u
Q
R5
133
R1
1K
Zo = 50 Ohm
VCC
R6
82.5
18pF
C5
0.1u
C3
10uF
+
-
U1
ICS843001
1
2
3
4
8
7
6
5
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q0
nQ0
FREQ_SEL
VCC
R3
133
R4
82.5
VCC
Zo = 50 Ohm
X1
26.5625MHz
R2
10
VCC
C2
33pF
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 3B shows an example of ICS843001 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age. The footprints of other components in this example are listed
in the
Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
T
ABLE
6. F
OOTPRINT
T
ABLE
e
c
n
e
r
e
f
e
R
e
z
i
S
2
C
,
1
C
2
0
4
0
3
C
5
0
8
0
5
C
,
4
C
3
0
6
0
2
R
3
0
6
0
t
n
e
n
o
p
m
o
c
s
t
s
il
,
6
e
l
b
a
T
:
E
T
O
N
.
e
l
p
m
a
x
e
t
u
o
y
a
l
s
i
h
t
n
i
n
w
o
h
s
s
e
z
i
s
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
10
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
·
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 93mA = 322.2mW
·
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.352W * 90.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
7. T
HERMAL
R
ESISTANCE


JA
FOR
8-
PIN
TSSOP, F
ORCED
C
ONVECTION


JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
843001AG
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REV. B OCTOBER 13, 2004
11
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
·
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
­ 0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
·
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
­ 1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
­ (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
­ (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
4. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
12
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843001 is: 1702
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP


JA
by Velocity (Meters Per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
13
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- G S
UFFIX
8 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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Y
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5
4
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°
0
°
8
a
a
a
-
-
0
1
.
0
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
14
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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-
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
843001AG
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 13, 2004
15
Integrated
Circuit
Systems, Inc.
ICS843001
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
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