Part Number HY57V281620HC

Download:  PDF   ZIP

HY57V281620HC(L/S)T-I Series

4 Banks x 2M x 16bits Synchronous DRAM

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 1.0/Mar. 02 1

DESCRIPTION

The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which
require low power consumption and extended temperature range. HY57V281620HC(L/S)T is organized as 4banks of 2,097,152x16

HY57V281620HC(L/S)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

·

Single 3.3

±

0.3V power supply

·

All device pins are compatible with LVTTL interface

·

JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch

·

All inputs and outputs referenced to positive edge of
system clock

·

Data mask function by UDQM or LDQM

·

Internal four banks operation

·

Auto refresh and self refresh

·

4096 refresh cycles / 64ms

·

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

·

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V281620HCT-6I

166MHz

Normal

4Banks x 2Mbits

x16

LVTTL

400mil 54pin TSOP II

HY57V281620HCT-7I

143MHz

HY57V281620HCT-KI

133MHz

HY57V281620HCT-HI

133MHz

HY57V281620HCT-8I

125MHz

HY57V281620HCT-PI

100MHz

HY57V281620HCT-SI

100MHz

HY57V281620HC(L/S)T-6I

166MHz

Low power

HY57V281620HC(L/S)T-7I

143MHz

HY57V281620HC(L/S)T-KI

133MHz

HY57V281620HC(L/S)T-HI

133MHz

HY57V281620HC(L/S)T-8I

125MHz

HY57V281620HC(L/S)T-PI

100MHz

HY57V281620HC(L/S)T-SI

100MHz

HY57V281620HC(L/S)T-I

Rev. 1.0/Mar. 02 2

PIN CONFIGURATION

PIN DESCRIPTION

PIN

PIN NAME

DESCRIPTION

CLK

Clock

The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK

CKE

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh

CS

Chip Select

Enables or disables all inputs except CLK, CKE, UDQM and LDQM

BA0, BA1

Bank Address

Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity

A0 ~ A11

Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10

RAS, CAS, WE

Row Address Strobe, Col-
umn Address Strobe, Write
Enable

RAS, CAS and WE define the operation
Refer function truth table for details

UDQM, LDQM

Data Input/Output Mask

Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ15

Data Input/Output

Multiplexed data input / output pin

V

DD

/V

SS

Power Supply/Ground

Power supply for internal circuits and input buffers

V

DDQ

/V

SSQ

Data Output Power/Ground

Power supply for output buffers

NC

No Connection

No connection

V

SS

DQ15
V

SSQ

DQ14
DQ13
V

DDQ

DQ12
DQ11
V

SSQ

DQ10
DQ9
V

DDQ

DQ8
V

SS

NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

V

DD

DQ0

V

DDQ

DQ1
DQ2

V

SSQ

DQ3
DQ4

V

DDQ

DQ5
DQ6

V

SSQ

DQ7

V

DD

LDQM

/WE

/CAS
/RAS

/CS

BA0
BA1

A10/AP

A0
A1
A2
A3

V

DD

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

HY57V281620HC(L/S)T-I

Rev. 1.0/Mar. 02 3

FUNCTIONAL BLOCK DIAGRAM

2Mbit x 4banks x 16 I/O Synchronous DRAM

X decoders

State Machine

A0
A1

A11

BA0
BA1

Addres

s buffers

Address
Registers

Mode Registers

Row

Pre

Decoders

Column

Pre

Decoders

Column Add

Counter

Row active

Column
Active

Burst

Counter

Data Out Control

CAS Latency

Internal Row

counter

DQ0

DQ1

DQ14

DQ15

refresh

Self refresh logic

& timer

Pipe Line Control

I/O Buffer & Logic

Bank Select

Sense

AMP & I/O Gate

CLK

CKE

CS

RAS

CAS

WE

UDQM

LDQM

2Mx16 Bank 3

X decoders

X decoders

Memory

Cell

Array

Y decoders

X decoders

2Mx16 Bank 0

2Mx16 Bank 1

2Mx16 Bank 2

HY57V281620HC(L/S)T-I

Rev. 1.0/Mar. 02 4

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION

(T

A

= -40 to 85

°C

)

Note :
1.All voltages are referenced to V

SS

= 0V

2.V

IH

(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3.V

IL

(min) is acceptable -2.0V AC pulse width with <=3ns of duration.

AC OPERATING TEST CONDITION

(T

A

= -40 to 85

°C

, V

DD

=3.3

±

0.3V, V

SS

=0V)

Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature

T

A

-40 ~ 85

°C

Storage Temperature

T

STG

-55 ~ 125

°C

Voltage on Any Pin relative to V

SS

V

IN

, V

OUT

-1.0 ~ 4.6

V

Voltage on V

DD

relative to V

SS

V

DD,

V

DDQ

-1.0 ~ 4.6

V

Short Circuit Output Current

I

OS

50

mA

Power Dissipation

P

D

1

W

Soldering Temperature

Time

T

SOLDER

260

10

°C

Sec

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

V

DD

, V

DDQ

3.0

3.3

3.6

V

1

Input High voltage

V

IH

2.0

3.0

V

DDQ

+ 0.3

V

1,2

Input Low voltage

V

IL

-0.3

0

0.8

V

1,3

Parameter

Symbol

Value

Unit

Note

AC Input High / Low Level Voltage

V

IH

/ V

IL

2.4/0.4

V

Input Timing Measurement Reference Level Voltage

Vtrip

1.4

V

Input Rise / Fall Time

tR / tF

1

ns

Output Timing Measurement Reference Level Voltage

Voutref

1.4

V

Output Load Capacitance for Access Time Measurement

C

L

50

pF

1

HY57V281620HC(L/S)T-I

Rev. 1.0/Mar. 02 5

CAPACITANCE

(TA=25

°C

, f=1MHz)

OUTPUT LOAD CIRCUIT

DC CHARACTERISTICS I

(TA= -40 to 85

°C

, V

DD

=3.3

±

0.3V)

Note :

1.V

IN

= 0 to 3.6V, All other pins are not tested under V

IN

=0V

2.D

OUT

is disabled, V

OUT

=0 to 3.6

Parameter

Pin

Symbol

-6I/KI/HI

-8I/PI/SI

Unit

Min

Max

Min

Max

Input capacitance

CLK

C

I1

2.5

3.5

2.5

4.0

pF

A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,
WE, UDQM, LDQM

CI

2

2.5

3.8

2.5

5.0

pF

Data input / output capacitance

DQ0 ~ DQ15

C

I/O

4.0

6.5

4.0

6.5

pF

Parameter

Symbol

Min.

Max

Unit

Note

Input Leakage Current

I

LI

-1

1

uA

1

Output Leakage Current

I

LO

-1

1

uA

2

Output High Voltage

V

OH

2.4

-

V

I

OH

= -2mA

Output Low Voltage

V

OL

-

0.4

V

I

OL

= +2mA

Vtt=1.4V

RT=250

50pF

Output

50pF

Output

DC Output Load Circuit

AC Output Load Circuit

Document Outline

• Description
• Features
• Ordering Information
• Pin Configuration
• Pin Description
• Functional Block Diagram
• Absolute Maximum Ratings
• DC Operating Condition
• AC Operating Test Condition
• Capacitance
• Output Load Circuit
• DC Characteristics-I
• DC Characteristics-II
• AC Characteristics-I
• AC Characteristics-II
• Device Operating Option Table
• Command Truth Table
• Package Information