FIFO--SOI
HX6409
HX6218
HX6136
Aerospace Electronics
FEATURES
· 1K x 36, 2K x 18, 4K x 9 Organizations
· Fabricated with RICMOS
TM
IV Silicon on Insulator
(SOI) 0.8
µ
m Process (L
eff
= 0.65
µ
m)
RADIATION
· Total Dose Hardness through 1x10
6
rad(SiO
2
)
· Neutron Hardness through 1x10
14
cm
-2
· Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
· Dose Rate Survivability through 1x10
11
rad(Si)/s
· Soft Error Rate of <1x10
-10
upsets/bit-day
· No Latchup
OTHER
· Read/Write Cycle Times
<35 ns (-55
°
to 125
°
C)
· Expandable in Width
· Supports Free-Running 50% Duty Cycle Clock
· Empty, Full, Half Full, 1/4 Full, 3/4 Full, Error Flags
· Parity Generation/Checking
· Fully Asynchronous with Simultaneous
Read and Write Operation
· Output Enable (OE)
· CMOS or TTL Compatible I/O
· Single 5 V
±
10% Power Supply
· Various Flat Pack Options
The HX6409, HX6218, and HX6136 are high speed, low-
power, first-in first-out memories with clocked read and
write interfaces. The HX6409 is a 4096 word by 9 bit
memory array, the HX6218 is a 2048 word by 18 bit
memory array, and the HX6136 is a 1024 word by 36 bit
memory array. The FIFOs support width expansion while
depth expansion requires external logic control using state
machine techniques. Features include programmable par-
ity control, an empty/full flag, a quarter/three quarter full
flag, a half full flag and an error flag.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffer-
ing. These FIFOs have separate input and output ports
that are controlled by separate clock and enable sig-
nals. The input port is controlled by a free running clock
(CKW) and a write enable pin
ENW
. When
ENW
is
asserted, data is written into the FIFO on the rising edge
of the CKW signal. While
ENW
is held active, data is
continually written into the FIFO on each CKW cycle.
The output port is controlled in a similar manner by a free-
running read clock (CKR) and a read enable pin (
ENR
). In
addition, the three FIFOs have an output enable pin (
OE
)
and a master reset pin (
MR
). The read (CKR) and write
(CKW) clocks may be tied together for single-clock
operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies
up to 30 MHz are achievable in the three configurations.
Honeywell's enhanced SOI RICMOSTM IV (Radiation In-
sensitive CMOS) technology is radiation hardened through
the use of advanced and proprietary design, layout and
process hardening techniques. The FIFO is fabricated with
Honeywell's radiation hardened technology, and is de-
signed for use in systems operating in radiation environ-
ments. The SOI RICMOSTM IV process is a 5-volt, SIMOX
CMOS technology with a 150 Å gate oxide and a minimum
drawn feature size of 0.8
µ
m, (0.65
µ
m effective gate
array--L
eff
). Additional features include tungsten via plugs,
Honeywell's proprietary SHARP planarization process,
and a lightly doped drain (LDD) structure for improved short
channel reliability.
GENERAL DESCRIPTION
Solid State Electronics Center · 12001 State Highway 55, Plymouth, MN 55441 · (800) 323-8295 · http://www.ssec.honeywell.com
HX6409/HX6218/HX6136
2
Word Count
EF_ Fault
E/ F
QF/TQF HF
State
4K x 9
2K x 18
1K x 36
0
0
0
1
Empty Fault
(Enabled Read when Empty)
0
0
0
1
0
0
1
Empty
0
0
0
1
1
0
1
Less than or Equal to 1/4 Full
1 to 1024
1 to 512
1 to 256
1
1
1
1
Less than or Equal to 1/2 Full
1025 to 2048
513 to 1024
257 to 512
1
1
1
0
Greater that 1/2 Full
2049 to 3071
1025 to1535
513 to 767
1
1
0
0
Greater than or Equal to 3/4 Full
3072 to 4095
1536 to 2047
768 to 1023
1
0
0
0
Full
4096
2048
1024
0
0
0
0
Full Fault
(Enabled Write when Full)
4096
2048
1024
FLAG DECODE TABLE
LOGIC BLOCK DIAGRAM
CKW
ENW
Write Control
MR
Parity
Program
Register
Parity
Write Pointer
Reset Logic
Read Pointer
Read Control
CKR
ENR
Input
Register
Q: 0 - 8
Q: 0 - 17
Q: 0 - 35
Tri-State
Output Register
Memory
Array
4096 x 9
2048 x 18
1024 x 36
OE
D: 0 - 8
D: 0 - 17
D: 0 - 35
Flag Logic
HF
E/F
QF/TQF
EF_Fault
3
HX6409/HX6218/HX6136
Signal Name
I/O
Description
D: 0 - 35
I
Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when
ENW
is active and the FIFO is not full.
Q: 0 - 35
O
Data Outputs: Data Outputs are read out of the FIFO memory and updated on the rising
edge of CKR when
ENR
is active and the FIFO is not Empty. The Data Outputs are in a
high impedance state if
OE
is not active.
ENW
I
Enable Write: An active low signal that enables the write of the Data Inputs on the CKW
rising edge (if FIFO is not full).
ENR
I
Enable Read: An active low signal that enables the read and update of the Data Outputs
on the CKR rising edge (if FIFO is not empty).
CKW
I
Write Clock: The rising edge clocks data into the FIFO when
ENW
is low (active). On the
rising edge, this signal also updates the Half Full, 3/4 Full, Full, and Full Fault Flags.
CKR
I
Read Clock: The rising edge clocks data out of the FIFO when
ENR
is low (active). On
the rising edge, this signal also updates the 1/4 Full, Empty, and Empty Fault Flags.
HF
O
Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is greater
than half full.
E/ F
O
Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated on
the rising edge of CKW.
QF/TQF
O
1/4 Full or 3/4 Full Flag: 1/4 Full is updated on the rising edge of CKR, and 3/4 Full is
updated on the rising edge of CKW. 1/4 Full signifies 256 or less words in the 1K x 36
FIFO and 3/4 Full signifies 256 words or less until a full condition.
EF_Fault
O
Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full
Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already
empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault condition
is detected, the Fault Flag remains latched until the empty or full condition is removed.
M R
I
Master Reset: Active low signal which, when active, resets device to empty condition.
OE
I
Output Enable: Active low signal which, when active, enables low impedance Data
Outputs, Q: 0 - 35.
SIGNAL DEFINITIONS
PROGRAMMABLE PARITY OPTIONS
2
D
1
D
0
D
s
n
o
i
t
i
d
n
o
C
O
X
X
d
e
l
b
a
s
i
D
y
t
i
r
a
P
I
O
O
5
3
Q
,
6
2
Q
,
7
1
Q
,
8
Q
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t
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r
a
P
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v
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t
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r
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P
d
d
O
e
t
a
r
e
n
e
G
5
3
Q
,
6
2
Q
,
7
1
Q
,
8
Q
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S
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o
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a
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r
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5
3
Q
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6
2
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7
1
Q
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8
Q
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r
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S
w
o
L
a
s
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r
o
r
r
E
,
5
3
Q
,
6
2
Q
,
7
1
Q
,
8
Q
HX6409/HX6218/HX6136
4
Total Dose
1x10
6
rad(SiO
2
)
Transient Dose Rate Upset
1x10
9
rad(Si)/s
Transient Dose Rate Survivability
1x10
11
rad(Si)/s
Soft Error Rate
<1x10
-10
upsets/bit-day
Neutron Fluence
1x10
14
N/cm
2
Parameter
Limits (2)
Test Conditions
RADIATION-HARDNESS RATINGS (1)
Units
T
A
=25
°
C
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
All FIFO configurations will meet all stated functional and
electrical specifications over the entire operating tempera-
ture range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will re-
main within specifications after rebound at VDD = 5.5 V
and T = 125
°
C extrapolated to ten years of operation. Total
dose hardness is assured by wafer level testing of process
monitor transistors and product using 10 KeV X-ray and
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 KeV X-rays applied at
a dose rate of 1x10
5
rad(SiO
2
)/min at T = 25
°
C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
Each FIFO configuration is capable of writing, reading
and retaining stored data during and after exposure to a
transient ionizing radiation pulse of <50 ns duration up to
1x10
9
rad(Si)/s, when applied under recommended oper-
ating conditions. To ensure validity of all specified perfor-
mance parameters before, during, and after radiation
(timing degradation during transient pulse radiation (tim-
ing degradation during transient pulse radiation is
10%),
it is suggested that stiffening capacitance be placed near
the package VDD and VSS, with a maximum inductance
between the package (chip) and stiffening capacitor of
0.7 nH per part. If there are no operate-through or valid
stored data requirements, typical circuit board mounted
de-coupling capacitors are recommended.
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55
°
C to 125
°
C.
1 MeV equivalent energy,
Unbiased, T
A
=25
°
C
T
A
=125
°
C, Adams 90%
worst case environment
Pulse width
50 ns, X-ray,
VDD=6.0 V, T
A
=25
°
C
Pulse width
50 ns
Each FIFO will meet any functional or electrical specifica-
tion after exposure to a radiation pulse of
50 ns duration
up to 1x10
11
rad(Si)/s, when applied under recommended
operating conditions. Note the current conducted during
the pulse by the inputs, outputs and power supply may
significantly exceed the normal operating levels. The appli-
cation design must accommodate these effects.
Neutron Radiation
Each FIFO configuration will meet any functional or timing
specification after a total neutron fluence of up to 1x10
14
cm
-
2
applied under recommended operating or storage condi-
tions. This assumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
This FIFO configuration has a soft error rate (SER) perfor-
mance of <1x10
-10
upsets/bit-day, under recommended
operating conditions. This hardness level is defined by the
Adams 90% worst case cosmic ray environment.
Latchup
This FIFO configuration will not latch up due to any of the
above radiation exposure conditions when applied under
recommended operating conditions. Fabrication with the
SIMOX substrate with its oxide isolation ensure latchup
immunity.
5
HX6409/HX6218/HX6136
VDD
Supply Voltage Range (2)
-0.5
7.0
V
VPIN
Voltage on Any Pin (2)
-0.5
VDD+0.5
V
TSTORE
Storage Temperature (Zero Bias)
-65
150
°
C
TSOLDER
Soldering Temperature (5 Seconds)
270
°
C
PD
Maximum Power Dissipation (3)
2.5
W
IOUT
DC or Average Output Current
25
mA
VPROT
ESD Input Protection Voltage (4)
2000
V
JC
Thermal Resistance (Jct-to-Case)
5
°
C/W
TJ
Junction Temperature
175
°
C
VDD
Supply Voltage (referenced to VSS)
4.5
5.0
5.5
V
TA
Ambient Temperature
-55
25
125
°
C
VPIN
Voltage on Any Pin (referenced to VSS)
-0.3
VDD+0.3
V
Parameter
Parameter
Symbol
CAPACITANCE (1)
Symbol
Test Conditions
Min
Max
Units
(1) This parameter is tested during initial design characterization only.
RECOMMENDED OPERATING CONDITIONS
Symbol
Max
Typ
Parameter
Min
Units
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Rating
CI
Input Capacitance
7
pF
VI=VDD or VSS, f=1 MHz
CO
Output Capacitance
9
pF
VIO=VDD or VSS, f=1 MHz
Units
Typical
(1)
Worst Case
Min
Max
Test Conditions
(1) Typical operating conditions: TA= 25
°
C, pre-radiation.
(2) Worst case operating conditions: TC= -55
°
C to +125
°
C, post total dose at 25
°
C.
VDR
Data Retention Voltage
2.5
V
IDR
Data Retention Current
500
µ
A
NCS=VDR
VI=VDR or VSS
NCS=VDD=VDR
VI=VDR or VSS
Worst Case
(2)
Typical
(1)
Description
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) FIFO power dissipation (IDDSB + IDDOP) plus FIFO output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
ABSOLUTE MAXIMUM RATINGS (1)
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