HD74HC137
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When
GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As
long as
GL remains high no address changes will be recognized. Output enable controls, G
1
and G
2
, control
the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are high unless G
1
is high and G
2
is low. The HD74HC137 is ideally suited for the
implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
·
High Speed Operation: t
pd
(A, B, C to Y) = 16.5 ns typ (C
L
= 50 pF)
·
High Output Current: Fanout of 10 LSTTL Loads
·
Wide Operating Voltage: V
CC
= 2 V to 6 V
·
Low Input Current: 1 µA max
·
Low Quiescent Supply Current: I
CC
(static) = 4 µA max (Ta = 25°C)