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Part Number HD74ALVC162836

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HD74ALVC162836
20-bit Universal Bus Driver with 3-state Outputs
ADE-205-207 (Z)
Preliminary
1st. Edition
January 1998
Description
This 20-bit universal bus driver is designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (
OE) input. The device operates in the
transparent mode when the latch enable (
LE) input is low. When LE is high, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is high, the A data is stored in the latch flip
flop on the low to high transition of CLK. When
OE is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
All outputs, which are designed to sink up to 12 mA, include 26
resistors to reduce overshoot and
undershoot.
Features
·
V
CC
= 2.3 V to 3.6 V
·
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
°
C)
·
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25
°
C)
·
High output current
±
12 mA (@V
CC
= 3.0 V)
·
All outputs have equivalent 26
series resistors, so no external resistors are required.
HD74ALVC162836
2
Function Table
Inputs
Output Y
OE
LE
CLK
A
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
L
L
L
H
H
H
L
H
L or H
X
Y
0
*1
H : High level
L : Low level
X : Immaterial
Z : High impedance
: Low to high transition
Note:
1. Output level before the indicated steady state input conditions were established.
HD74ALVC162836
3
Pin Arrangement
(Top view)
1
2
3
4
5
6
7
8
9
10
V
CC
V
CC
Y1
Y2
GND
Y3
Y4
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
Y17
Y18
OE
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
A18
GND 25
32 GND
Y19 26
31 A19
Y20 27
30 A20
NC 28
29
LE
A17
A16
A15
A14
A13
GND
A12
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
CLK
GND
A1
V
CC
V
CC
HD74ALVC162836
4
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
V
CC
­0.5 to 4.6
V
Input voltage
*1
V
I
­0.5 to 4.6
V
Output voltage
*1, 2
V
O
­0.5 to V
CC
+0.5
V
Input clamp current
I
IK
­50
mA
V
I
< 0
Output clamp current
I
OK
±
50
mA
V
O
< 0 or V
O
> V
CC
Continuous output current
I
O
±
50
mA
V
O
= 0 to V
CC
V
CC
, GND current / pin
I
CC
or I
GND
±
100
mA
Maximum power dissipation
at Ta = 55
°
C (in still air)
*3
P
T
1
W
TSSOP
Storage temperature
Tstg
­65 to 150
°
C
Notes:
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150
°
C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Conditions
Supply voltage
V
CC
2.3
3.6
V
Input voltage
V
I
0
V
CC
V
Output voltage
V
O
0
V
CC
V
High level output current
I
OH
--
­6
mA
V
CC
= 2.3 V
--
­8
V
CC
= 2.7 V
--
­12
V
CC
= 3.0 V
Low level output current
I
OL
--
6
mA
V
CC
= 2.3 V
--
8
V
CC
= 2.7 V
--
12
V
CC
= 3.0 V
Input transition rise or fall rate
t /
v
0
10
ns / V
Operating temperature
Ta
­40
85
°
C
Note:
Unused control inputs must be held high or low to prevent them from floating.
HD74ALVC162836
5
Logic Diagram
OE
LE
A1
1
56
29
55
To nineteen other channels
CLK
C1
1D
CLK
2
Y1