HD74AC125/HD74ACT125
Quad Buffer/Line Driver with 3-State Output
Description
The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory
address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board
density.
Features
·
3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
·
Outputs Source/Sink 24 mA
·
HD74ACT125 has TTL-Compatible Inputs
Pin Arrangement
1
2
3
4
5
6
7
E
D
O
E
D
O
GND
V
CC
E
D
O
E
D
O
14
13
12
11
10
9
8
(Top view)
HD74AC125/HD74ACT125
2
Logic Symbol
D
O
E
Pin Names
D
Data Inputs
E
3-State Output Enable Inputs (Active Low)
O
Outputs
Truth Table
Inputs
E
D
Output
L
L
L
L
H
H
H
X
Z
H :
High Voltage Level
L
:
Low Voltage Level
X :
Immaterial
Z
:
High Impedance
DC Characteristics (unless otherwise specified)
Item
Symbol
Max
Unit
Condition
Maximum quiescent supply current
I
CC
80
µ
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
Maximum quiescent supply current
I
CC
8.0
µ
A
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25
°
C
Maximum I
CC
/input (HD74ACT125)
I
CCT
1.5
mA
V
IN
= V
CC
2.1 V, V
CC
= 5.5 V
Ta = Worst case
HD74AC125/HD74ACT125
3
AC Characteristics: HD74AC125
Ta = +25
°
C
C
L
= 50 pF
Ta = 40
°
C to +85
°
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Min
Typ
Max
Min
Max
Unit
Propagation delay
t
PLH
3.3
1.0
6.5
9.0
1.0
10.0
ns
5.0
1.0
5.5
7.0
1.0
7.5
Propagation delay
t
PHL
3.3
1.0
6.5
9.0
1.0
10.0
5.0
1.0
5.0
7.0
1.0
7.5
Enable time
t
PZH
3.3
1.0
6.0
10.5
1.0
11.0
5.0
1.0
5.0
7.0
1.0
8.0
Enable time
t
PHZ
3.3
1.0
7.5
10.0
1.0
11.0
5.0
1.0
5.5
8.0
1.0
8.5
Disable time
t
PZL
3.3
1.0
7.0
10.0
1.0
10.5
5.0
1.0
6.5
9.5
1.0
9.5
Disable time
t
PLZ
3.3
1.0
7.5
10.5
1.0
11.5
5.0
1.0
6.5
9.0
1.0
9.5
Note:
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
AC Characteristics: HD74ACT125
Ta = +25
°
C
C
L
= 50 pF
Ta = 40
°
C to +85
°
C
C
L
= 50 pF
Item
Symbol
V
CC
(V)*
1
Min
Typ
Max
Min
Max
Unit
Propagation delay
t
PLH
5.0
1.0
6.5
9.0
1.0
10.0
ns
Propagation delay
t
PHL
5.0
1.0
7.0
9.0
1.0
10.0
Enable time
t
PZH
5.0
1.0
6.0
8.5
1.0
9.5
Enable time
t
PZL
5.0
1.0
7.0
9.5
1.0
10.5
Disable time
t
PHZ
5.0
1.0
7.0
9.5
1.0
10.5
Disable time
t
PLZ
5.0
1.0
7.5
10.0
1.0
10.5
Note:
1. Voltage Range 5.0 is 5.0 V
±
0.5 V
Capacitance
Item
Symbol
Typ
Unit
Condition
Input capacitance
C
IN
4.5
pF
V
CC
= 5.5 V
Power dissipation capacitance
C
PD
45.0
pF
V
CC
= 5.0 V
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-14
Conforms
Conforms
0.97 g
Unit: mm
7.62
0.25
0
°
15
°
19.20
20.32 Max
1
8
14
7
1.30
2.54
±
0.25
0.48
±
0.10
6.30
7.40 Max
0.51 Min
2.54 Min
5.06 Max
+ 0.10
0.05
2.39 Max
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-14DA
--
Conforms
0.23 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
*0.22
±
0.05
*0.42
±
0.08
0.70
±
0.20
0.12
0.15
0
°
8
°
M
0.10
±
0.10
2.20 Max
5.5
10.06
1.42 Max
14
8
1
7
10.5 Max
+ 0.20
0.30
7.80
1.15
1.27
0.40
±
0.06
0.20
±
0.04
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