SERIAL DATA

PLL

SERIAL CLOCK

LOOP

FILTER

SS0

SS1

CARRIER
DETECT

DATA

LATCH

PHASE

COMPARATOR

CARRIER
DETECT

CHARGE

PUMP

STANDARD

SELECT

VCO

13 14 15 17

SERIAL DATA

SERIAL CLOCK

DIGITAL
IN

5,6

GS9015A

GENLINX

GS9015A

Serial Digital Reclocker

DATA SHEET

Revision Date: April 1998

FEATURES

DEVICE DESCRIPTION

The GS9015A is a monolithic IC designed to receive SMPTE
259M serial digital video signals. This device performs the
function of data and clock recovery. It interfaces directly with
the

GENLINX

GS9000B or GS9000S Decoder.

While there are no plans to discontinue the GS9015A, Gennum
has developed a successor product with improved features
and performance called the GS9035. The GS9035 is
recommended for new designs.

The VCO centre frequencies are controlled by external resistors
which can be selected by applying a two bit binary code to the
Standards Select input pins. Alternatively, the GS9015A can
be used with the GS9010A to form an adjustment free reclocker
system.

The GS9015A is packaged in a 28 pin PLCC operating from
a single +5 or -5 volt supply.

· reclocking of SMPTE 259M signals

· operational to 400 Mb/s

· adjustment free reclocker when used with the
GS9000B or GS9000S decoder and GS9010A
Automatic Tuning Sub-system

· 28 pin PLCC packaging

APPLICATIONS

· 4

, 4:2:2 and 360 Mb/s serial digital interfaces

ORDERING INFORMATION

PART NUMBER

PACKAGE TEMPERATURE

GS9015ACPJ

28 Pin PLCC

C to 70

GS9015ACTJ

28 Pin PLCC Tape

C to 70

SPECIAL NOTE: R

VCO1

and R

VCO2

are functional over a

reduced temperature range of T

C to 50

C. R

VCO0

and R

VCO3

are functional over the full temperature range

of T

C to 70

C. This limitation does not affect

operation with the GS9010A ATS.

FUNCTIONAL BLOCK DIAGRAM

Document No. 520 - 99 - 05

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946

Web Site: www.gennum.com E-mail: info@gennum.com

520 - 99 - 05

ABSOLUTE MAXIMUM RATINGS

PARAMETER

VALUE/UNITS

Supply Voltage

5.5 V

Input Voltage Range (any input)

+0.5 to V

-0.5 V

DC Input Current (any one input)

5 mA

Power Dissipation

750 mW

Operating Temperature Range

Storage Temperature Range

-65

150

Lead Temperature (soldering, 10 seconds)

260

PARAMETER SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS NOTES

Supply Voltage

Operating Range

4.75

5.0

5.25

Power Consumption

330

500

Supply Current (Total)

120

mA see Figure11

Serial Data & - High

= 25

-1.025

-0.88

V with respect to V

Clock Output - Low

= 25

-1.9

-1.6

Logic Inputs - High

IH MIN

+2.0

V with respect to V

- Low

IL MAX

+0.8

V with respect to V

Carrier Detect

CDL

= 10 k

to V

0.2

0.4

Output Voltage

CDH

4.0

5.0

Serial Data Bit Rate

SDO

= 25

100

400

Mb/s

Serial Clock Frequency

SLK

= 25

100

400

MHz see Figure 9

Output Signal Swing

= 25

700

800

900

mV p-p see Figure10

Serial Data to Serial Clock

See Waveforms

-500

ps Data lags Clock

Lock Times

LOCK

see note 1

Jitter

= 25

C, 270 Mb/s

100

ps p-p see Figure12

Direct Digital Input

DDI

200

2000

mVp-p Differential Drive

Levels (5, 6)

= 5V, T

= 0

C to 70

C, R

= 100

to (V

- 2V) unless otherwise shown.

(1, 10, 20, 21)

GS9015A RECLOCKER DC ELECTRICAL CHARACTERISTICS

with respect to V

with respect to

Open

Collector - Active High

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

Synchronization

= 5V, T

= 0

C to 70

C, R

= 100

to (V

- 2V) unless otherwise shown.

GS9015A RECLOCKER AC ELECTRICAL CHARACTERISTICS

NOTES: 1.

Switching between two sources of the same data rate.

CAUTION

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE

EXCEPT AT A STATIC-FREE WORKSTATION

520 - 99 - 05

The GS9015A Reclocking Receiver is a bipolar integrated
circuit containing circuitry necessary to re-clock and regenerate
the NRZI serial data stream.

Packaged in a 28 pin PLCC, the receiver operates from a
single five volt supply at data rates to 400 Mb/s. Typical power
consumption is 330 mW. Typical output jitter is

100 ps at

270 Mb/s.

Serial Digital signals are applied to digital inputs DDI and DDI
(pins 5,6).

SERIAL
DATA OUT
(SD0)

50%

SERIAL
CLOCK OUT
(SCK)

50%

Phase Locked Loop

The phase comparator itself compares the position of
transitions in the incoming signal with the phase of the local
oscillator (VCO). The error-correcting output signals are fed
to the charge pump in the form of short pulses. The charge
pump converts these pulses into a "charge packet" which is
accurately proportional to the system phase error.

The charge packet is then integrated by the second-order
loop filter to produce a control voltage for the VCO.

During periods when there are no transitions in the signal, the
loop filter voltage is required to hold precisely at its last value
so that the VCO does not drift significantly between corrections.
Commutating diodes in the charge pump keep the output
leakage current extremely low, minimizing VCO frequency
drift.

The VCO is implemented using a current-controlled
multivibrator, designed to deliver good stability, low phase
noise and wide operating frequency capability. The frequency
range is design-limited to

10% about the oscillator centre

frequency.

Fig.1 Waveforms

VCO Centre Frequency Selection

The centre frequency of the VCO is set by one of four external
current reference resistors (RVCO0-RVCO3) connected to
pins 13,14,15 or 17. These are selected by two logic inputs
SS0 and SS1 (pins 20, 21) through a 2:4 decoder according
to the following truth table.

SS1

SS0 Resistor Selected

RVCO0 (13)

RVCO1 (14)

RVCO2 (15)

RVCO3 (17)

As an alternative, the GS9010A Automatic Tuning Sub-system
and the GS9000B or GS9000S Decoder may be used in
conjunction with the GS9015A to obtain adjustment free and
automatic standard select operation (see Figure17).

With the VCO operating at twice the clock frequency, a clock

phase which is centred on the eye of the locked signal is used
to latch the incoming data, thus maximising immunity to
jitter-induced errors. The alternate phase is used to latch the
output re-clocked data SDO and SDO (pins 25, 24). The true
and inverse clock signals themselves are available from the
SCO and SCO pins 23 and 22.

GS9015A Reclocking Receiver - Detailed Device Description

520 - 99 - 05

GS9015A PIN DESCRIPTIONS

PIN NO.

SYMBOL

TYPE

DESCRIPTION

EE1

Power Supply

. Most negative power supply connection.

EE1

Power Supply

. Most negative power supply connection.

EE1

Power Supply.

Most negative power supply connection.

EE1

Power Supply.

Most negative power supply connection.

5,6

DDI/DDI

Input

Direct Data Inputs (true and inverse).

Pseudo-ECL, differential serial data inputs. They may be

directly driven from true ECL drivers when V

= -5V and V

= 0 V.

CC1

Power Supply

. Most positive power supply connection. (Phase Detector, Carrier Detect).

8, 9

EE1

Power Supply

. Most negative power supply connection.

10 /2 EN

Input

/2 Enable-

TTL compatible input used to enable the divide by 2 function.

11 V

EE3

Power Supply.

Most negative power supply connection. (VCO, MUX, Standard Select)

LOOP FILT

Loop Filter.

Node for connecting the loop filter components.

VCO0

Input

VCO Resistor 0.

Analog current input used to set the centre frequency of the VCO when the two

Standard Select bits (pins 20 and 21) are set LOW. A resistor is connected from this pin to V

VCO1

Input

VCO Resistor 1.

Analog current input used to set the centre frequency of the VCO when Standard

Select bit 0 (pin 20) is set HIGH and bit 1 (pin 21) is set LOW. A resistor is connected from this pin to V

VCO2

Input

VCO Resistor 2.

Analog current input used to set the centre frequency of the VCO when Standard

Select bit 0 (pin 20) is set LOW and bit 1 (pin 21) is set HIGH. A resistor is connected from this pin to V

16 V

EE3

Power Supply

. Most negative power supply connection.

17 R

VCO3

Input

VCO Resistor 3.

Analog current input used to set the centre frequency of the VCO when the two

Standard Select bits (pins 20 and 21) are set HIGH. A resistor is connected from this pin to V

Fig. 2 GS9015A Pin Connections

SD0

SC0

SS1

SS0

DDI

CC1

EE1

EE2

CC3

GS9015A

TOP VIEW

LOOP R

VCO0

VCO1

VCO2

EE3

VCO3

CC2

FILT

13 14 15 16 17 18

4 3 2 28 27 26

/2 EN

EE3

520 - 99 - 05

PIN NO SYMBOL TYPE

DESCRIPTION

18 V

CC2

Power Supply.

Most positive power supply connection. (VCO, MUX, Standard Select).

Output

Carrier Detect

. Open collector output which goes HIGH when a signal is present at either the Serial

Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S

in the Automatic Standards Select Mode to disable the 2 bit standard select counter. This pin should

see a low AC impedance (e.g. 1nF to AC Gnd)

20,21

SS0, SS1 Inputs

Standard Select Inputs.

TTL inputs to the 2:4 multiplexer used to select one of four VCO

centre

frequency setting resistors (R

VCO0

- R

VCO3

). When both SS0 and SS1 are LOW, R

VCO0

is selected.

When SS0 is HIGH and SS1 is LOW, R

VCO1

is selected. When SS0 is LOW and SS1 is HIGH, R

VCO2

is selected and when both SS0 and SS1 are HIGH, R

VCO3

is selected. These pins should see a

low AC impedance (e.g. 1nF to AC Gnd)

22,23 SCO/SCO Outputs

Serial Clock Outputs (inverse and true).

Pseudo-ECL differential outputs of the extracted serial clock.

These outputs require a 390

pull-down resistors to V

24,25

SDO/SDO Outputs

Serial Data Outputs (inverse and true).

Pseudo-ECL differential outputs of the regenerated serial data.

These outputs require a 390

pull-down resistors to V

CC3

Power Supply.

Most positive power supply connection. (ECL Outputs).

EE2

Power Supply.

Most negative power supply connection. (Phase Detector, Carrier Detect)

EE1

Power Supply

. Most negative power supply connection.

GS9015A PIN DESCRIPTIONS cont.

1.6V

DDI

Pin 5

Pin 6

DDI

1.2V

380µA

Fig. 3 Pins 1, 5 and 6

INPUT / OUTPUT CIRCUITS

520 - 99 - 05

400

350

300

250

200

150

100

DATA RATE (Mb/s)

Fig. 12 Output Jitter

TYPICAL PERFORMANCE CURVES

500

450

400

350

300

250

200

150

100

2 3 4 5 6 7 8 9 10

FREQUENCY SETTING RESISTANCE (k

)

Fig. 9 Clock Frequency

0 10 20 30 40 50 60 70

TEMPERATURE (

Fig. 11 Supply Current

= 4.75V

= 5.25V

900

850

800

750

700

650

600

0 10 20 30 40 50 60 70

TEMPERATURE (

Fig. 10 Serial Outputs

/2 OFF

/2 ON

= 5.00V

= 5.25V

= 4.75V

= 5V, T

= 25

C unless otherwise shown)

105

100

100 150 200 250 300 350 400

= 5.00V

/2 OFF

/2 ON

FREQUENCY (MHz)

SERIAL OUTPUTS (mV) (p-p)

CURRENT (mA)

JITTER p-p (ps)

520 - 99 - 05

TEST SETUP

Figure 13 shows a typical circuit for the GS9015A using a +5
volt supply. Figure 14 shows the GS9015A connections when
using a -5 volt supply.

The 0.1

F decoupling capacitors must be placed as close as

possible to the corresponding VCC pins.

The layout of the loop filter and RVCO components requires
careful attention. This has been detailed in an application
note entitled "Optimizing Circuit and Layout Design of the
GS9005A/15A", Document No. 521 - 32 - 00.

The loop voltage can be conveniently measured across the
10 nF capacitor in the loop filter. Tuning procedures are
described in the Temperature Compensation Section (page
11). The fixed value frequency setting resistors should be
placed close to the corresponding pins on the GS9015A.

The Carrier Detect is an open-collector active high output
requiring a pull-up resistor of approximately 10 k

The SS0, SS1, and CD pins should see a low AC impedance.
This is particularly important when driving the SS0, SS1 pins
with external logic. The use of 1nF decoupling capacitors at
these pins ensures this.

Fig. 13 GS9015A Typical Test Circuit Using +5V Supply

All resistors in ohms, all capacitors in microfarads unless otherwise stated.

ECL DATA
INPUTS

0.1

100

390

DATA

CLOCK

4 3 2 1 28 27 26

12 13 14 15 16 17 18

910

5.6p

10n

See Figure 15

+5V

0.1

10k

CARRIER
DETECT
OUTPUT

+5V

GS9015A

SDO

SCO

SS1

SS0

VEE1

VEE2

VCC3

LOOP

RVCO0

RVCO1

RVCO2

VEE3

RVCO3

VCC2

STAR
ROUTED

LOOP
VOLTAGE
TEST
POINT

0.1

VCC1

VEE1

VEE3

520 - 99 - 05

Fig. 14 GS9015A Typical Test Circuit Using -5V Supply

All resistors in ohms, all capacitors in microfarads unless otherwise stated.

VCO Frequency Setting Resistors

There are two modes of VCO operation available in the
GS9015A depending on the state of the

2 block. The

block is enabled according to :

2 ENABLE = /2 · SS1. When

the /2 ENABLE (pin 10) is LOW, any of the four VCO
frequency setting resistors, RVCO0 through RVCO3, (pins
13, 14, 15 and 17) may be used for any data r a t e f r o m 100
Mb/s t o 4 0 0 M b / s . F o r e x a m p l e , f o r 143 Mb/s data
rate, the value of the total RVCO resistance is approximately
6k8 and f o r 2 7 0 M b / s o p e r a t i o n , t h e v a l u e i s
approximately 3k5. The 5k potentiometers will then tune
the desired data rate near their mid-points.

Jitter performance at the lower data rates (143, 177 Mb/s) is
improved by operating the VCO at twice the normal frequency.
This is accomplished by enabling the divide by two block in
the PLL section of the GS9015A.

When /2 (Pin 10) is HIGH, two of the RVCO pins are assigned
to data rates below 200 Mb/s and two are assigned to data
rates over 200 Mb/s. The selection is dependent upon the
level of STANDARD SELECT BIT, SS1 (pin 21). When SS1
is LOW, RVCO0 and RVCO1 (pins 13 and 14) are used for the
higher data rates. When SS1 is HIGH, the VCO frequency is
now twice the bit rate and its frequency is set by RVCO2 and
RVCO3 (pins 15 and 17).

For 143 Mb/s and 270 Mb/s operation, (the VCO is at
286 MHz and 270 MHz respectively) the total resistance
required is approximately the same for both data rates. This
also applies for 177 Mb/s and 360 Mb/s operation (the VCO
is tuned to 354 MHz and 360 MHz respectively). This means
that one potentiometer may be used for each frequency pair
with only a small variation of the fixed resistor value. This
halves the number of adjustments required.

ECL
DATA
INPUTS

-5V

100

390

0.1

4 3 2 1 28 27 26

12 13 14 15 16 17 18

910

5.6p

10n

-5V

0.1

10k

DATA

CARRIER
DETECT
OUTPUT

DATA

CLOCK

GS9015A

VCC1

VEE1

VEE3

SDO

SCO

SS1

SS0

VEE1

VEE2

VCC3

LOOP

RVCO0

RVCO1

RVCO2

V EE3

RVCO3

VCC2

STAR
ROUTED

LOOP
VOLTAGE

See Figure 15

-5V

0.1

520 - 99 - 05

5.6k

1N914

1.3k

Divide by 2 is OFF

4.3k

1N914

1.3k

Divide by 2 is ON

1N914

Divide by 2 is OFF

Divide by 2 is ON

1N914

0.1µF

Fig. 15 Frequency Setting Resistor Values

& Temperature Compensation

Divide by 2 is OFF

0.1µF

Figure 15 shows the connections for the frequency setting
resistors for the various data rates. The compensation shown
for 360 Mb/s and 177 Mb/s with Divide by 2 ON, is useful to
a maximum ambient temperature of 50

C. If the Divide by 2

function is not enabled by the /2 ENABLE input, no
compensation is needed for the 143 Mb/s and 177 Mb/s data
rates. The resistor connections are shown in Figure 16. In both
cases , the 0.1

F capacitor that bypasses the potentiometer

should be star routed to VEE3.

Temperature Compensation

Loop Bandwidth

The loop bandwidth is dependant upon the internal PLL gain
constants along with the loop filter components connected to
pin 12. In addition, the impedance seen by the RVCO pin also
influences the loop characteristics such that as the imped-
ance drops, the loop gain increases.

Applications Circuit

Figure 17 shows an application of the GS9015A in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Sub-
system IC and a GS9000B or GS9000S Decoder IC.

The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the
incoming data stream is 4sc NTSC,4sc PAL or component
4:2:2.

The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Reclocker VCO frequency over a
set range until the system is correctly locked. An automatic
fine tuning (AFT) loop maintains the Reclocker VCO

control

voltage at it's centre point through continuous, long term
adjustments of the VCO centre frequency.

During normal operation, the GS9000B or GS9000S Decoder
provides continuous HSYNC pulses which disable the
ramp/oscillator of the GS9010A. This maintains the
correct Reclocker VCO

frequency. When an interruption

to the incoming data stream is detected by the Reclocker,
the Carrier Detect goes LOW and opens the AFT loop in
order to maintain the correct VCO frequency for a period
of at least 2 seconds. This allows the Reclocker to rapidly
relock when the signal is re-established.

143Mb/s and 177 Mb/s using any R

VCO

pins

Fig. 16 Non - Temperature Compensated Resistor Values

for 143 Mb/s and 177 Mb/s

Temperature Compensation Procedure

In order to correctly set the VCO frequency so that the PLL will
always re-acquire lock over the full temperature range, the
following procedure should be used. The circuit should be
powered on for at least one minute prior to starting this
procedure.

Monitor the loop filter voltage at the junction of the loop filter
resistor and 10 nF loop filter capacitor (LOOP FILTER TEST
POINT). Using the appropriate network shown above, the
VCO frequency is set by first tuning the potentiometer so that
the PLL loses lock at the low end (lowest loop filter voltage).
The loop filter voltage is then slowly increased by adjusting the
the potentiometer to determine the error free low limit of the
capture range. Error free operation is determined by using a
suitable CRC or EDH measurement method to obtain a stable
signal with no errors. Record the loop filter voltage at this point
as V

. Now adjust the potentiometer so that the loop filter

voltage is 250 mV above V

270 Mb/s using R

VCO0

or R

VCO1

143 Mb/s using R

VCO2

or R

VCO3

177 Mb/s using R

VCO2

or R

VCO3

360 Mb/s using R

VCO0

or R

VCO1

520 - 99 - 05

Application Note - PCB Layout

Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, "Optimizing Circuit and Layout
Design of the GS90005A/15A". A recommended PCB layout can be found in the Gennum Application Note "EB9010B Deserializer
Evaluation Board"

The use of a star grounding technique is required for the loop filter components of the GS9005A/15A.

Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and
the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed
when a microstrip trace runs across a break in the ground plane.

The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.

(1) To reduce board space, the two anti-series 6.8

F capacitors (connected across pins 2 and 3 of

the GS9010A) may be replaced with a 1.0

F non-polarized capacitor provided that:

(a) the 0.68

F capacitor connected to the OSC pin (11) of the GS9010A is replaced with a

0.33

F capacitor and

(b) the GS9005A /15A Loop Filter Capacitor is 10 nF.

(2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.

(3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to

a maximum of 300 Mbps.

Fig. 17 Typical Application Circuit

All resistors in ohms,

all capacitors in microfarads,

all inductors in henries unless otherwise stated.

STANDARD TRUTH TABLE

/2 P/N STANDARD

0 0 4:2:2 - 270

0 1 4:2:2 - 360

1 0 4sc - NTSC

1 1 4sc - PAL

P/N

OUT

IN-

COMP

VCC
SWF

PARALLEL DATA BIT 9

PARALLEL DATA BIT 8

PARALLEL DATA BIT 7

PARALLEL DATA BIT 6

PARALLEL DATA BIT 5

PARALLEL DATA BIT 4

PARALLEL DATA BIT 3

PARALLEL DATA BIT 2

PARALLEL DATA BIT 1

PARALLEL DATA BIT 0

PARALLEL CLOCK OUT

SYNC CORRECTION ENABLE

HSYNC OUTPUT

SYNC WARNING FLAG

STDT

VCC

HSYNC

GND

OSC

DLY

FVCAP

0.1

+5V

100

390

4 3 2 1 28 27 26

12 13 14 15 16 17 18

910

5.6p

10n

(1)

(2)

0.1

3.3n

82n

180n

0.68

0.1

22n

DGND

DVCC

DGND

DVCC

VCC

DGND

GND

DGND

0.1

SERIAL
DIGITAL
INPUT

1.2k

68k

100

DVCC

DGND

120

50k

0.1

100k

GS9010A

VCC1

VEE1

VEE3

SDO

SCO

SS1

SS0

VEE1

VEE2

VCC3

LOOP

RVCO0

RVCO1

RVCO2

VEE3

RVCO3

VCC2

4 3 2 1 28 27 26

0.1

100

3.3k

100

GS9000B

or GS9000S

PD7

PD6

PD5

PD4

PD3

PD2

PD1

VSS

SWF

VSS

HSYNC

PD9

PD8

VSS

VDD

SCE

SWC

PCLK

PDO

VDD

STAR
ROUTED

12 13 14 15 16 17 18

VCC

SWF

VCC

6.8

GS9015A

SS1

SS0

SST

SWF

(3)

520 - 99 - 05

Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.

DOCUMENT IDENTIFICATION:

DATA SHEET

The product is in production. Gennum reserves the right to
make changes at any time to improve reliability, function or
design, in order to provide the best product possible.

REVISION NOTES:

New information added to Device Description

GENNUM CORPORATION

MAILING ADDRESS:

P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. +1 (905) 632-2996 Fax +1 (905) 632-2814

SHIPPING ADDRESS:

970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5

GENNUM JAPAN CORPORATION

C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168-0081, Japan

Tel. +81 (3) 3334-7700 Fax: +81 (3) 3247-8839

GENNUM UK LIMITED

Centaur House, Ancells Business Park, Ancells Road, Fleet, Hampshire, UK GU13 8UJ

Tel. +44 (1252) 761 039 Fax +44 (1252) 761 114

Part Number GS9015A