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GF9320
Scaling Processor
GF9320 Data Sheet
1 of 60
Proprietary and Confidential
18090 - 7
November 2004
Features
·
broadcast quality 10 / 8-bit 24-tap poly-phase horizontal
and vertical scalar for HDTV / SDTV video images
·
high performance 2D scaling processor with separate
control of horizontal and vertical scaling factors and pan
positions
·
support for arbitrary video formats up to 2048 by 2048
·
support for multiplexed and non-multiplexed Y/C video
·
flexible 4:2:2 or 4:4:4 YCbCr or RGB output
·
field merge / separation can be inserted / removed from
progressive images using interlaced I/O
·
double banked control registers for 'on-the-fly' dynamic
effects
·
external 3:2 / 2:2 pull-down insertion and extraction
·
programmable output matrix with 6dB gain range
·
film rate features include 1080p24 and 1080PsF support
·
fully programmable colour background generator
·
flexible F,V,H output and TRS insertion
·
seamless interface to GF9330 de-interlacer
·
seamless interface to common SDRAM
·
user configuration through dedicated serial interface
·
3.3V supply
Description
The GF9320 Scaling Processor offers 10 / 8-bit
broadcast quality scaling of video images up to 2048 by
2048 pixels. The GF9320 supports arbitrary display
modes to fit custom applications. Dynamic zoom and
pan effects allow for a variety of aspect ratio conversion
choices while a programmable colour background
generator can be customized to appropriately match the
image content. A fully programmable and flexible output
matrix allows for colour difference over-sampling, gain
and hue controls as well as YCbCr to RGB conversions
to power nearly any display device on the market.
The GF9320 also includes a vertical interpolation filter
to perform stand alone cost-sensitive de-interlacing.
Broadcast quality de-interlacing is offered through a
seamless interface to the GF9330 and GF9331 devices.
Applications
·
HDTV Up / Down Converters
·
Production Equipment
·
Video Walls
·
Projection Systems
·
Plasma Displays
·
LCD TVs
·
Home Theatre Systems
·
HD DVD Players
Ordering Information
Block Diagram
Part Number
Package
Temp. Range
GF9320-CBW
352 pin TBGA
0
o
C to 70
o
C
Input
Processing
Control
Interface
MUX
External
Memory Interface 1
External
Memory Interface 2
Horizontal
Scaling Filter
Vertical
Scaling Filter
MUX
MUX
Input
Processing
YC/Y
C
CTRL
G/Y/YC
B/Cb/C
R/Cr
GF9320 Data Sheet
2 of 60
Proprietary and Confidential
18090 - 7
November 2004
Contents
Features ........................................................................................................................1
Description ....................................................................................................................1
Applications...................................................................................................................1
Ordering Information .....................................................................................................1
1. Pin Description ..........................................................................................................3
2. Electrical Characteristics...........................................................................................7
3. Detailed Device Description ....................................................................................11
3.1 Device Overview ...........................................................................................11
3.2 Serial Interface Control .................................................................................12
3.3 Input Processing ...........................................................................................21
3.4 Scaling Processor .........................................................................................22
3.5 SDRAM Memory Interface ............................................................................34
3.6 Output Processor ..........................................................................................57
3.7 Output Timing Control ...................................................................................58
4. Package Dimensions ..............................................................................................59
5. Revision History ......................................................................................................60
GF9320 Data Sheet
3 of 60
Proprietary and Confidential
18090 - 7
November 2004
1. Pin Description
Figure 1-1: GF9320 Pin Out
TOP VIEW
GF9320 PIN OUT
352 TBGA
VDD: +3.3V
GND: 0V
NC: No Connection
ADDR_A5
ADDR_A7 ADDR_A10
CS_A0
CS_A2
WE_A
NC
DATA_A0
DATA_A4
DATA_A6
VDD
DATA_A12 DATA_A14
DATA_A15 DATA_A19 ADDR_B2
ADDR_B6
NC
BA_B
GND
CKEN_B
CS_B3
DATA_B0
DATA_B3
DATA_B6
DATA_B7
ADDR_A4
ADDR_A6
ADDR_A8
GND
CS_A1
CAS_A
NC
CKEN_A
DATA_A3
DATA_A5
GND
DATA_A11 DATA_A13
DATA_A16
GND
ADDR_B3
ADDR_B7
ADDR_B8
RAS_B
CK_B
CS_B0
DATAEN_AB DATA_B1
DATA_B5
DATA_B8
DATA_B9
ADDR_A1
ADDR_A3
VDD
ADDR_A9
VDD
RAS_A
VDD
GND
DATA_A2
VDD
DATA_A8
DATA_A10
VDD
DATA_A17 ADDR_B0
ADDR_B4
VDD
ADDR_B9
CAS_B
VDD
CS_B1
GND
DATA_B4
VDD
DATA_B10 DATA_B12
NC
NC
ADDR_A2
GND
BA_A
CS_A3
GND
CK_A
DATA_A1
GND
DATA_A7
DATA_A9
GND
DATA_A18 ADDR_B1
ADDR_B5
GND
ADDR_B10
WE_B
GND
CS_B2
DATA_B2
GND
DATA_B11
GND
DATA_B14
OUT_FRST
NC
NC
ADDR_A0
DATA_B13
VDD
DATA_B15 DATA_B16
RST
NC
NC
NC
DATA_B17 DATA_B18 DATA_B19
NC
GND
CK_IN
VDD
GND
GND
VDD
CK_V
GND
YIN9
FILM_FR
GND
NC
NC
NC
NC
NC
YIN5
YIN6
YIN7
YIN8
NC
NC
GND
OUT_CK
YIN3
YIN4
VDD
GND
GND
VDD
GOUT9
GOUT8
CIN9
YIN0
YIN1
YIN2
GOUT7
GOUT6
GOUT5
GOUT4
CIN5
CIN6
CIN7
CIN8
GOUT3
GND
GOUT2
GOUT1
CIN1
CIN2
CIN3
CIN4
GND
VDD
GOUT0
NC
CIN0
NC
VDD
GND
BOUT6
BOUT7
BOUT8
BOUT9
GND
GND
GND
GND
BOUT4
GND
VDD
BOUT5
OUT_H
OUT_V
OUT_F
NC
BOUT0
BOUT1
BOUT2
BOUT3
NC
NC
VDD
GND
GND
VDD
ROUT8
ROUT9
SIF_IN
SIF_CK
SIF_RST
SIF_OUT
ROUT5
ROUT6
ROUT7
NC
NC
NC
NC
NC
ROUT1
ROUT2
ROUT3
ROUT4
VDD
VDD
VDD
GND
GND
VDD
NC
ROUT0
TOUT1
TOUT2
NC
NC
DATA_D18 DATA_D19
GND
CK_OUT
NC
NC
NC
ADDR_C1
DATA_D13
GND
DATA_D16 DATA_D17
NC
ADDR_C0
ADDR_C3
GND
GND
CAS_C
GND
DATA_C1
VDD
GND
DATA_C7
DATA_C11 DATA_C14
GND
ADDR_D1
ADDR_D5
GND
BA_D
WE_D
GND
CS_D3
DATA_D2
GND
DATA_D11 DATA_D14 DATA_D15
ADDR_C2
ADDR_C4
VDD
ADDR_C10
CS_C1
RAS_C
VDD
DATA_C2
NC
VDD
DATA_C8
DATA_C12 DATA_C15
VDD
ADDR_D0
ADDR_D4
VDD
ADDR_D10
CAS_D
VDD
CS_D2
GND
DATA_D4
VDD
DATA_D10 DATA_D12
ADDR_C5
ADDR_C6
ADDR_C9
CS_C0
CS_C3
GND
CKEN_C
DATA_C3
NC
DATA_C5
DATA_C9
GND
DATA_C16 DATA_C19
NC
ADDR_D3
ADDR_D7
ADDR_D9
RAS_D
CK_D
CS_D1
DATAEN_CD DATA_D1
DATA_D5
DATA_D7
DATA_D9
ADDR_C7
ADDR_C8
BA_C
CS_C2
WE_C
CK_C
DATA_C0
DATA_C4
NC
DATA_C6
DATA_C10 DATA_C13 DATA_C17 DATA_C18
NC
ADDR_D2
ADDR_D6
ADDR_D8
CKEN_D
GND
CS_D0
VDD
DATA_D0
DATA_D3
DATA_D6
DATA_D8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
B
C
D
F
E
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GF9320 Data Sheet
4 of 60
Proprietary and Confidential
18090 - 7
November 2004
Table 1-1: Pin Descriptions
Symbol
Pin Grid
Type
Description
YIN[9:0]
H1, J4, J3, J2, J1, K2, K1,
L4, L3, L2
I
10-bit multiplexed signed luminance / signed offset colour difference data
input.
Note that either input must include TRS words.
CIN[9:0]
L1, M4, M3, M2, M1, N4,
N3, N2, N1, P1
I
10-bit signed offset colour difference data input.
Note that theinput must include TRS words.
CK_IN
G2
I
Input clock.
Note that it is equal Y data rate for separate Y and C inputs, and is equal to 2x
Y data rate for multiplexed YC input.
CK_V
G25
I
Vertical processing clock.
Note that it is usually the higher of CK_IN or CK_OUT.
CK_OUT
AA26
I
Output clock.
FILM_FR
H2
I
Input film sequence reset.
OUT_FRST
E1
I
Output frame reset.
GOUT[9:0]
K25, K26, L23, L24, L25,
L26, M23, M25, M26, N25
O
10 / 8-bit unsigned green data output OR
10 / 8-bit unsigned luminance data output OR
10 / 8-bit multiplexed signed luminance / signed offset colour difference data
output.
BOUT[9:0]
P26, P25, P24, P23, R26,
R23, T26, T25, T24, T23
O
10 / 8-bit unsigned blue data output OR
10 / 8-bit signed offset (B-Y) data output OR
10/8-bit multiplexed signed offset colour difference data output.
ROUT[9:0]
U26, U25, V25, V24, V23,
W26, W25, W24, W23,
Y26
O
10 / 8-bit unsigned red data output OR
10 / 8-bit signed offset (R-Y) data output.
OUT_CK
J26
O
Output clock timed to clock output data.
OUT_F
T3
O
Output format frame / field signal.
Note that the output is 3 clocks in advance of output video data.
OUT_V
T2
O
Output format vertical signal.
Note that the output is 3 clocks in advance of output video data.
OUT_H
T1
O
Output format horizontal signal.
Note that the output is 3 clocks in advance of output video data.
SIF_OUT
V4
O
Serial interface control data out.
SIF_IN
V1
I
Serial interface control data in.
SIF_CK
V2
I
Serial interface clock.
SIF_RST
V3
I
Serial interface reset.
RST
F1
I
Power-on reset.
DATA_A[19:0]
A15, D14, C14, B14, A14,
A13, B13, A12, B12, C12,
D12, C11, D11, A10, B10,
A9, B9, C9, D9, A8
I/O
Data bus for memory array A.
GF9320 Data Sheet
5 of 60
Proprietary and Confidential
18090 - 7
November 2004
DATA_B[19:0]
F25, F24, F23, E26, E25,
D26, E23, C26, D24, C25,
B26, B25, A26, A25, B24,
C23, A24, D22, B23, A23
I/O
Data bus for memory array B.
DATA_C[19:0]
AE14, AF14, AF13, AE13,
AD13, AC13, AF12, AD12,
AC12, AF11, AE11, AD11,
AC11, AF10, AE10, AF8,
AE8, AD8, AC8, AF7
I/O
Data bus for memory array C.
DATA_D[19:0]
AA24, AA23, AB26, AB25,
AC26, AC25, AB23, AD26,
AC24, AD25, AE26, AF26,
AE25, AF25, AE24, AD23,
AF24, AC22, AE23, AF23
I/O
Data bus for memory array D.
ADDR_A[10:0]
A3, C4, B3, A2, B2, A1,
B1, C2, D3, C1, E4
O
Address bus for memory array A.
BA_A
D5
O
SDRAM bank select for memory array A.
ADDR_B[10:0]
D18, C18, B18, B17, A17,
D16, C16, B16, A16, D15,
C15
O
Address bus for memory array B.
BA_B
A19
O
SDRAM bank select pin for memory array B.
ADDR_C[10:0]
AD4, AE3, AF2, AF1, AE2,
AE1, AD2, AC3, AD1, AB4,
AC2
O
Address bus for memory array C.
BA_C
AF3
O
SDRAM bank select pin for memory array C.
ADDR_D[10:0]
AD18, AE18, AF18, AE17,
AF17, AC16, AD16, AE16,
AF16, AC15, AD15
O
Address bus for memory array D.
BA_D
AC18
O
SDRAM bank select pin for memory array D.
CS_A[3:0]
D6, A5, B5, A4
O
Chip select for memory array A.
CS_B[3:0]
A22, D21, C21, B21
O
Chip select for memory array B.
CS_C[3:0]
AE5, AF4, AD5, AE4
O
Chip select for memory array C.
CS_D[3:0]
AC21, AD21, AE21, AF21
O
Chip select for memory array D.
RAS_A
C6
O
Row address strobe for memory array A.
RAS_B
B19
O
Row address strobe for memory array B.
RAS_C
AD6
O
Row address strobe for memory array C.
RAS_D
AE19
O
Row address strobe for memory array D.
CAS_A
B6
O
Column address strobe for memory array A.
CAS_B
C19
O
Column address strobe for memory array B.
CAS_C
AC6
O
Column address strobe for memory array C.
Table 1-1: Pin Descriptions (Continued)
Symbol
Pin Grid
Type
Description
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