DS05-20864-3E

FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

4M (512K

8) BIT

MBM29LV004TC

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/MBM29LV004BC

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FEATURES

· Single 3.0 V read, program, and erase

Minimizes system level power requirements

· Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

· Compatible with JEDEC-standard world-wide pinouts

40-pin TSOP(I) (Package suffix: PTN Normal Bend Type, PTR Reversed Bend Type)
40-pin SON (Package suffix: PNS)

· Minimum 100,000 program/erase cycles
· High performance

70 ns maximum access time

· Sector erase architecture

One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes
Any combination of sectors can be concurrently erased. Also supports full chip erase

· Boot Code Sector Architecture

T = Top sector
B = Bottom sector

· Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

· Embedded Program

Algorithms

Automatically writes and verifies data at specified address

· Data Polling and Toggle Bit feature for detection of program or erase cycle completion
· Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

· Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode

· Low V

write inhibit

2.5 V

· Erase Suspend/Resume

Suspends the erase operation to allow a read data in another sector within the same device

· Sector protection

Hardware method disables any combination of sectors from program or erase operations

· Sector Protection Set function by Extended sector protection command
· Temporary sector unprotection

Temporary sector unprotection via the RESET pin

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

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GENERAL DESCRIPTION

The MBM29LV004TC/BC are a 4M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each. The
MBM29LV004TC/BC are offered in a 40-pin TSOP(I) and 40-pin SON packages. These devices are designed
to be programmed in-system with the standard system 3.0 V V

supply. 12.0 V V

and 5.0 V V

are not required

for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV004TC/BC offer access times 70 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.

The MBM29LV004TC/BC are pin and command set compatible with JEDEC standard E

PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV004TC/BC are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.

Any individual sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV004TC/BC are erased when shipped from the
factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

Fujitsu's Flash technology combines years of EPROM and E

PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29LV004TC/BC memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte
at a time using the EPROM programming mechanism of hot electron injection.

MBM29LV004TC

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CONNECTION DIAGRAMS

(Continued)

RESET

N.C.

RY/BY

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

MBM29LV008TA/MBM29LV008BA

Standard Pinout

TSOP (I)

N.C.
A

N.C.
DQ

OE
V

CE
A

(Marking Side)

FPT-40P-M06

RY/BY

N.C.

RESET

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

MBM29LV008TA/MBM29LV008BA

Reverse Pinout

CE
V

OE
DQ

N.C.
V

(Marking Side)

FPT-40P-M07

MBM29LV004TC

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LOGIC SYMBOL

Legend: L = V

, H = V

, X = V

or V

= Pulse input. See DC Characteristics for voltage levels.

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 6.

2. Refer to the section on Sector Protection.
3. WE can be V

if OE is V

, OE at V

initiates the write operations.

4. V

= 3.3 V ± 10%

5. It is also used for the extended sector protection.

Table 1 MBM29LV004TC/004BC Pin Configuration

Pin

Function

to A

Address Inputs

to DQ

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

RY/BY

Ready/Busy Output

RESET

Hardware Reset Pin/Temporary Sector
Unprotection

N.C.

No Internal Connection

Device Ground

Device Power Supply

Table 2 MBM29LV004TC/004BC User Bus Operations

Operation

to DQ

RESET

Auto-Select Manufacturer Code (1)

Code

Auto-Select Device Code (1)

Code

Read (3)

OUT

Standby

HIGH-Z

Output Disable

HIGH-Z

Write (Program/Erase)

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

Code

Temporary Sector Unprotection (5)

Reset (Hardware)/Standby

HIGH-Z

to A

to DQ

RESET

RY/BY

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FUNCTIONAL DESCRIPTION

Read Mode

The MBM29LV004TC/BC have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.

Address access time (t

ACC

) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t

ACC

-t

time.) When reading out a data without changing addresses after

power-up, it is necessary to input hardware reset or change CE pin from "H" or "L"

Standby Mode

There are two ways to implement the standby mode on the MBM29LV004TC/BC devices, one using both the
CE and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V

± 0.3 V.

Under this condition the current consumed is less than 5

A. The device can be read with standard access time

) from either of these standby modes. During Embedded Algorithm operation, V

active current (I

CC2

) is

required even CE = "H".

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V

± 0.3 V (CE

= "H" or "L"). Under this condition the current is consumed is less than 5

A. Once the RESET pin is taken high,

the device requires t

of wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV004TC/BC data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.

To activate this mode, MBM29LV004TC/BC automatically switch themselves to low power mode when
MBM29LV004TC/BC addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1

A (CMOS Level).

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29LV004TC/BC read-out the data for changed addresses.

Output Disable

With the OE input at a logic high level (V

), output from the devices are disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.

To activate this mode, the programming equipment must force V

(11.5 V to 12.5 V) on address pin A

. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A

from V

to V

. All

addresses are DON'T CARES except A

, A

, and A

. (See Table 3.1.)

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The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV004TC/BC are erased or programmed in a system without access to high voltage on the A

pin. The

command sequence is illustrated in Table 6. (Refer to Autoselect Command section.)

Byte 0 (A

= V

) represents the manufacturer's code (Fujitsu = 04H) and (A

= V

) represents the device identifier

code (MBM29LV004TC = B5H and MBM29LV004BC = B6H). These two bytes/words are given in the tables 3.1
and 3.2. All identifiers for manufactures and device will exhibit odd parity with DQ

defined as the parity bit. In

order to read the proper device codes when executing the autoselect, A

must be V

. (See Tables 3.1 and 3.2.)

* : Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

Table 3 .1 MBM29LV004TC/004BC Sector Protection Verify Autoselect Codes

Type

to A

Code (HEX)

Manufacture's Code

04H

Device Code

MBM29LV004TC

B5H

MBM29LV004BC

B6H

Sector Protection

Sector

Addresses

01H*

Table 3 .2 Expanded Autoselect Code Table

Type

Code

Manufacture's Code

04H

Device Code

MBM29LV004TC

B5H

MBM29LV004BC

B6H

Sector Protection

01H

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Table 4 Sector Address Tables (MBM29LV004TC)

Sector

Address

Address Range

SA0

00000H to 0FFFFH

SA1

10000H to 1FFFFH

SA2

20000H to 2FFFFH

SA3

30000H to 3FFFFH

SA4

40000H to 4FFFFH

SA5

50000H to 5FFFFH

SA6

60000H to 6FFFFH

SA7

70000H to 77FFFH

SA8

78000H to 79FFFH

SA9

7A000H to 7BFFFH

SA10

7C000H to 7FFFFH

Table 5 Sector Address Tables (MBM29LV004BC)

Sector

Address

Address Range

SA0

00000H to 03FFFH

SA1

04000H to 05FFFH

SA2

06000H to 07FFFH

SA3

08000H to 0FFFFH

SA4

10000H to 1FFFFH

SA5

20000H to 2FFFFH

SA6

30000H to 3FFFFH

SA7

40000H to 4FFFFH

SA8

50000H to 5FFFFH

SA9

60000H to 6FFFFH

SA10

70000H to 7FFFFH

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Write

Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V

, while CE is at V

and OE is at V

. Addresses are latched on

the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Protection

The MBM29LV004TC/BC feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 10). The sector protection feature is enabled using programming
equipment at the user's site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.

To activate this mode, the programming equipment must force V

on address pin A

and control pin OE, (suggest

= 11.5 V), CE = V

, and A

= V

. The sector addresses (A

, A

, and A

) should be set to the

sector to be protected. Tables 4 and 5 define the sector address for each of the eleven (11) individual sectors.
Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
rising edge of the same. Sector addresses must be held constant during the WE pulse. See Figures 13 and 21
for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V

on address pin A

with CE and OE at V

and WE at V

. Scanning the sector addresses (A

, A

, and A

) while (A

, A

) = (0, 0, 1, 0) will produce a logical "1" code at device output DQ

for a protected sector. Otherwise

the devices will read 00H for unprotected sector. In this mode, the lower order addresses, except for A

, A

and A

are DON'T CARES. Address locations with A

= V

are reserved for Autoselect manufacturer and device

codes.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A

, A

, and

) are the desired sector address will produce a logical "1" at DQ

for a protected sector. See Tables 3.1 and

3.2 for Autoselect codes.

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29LV004TC/BC devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. See Figures 14 and 22.

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Notes: 1. Address bits A

to A

= X = "H" or "L" for all address commands except or Program Address (PA) and

Sector Address (SA)

2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A

, A

, and A

will

uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

Table 6 MBM29LV004TC/004BC Standard Command Definitions

Command

Sequence

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset

XXXH F0H

Read/Reset

555H

AAH

2AAH

55H

555H

F0H

Autoselect

555H

AAH

2AAH

55H

555H

90H

Program

555H

AAH

2AAH

55H

555H

A0H

Chip Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

10H

Sector Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

30H

Sector Erase Suspend

Erase can be suspended during sector erase with Addr. ("H" or "L"). Data (B0H)

Sector Erase Resume

Erase can be resumed after suspend with Addr. ("H" or "L"). Data (30H)

MBM29LV004TC

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SPA: Sector address to be protected. Set sector address (SA) and (A

, A

) = (0, 0, 1, 0).

SD: Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected

sector addresses.

*1 : This command is valid while Fast Mode.
*2 : This command is valid while RESET

*3 : The data "00H" is also acceptable.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ

= 1) to read/reset mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.

The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.

Table 7 MBM29LV004TC/BC Extended Command Definitions

Command

Sequence

Bus Write

Cycles

Req'd

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Set to
Fast Mode

555H

AAH

2AAH

55H

555H

20H

Fast Program*

(Note)

XXXH

A0H

Reset from Fast
Mode*

XXXH

90H

XXXH

F0H*

Extended Sector
Protect*

XXXH

60H

SPA

60H

SPA

40H

SPA

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Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A

to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H returns the device code (MBM29LV004TC = B5H and MBM29LV004BC = B6H). (See
Tables 3.1 and 3.2.) All manufacturer and device codes will exhibit odd parity with DQ

defined as the parity bit.

Sector state (protection or unprotection) will be informed by address XX02H.
Scanning the sector addresses (A

, A

, and A

) while (A

, A

) = (0, 0, 1, 0) will produce

a logical "1" at device output DQ

for a protected sector. The programming verification should be perform margin

mode on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.

Byte Programming

The devices are programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are
two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required
to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ

is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still "0". Only
erase operations can convert "0"s to "1"s.

Figure 17 illustrates the Embedded Program

Algorithm using typical command strings and bus operations.

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Chip Erase

Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.

The automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates
when the data on DQ

is "1" (See Write Operation Status section.) at which time the device returns to read the

mode.

Chip Erase Time; Sector Erase Time

All sectors + Chip Program Time (Preprogramming)

Figure 18 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of write pulse, while the
command (Data=30H) is latched on the rising edge of write pulse. After time-out of 50

s from the rising edge

of the last sector erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50

from the rising edge of the last write pulse will initiate the execution of the Sector Erase command(s). If another
falling edge of the write pulse occurs within the 50

s time-out window the timer is reset. (Monitor DQ

to determine

if the sector erase timer window is still open, see section DQ

, Sector Erase Timer.) Any command other than

Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the
previous command string. Resetting the devices once execution has begun will corrupt the data in the sector.
In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status
section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and
with any number of sectors (0 to 10).

Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.

The automatic sector erase begins after the 50

s time out from the rising edge of the write pulse pulse for the

last sector erase command pulse and terminates when the data on DQ

is "1" (See Write Operation Status

section.) at which time the devices return to the read mode. Data polling must be performed at an address within
any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time
(Preprogramming)]

Number of Sector Erase

Figure 18 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

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Erase Suspend

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are DON'T CARES when
writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20

s to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/

BY output pin and the DQ

bit will be at logic "1", and DQ

will stop toggling. The user must use the address of

the erasing sector for reading DQ

and DQ

to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ

to toggle. (See the section on DQ

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ

to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ

, or by the Toggle Bit I

(DQ

) which is the same as the regular Program operation. Note that DQ

must be read from the Program address

while DQ

can be read from any address.

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

Extended Command

(1) Fast Mode

MBM29LV004TC/BC has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also executed
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. (Refer to the Figure 24 Extended algorithm.) The V

active current is required even CE = V

during

Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 24 Extended algorithm.)

(3) Extended Sector Protection

In addition to normal sector protection, the MBM29LV004TC/BC has Extended Sector Protection as extended
function. This function enable to protect sector by forcing V

on RESET pin and write a commnad sequence.

Unlike conventional procedure, it is not necessary to force V

and control timing for control pins. The only

RESET pin requires V

for sector protection in this mode. The extended sector protect requires V

on RESET

pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command
register. Then, the sector addresses pins (A

, A

, and A

) and (A

, A

) = (0, 0, 1, 0)

should be set to the sector to be protected (recommend to set V

for the other addresses pins), and write

extended sector protect command (60H). A sector is typically protected in 150

s. To verify programming of

the protection circuitry, the sector addresses pins (A

, A

, and A

) and (A

, A

) = (0,

0, 1, 0) should be set and write a command (40H). Following the command write, a logical "1" at device
output DQ

will produce for protected sector in the read operation. If the output data is logical "0", please

repeat to write extended sector protect command (60H) again. To terminate the operation, it is necessary
to set RESET pin to V

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

Write Operation Status

Notes: 1. Performing successive read operations from any address will cause DQ

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic "1" at the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ

toggle.

3. DQ

and DQ

are reserve pins for future use.

4. DQ

is Fujitsu internal use only.

Table 8 Hardware Sequence Flags

Status

In Progress

Embedded Program Algorithm

Toggle

Embedded Erase Algorithm

Toggle

Erase
Suspended
Mode

Erase Suspend Read
(Erase Suspended Sector)

Toggle

Erase Suspend Read
(Non-Erase Suspended Sector)

Data

Data Data

Data

Erase Suspend Program
(Non-Erase Suspended Sector)

Toggle

(Note 1)

(Note 2)

Exceeded
Time Limits

Embedded Program Algorithm

Toggle

Embedded Erase Algorithm

Toggle

N/A

Erase
Suspended
Mode

Erase Suspend Program
(Non-Erase Suspended Sector)

Toggle

N/A

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

Data Polling

The MBM29LV004TC/BC devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ

. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ

. During the Embedded

Erase Algorithm, an attempt to read the device will produce a "0" at the DQ

output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ

output. The flowchart

for Data Polling (DQ

) is shown in Figure 19.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV004TC/BC data pins (DQ

) may change asynchronously while the output

enable (OE) is asserted low. This means that the devices are driving status information on DQ

at one instant

of time and then that byte's valid data at the next instant of time. Depending on when the system samples the
DQ

output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm

operation and DQ

has a valid data, the data outputs on DQ

to DQ

may be still invalid. The valid data on DQ

to DQ

will be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 8.)

See Figure 9 for the Data Polling timing specifications and diagrams.

Toggle Bit I

The MBM29LV004TC/BC also feature the "Toggle Bit I" as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ

toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ

will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2

s and then stop

toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ

to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ

to toggle.

See Figure 10 for the Toggle Bit I timing specifications and diagrams.

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

Exceeded Timing Limits

will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ

will produce a "1". This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling DQ

, DQ

is the only operating function of the devices under

this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.

The DQ

failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ

bit and DQ

never stops toggling. Once the devices have exceeded timing limits, the

bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly

used. If this occurs, reset the device with command sequence.

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ

will

remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ

may

be used to determine if the sector erase timer window is still open. If DQ

is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ

is low ("0"), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ

prior to and following each subsequent Sector Erase command. If DQ

were high on

the second status check, the command may not have been accepted.

Refer to Table 8: Hardware Sequence Flags.

Toggle Bit II

This Toggle bit II, along with DQ

, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ

to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ

to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic "1" at the DQ

bit.

is different from DQ

in that DQ

toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ

, is summarized

as follows:

For example, DQ

and DQ

can be used together to determine if the erase-suspend-read mode is in progress.

(DQ

toggles while DQ

does not.) See also Table 8 and Figure 15.

Furthermore, DQ

can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ

toggles if this bit is read from an erasing sector.

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

Notes: 1. Performing successive read operations from any address will cause DQ

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic "1" at the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ

toggle.

RY/BY

Ready/Busy

The MBM29LV004TC/BC provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands with the exception of the Erase Suspend command. If the MBM29LV004TC/BC are placed in an
Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to V

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V

RESET

Hardware Reset

The MBM29LV004TC/BC devices may be reset by driving the RESET pin to V

. The RESET pin has a pulse

requirement and has to be kept low (V

) for at least 500 ns in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20

s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

devices require an additional t

before it will allow read access. When the RESET pin is low, the devices will

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.

If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.

Mode

Program

Toggle

Erase

Toggle

Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)

Toggle

Erase-Suspend Program

Toggle (Note 1)

1 (Note 2)

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

Data Protection

The MBM29LV004TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form V

power-up

and power-down transitions or system noise.

Low V

Write Inhibit

To avoid initiation of a write cycle during V

power-up and power-down, a write cycle is locked out for V

less

than 2.3 V (typically 2.4 V). If V

< V

LKO

, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V

level is greater than V

LKO

. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when V

is above 2.3 V.

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = V

, CE = V

, or WE = V

. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the devices with WE = CE = V

and OE = V

will not accept commands on the rising edge of write

pulse. The internal state machine is automatically reset to the read mode on power-up.

Handling of SON Package

The metal portion of marking side is connected with internal chip electrically. Please pay attention not to occur
electrical connection during operation. In worst case, it may be caused permanent damage to device or system
by excessive current.

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

ABSOLUTE MAXIMUM RATINGS

Storage Temperature .................................................................................................. 55°C to +125°C
Ambient Temperature with Power Applied .................................................................. 40°C to +85°C
Voltage with respect to Ground All pins except A

, OE and RESET (Note 1) ............. 0.5 V to V

+0.5 V

(Note 1) ................................................................................................................ 0.5 V to +5.5 V

, OE, and RESET (Note 2) ...................................................................................... 0.5 V to +13.0 V

Notes: 1. Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, inputs may negative

overshoot V

to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V

+0.5 V. During voltage transitions, outputs may positive overshoot to V

+2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A

, OE and RESET pins are 0.5 V. During voltage transitions, A9, OE

and RESET pins may negative overshoot V

to 2.0 V for periods of up to 20 ns. Maximum DC input

voltage on A

, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of

up to 20 ns. Voltage difference between input voltage and supply voltage (V

) do not exceed 9 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING RANGES

Ambient Temperature (T

) ................................................................. 40°C to +85°C

Supply Voltages

MBM29LV004TC/BC-70................................................................. +3.0V to +3.6 V
MBM29LV004TC/BC-90/-12........................................................... +2.7 V to +3.6 V

Operating ranges define those limits between which the functionality of the devices are guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

DC CHARACTERISTICS

Notes: 1. The I

current listed includes both the DC operating current and the frequency dependent component.

2. I

active while Embedded Algorithm (program or erase) is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. (V

) do not exceed 9 V.

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Max.

Unit

Input Leakage Current

= V

to V

, V

= V

Max.

1.0

+1.0

Output Leakage Current

OUT

= V

to V

, V

= V

Max.

1.0

+1.0

LIT

, OE, RESET Inputs Leakage

Current

= V

Max.

, OE, RESET = 12.5 V

CC1

Active Current (Note 1)

CE = V

, OE = V

, f=10 MHz

CE = V

, OE = V

, f=5 MHz

CC2

Active Current (Note 2)

CE = V

, OE = V

CC3

Current (Standby)

= V

Max., CE = V

± 0.3 V,

RESET = V

± 0.3 V

CC4

Current (Standby, Reset)

= V

Max.,

RESET = V

± 0.3 V

CC5

Current

(Automatic Sleep Mode) (Note 3)

= V

Max., CE = V

± 0.3 V,

RESET = V

± 0.3 V

= V

± 0.3 V or V

0.3 V

µA

Input Low Level

0.5

0.6

Input High Level

2.0

+ 0.3

Voltage for Autoselect, Sector
Protection, and Temporary
Sector Unprotection
(A

, OE, RESET)

(Note 4)

11.5

12.5

Output Low Voltage Level

= 4.0 mA, V

= V

Min.

0.45

OH1

Output High Voltage Level

= 2.0 mA, V

= V

Min.

2.4

OH2

= 100

0.4

LKO

Low V

Lock-Out Voltage

2.3

2.5

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

AC CHARACTERISTICS

· Read Only Operations Characteristics

Note: Test Conditions:

Output Load: 1 TTL gate and 30 pF (MBM29LV004TC/BC-70)

1 TTL gate and 100 pF (MBM29LV004TC/BC-90/-12)

Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level

Input: 1.5 V
Output:1.5 V

Parameter

Symbols

Description

Test Setup

-70

(Note)

-90

(Note)

-12

(Note)

Unit

JEDEC

Standard

AVAV

Read Cycle Time

Min.

120

AVQV

ACC

Address to Output Delay

CE = V

OE = V

Max.

120

ELQV

Chip Enable to Output Delay

OE = V

Max.

120

GLQV

Output Enable to Output Delay

Max.

EHQZ

Chip Enable to Output High-Z

Max.

GHQZ

Output Enable to Output High-Z

Max.

AXQX

Output Hold Time From
Addresses,
CE or OE, Whichever Occurs First

Min.

READY

RESET Pin Low to Read Mode

Max.

3.3 V

Diodes = IN3064
or Equivalent

2.7 k

Device

Under

Test

IN3064
or Equivalent

6.2 k

Notes: C

= 30 pF including jig capacitance (MBM29LV004TC/BC-70)

= 100 pF including jig capacitance (MBM29LV004TC/BC-90/-12)

Figure 4 Test Conditions

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

· Write/Erase/Program Operations

(Continued)

Parameter Symbols

Description

MBM29LV004TC/BC

Unit

JEDEC

Standard

-70

-90

-12

AVAV

Write Cycle Time

Min.

120

AVWL

Address Setup Time

Min.

WLAX

Address Hold Time

Min.

DVWH

Data Setup Time

Min.

WHDX

Data Hold Time

Min.

OES

Output Enable Setup Time

Min.

OEH

Output
Enable Hold
Time

Read

Min.

Toggle and Data Polling

Min.

GHWL

Read Recover Time Before Write

Min.

GHEL

Read Recover Time Before Write

Min.

ELWL

CE Setup Time

Min.

WLEL

WE Setup Time

Min.

WHEH

CE Hold Time

Min.

EHWH

WE Hold Time

Min.

WLWH

Write Pulse Width

Min.

ELEH

CE Pulse Width

Min.

WHWL

WPH

Write Pulse Width High

Min.

EHEL

CPH

CE Pulse Width High

Min.

WHWH1

Byte Programming Operation

Typ.

µs

WHWH2

Sector Erase Operation (Note 1)

Typ.

sec

VCS

Setup Time

Min.

µs

VIDR

Rise Time to V

(Note 2)

Min.

500

VLHT

Voltage Transition Time (Note 2)

Min.

µs

WPP

Write Pulse Width (Note 2)

Min.

100

µs

OESP

OE Setup Time to WE Active (Note 2)

Min.

µs

CSP

CE Setup Time to WE Active (Note 2)

Min.

µs

Recover Time From RY/BY

Min.

RESET Pulse Width

Min.

500

RESET Hold Time Before Read

Min.

200

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

Figure 23 Extended Sector Protection Algorithm

To Sector Protection

Yes

PLSCNT = 1

Yes

Protection Other Sector

Start

Sector Protection

Extended Sector

PLSCNT = 25?

Device Failed

Remove V

from RESET

Completed

Remove

from RESET

Write Reset Command

RESET = V

Wait to 4

Protection Entry?

To Setup Sector Protection

Write XXXH/60H

Write SPA/60H

= V

, A

= V

, A

= V

)

Time Out 150

To Verify Sector Protection

Write SPA/40H

= V

, A

= V

, A

= V

)

Data = 01H?

Device is Operating in

Temporary Sector

Read from Sector Address
(A

= V

, A

= V

, A

= V

)

Increment PLSCNT

Setup Next Sector Address

Yes

Unprotection Mode

FAST MODE ALGORITHM

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

ERASE AND PROGRAMMING PERFORMANCE

TSOP(I) PIN CAPACITANCE

Note: Test conditions T

= 25°C, f = 1.0 MHz

SON PIN CAPACITANCE

Note: Test conditions T

= 25°C, f = 1.0 MHz

Parameter

Limits

Unit

Comments

Min.

Typ.

Max.

Sector Erase Time

sec

Excludes programming time
prior to erasure

Byte Programming Time

300

Excludes system-level
overhead

Chip Programming Time

8.4

12.5

sec

Excludes system-level
overhead

Erase/Program Cycle

100,000

cycles

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Control Pin Capacitance

= 0

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Control Pin Capacitance

= 0

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

PACKAGE DIMENSIONS

(Continued)

1994 FUJITSU LIMITED F40007S-1C-1

INDEX

"A"

LEAD No.

20.00±0.20

(.787±.008)

18.40±0.20

(.724±.008)

19.00±0.20

(.748±.008)

0.10(.004)

0.50±0.10

(.020±.004)

0.15±0.05

(.006±.002)

0.20±0.10

(.008±.004)

9.50(.374)

REF.

0.10(.004)

0.50(.0197)

TYP

10.00±0.20

(.394±.008)

0.05(.002)MIN
(STAND OFF)

.043

.002

+.004

0.05

+0.10

1.10

Details of "A" part

MAX

0.35(.014)

MAX

0.15(.006)

0.25(.010)

(Mounting height)

Dimensions in mm (inches)

40-pin plastic TSOP(I)

(FPT-40P-M06)

1994 FUJITSU LIMITED F40008S-1C-1

INDEX

"A"

LEAD No.

19.00±0.20

(.748±.008)

0.10(.004)

20.00±0.20

(.787±.008)

18.40±0.20

(.724±.008)

0.15±0.05

(.006±.002)

0.50±0.10

(.020±.004)

10.00±0.20

(.394±.008)

9.50(.374)

REF.

0.20±0.10

(.008±.004)

0.50(.0197)

TYP

0.10(.004)

0.05(.002)MIN
(STAND OFF)

.043

.002

+.004

0.05

+0.10

1.10

0.25(.010)

0.15(.006)

MAX

0.35(.014)

MAX

Details of "A" part

(Mounting height)

Dimensions in mm (inches)

40-pin plastic TSOP(I)

(FPT-40P-M07)

MBM29LV004TC

-70/-90/-12

/MBM29LV004BC

-70/-90/-12

FUJITSU LIMITED

For further information please contact:

Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608
Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220

http://www.fmap.com.sg/

F9903

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have an inhereut chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.

Part Number MBM29LV004BC

Document Outline