FUJITSU SEMICONDUCTOR

DATA SHEET

DS04224101E

1994 by FUJITSU LIMITED

ASSP

COMMUNICATION CONTROL SCSI-2
PROTOCOL CONTROLLER

MB86603

DESCRIPTION

The MB86603 is a SCSI-2 protocol controller (SPC) that facilitates interface control between the host computer (medium/small) and peripheral
devices. The specifications conform to the SCSI-2 standard but have an improved baud rate and extended functions.

The MB86603 supports high-speed synchronous transfer, wide transfer (16 bits), the MPU/DMA stand-alone system bus, and programmable
commands, to enable configuration of high-performance systems.

The MB86603 (SPC hereafter) is applicable to both single-end and differential transmissions and has a driver/receiver that can drive
single-end heavy current (48 mA).

It can also have the phase-to-phase sequence control function to reduce the program overhead of the host MPU. For the abbreviations in this data
sheet, see the next page.

FEATURES

SCSI Bus Interface

Operable as initiator and target

Two types of data transfer

Synchronous transfer: Max. 20 Mbytes/s, max. 32 offsets, 32-level baud rate
Asynchronous transfer: Max. 10 Mbytes/s

Transfer parameters (transfer mode, baud rate, transfer offset for 15 connected devices)

Single-end and differential transmissions

Driver/receiver capable of driving 48-mA single-end heavy current

Tristate bidirectional buffers for transfer control signals (REQ, ACK)

FPT-176P-M01

176-Lead Plastic SQFP Package

MB86603

Transfer Operation

Automatic response to selection/reselection

Prespecified receiving performed automatically at selection or reselection
Initiator: Automatically responds to reselection from target and operable until message received
Target: Automatically responds to selection from initiator and can operate until command received

Automatic receiving

Initiator: Can automatically receive information for new phase to which target shifted
Target: Can perform automatic receiving in response to attention condition generated by initiator

64-byte data register (FIFO) for data phase

Two (send-only and receive-only) 32-byte memory data buffers for message, command, and status phases

16-bit transfer block and 24-bit transfer byte registers enabling 1Tbyte transfer (1Tbyte: 16 Mbytes x 64 Kblocks)

Independent data transfer bus enabling microprocessor to operate during data transfer

Selection between parity through and generate

System Bus Interface

16-bit MPU/DMA stand-alone system bus

Direct connection with 68 series/80 series 16-bit MPUs

Two types of transfer

Program transfer
DMA transfer (burst mode)

Commands

Sequential command for sequential operation and programmable command for programming, including ordinary commands

Command queuing

Commands can be tagged in the command phase for continuous issuing.

512-byte memory as command program memory and command queue buffer

Others

CMOS

System clock frequency: 12 MHz to 32 MHz

+5 V single power supply

SCSI-2: Enhanced Small Computer System Interface
ANSI: American National Standard Institute
SPC: SCSI-2 Protocol Controller
MPU: Micro-Processing Unit
DMA: Direct Memory Access
FIFO: First-In First-Out
ID: Identifier (identification number assigned to each device connected to SCSI bus)
80 series: General term for MPU based on command system of 8080A developed by Intel
68 series: General term for MPU developed by Motorola

MB86603

PIN ASSIGNMENT

CS0

CS1

LDP

(NC)

D10

D11

D12

(NC)

D13

D14

D15

UDP

(NC)

BHE

INT

MODE

RESET

LDBOEP

DBOE7

(NC)

DBOE6

DBOE4

DB6

(NC)

DB2

(NC)

DB0

(NC)

DB15

DB13

DB12

DBOE1

DBOE5

(NC)

DB3

(NC)

DB14

DBOE3

DBOE0

(NC)

LDBP

DB7

DB5

DB4

(NC)

DB1

UDBP

(NC)

DBOE2

UDBOEP

BSYOE

(NC)

C/D

I/O

(NC)

DBOE8

(OPEN)

SELOE

(NC)

ACK

(NC)

MSG

(NC)

DB8

DB9

DB11

TEST2

INIT

(OPEN)

(NC)

DBOE9

DBOE10

DBOE11

DBOE12

DREQ

DACK

(NC)

DMBHE

CLK

UDMDP

DMD15

DMD14

DMD13

DMD12

DMD11

DMD10

DMD9

DMD8

DMD7

DMD6

DMD5

DMD4

DMD3

DMD2

DMD1

DMD0

LDMDP

DMA0

(NC)

IOWR

IORD

S/DSEL

DBOE13

DBOE14

DBOE15

135

140

145

150

155

160

165

170

175

130

125

120

115

110

105

100

(TOP VIEW)

INDEX

(FPT-176P-M01)

RSTOE

ATN

BSY

RET

(NC)

SEL

(NC)

REQ

(NC)

DB10

TARG

MB86603

BLOCK DIAGRAM

DREQ

DACK

DMBHE

DMA0

DMD15 to
DMD8, UDMDP

DMD7 to
DMD0, LDMDP

IOWR

IORD

T.P.

MSG

C/D

I/O

ATN

BSYOE

BSY

SELOE

SEL

RSTOE

RST

REQ

ACK

INIT

TARG

SCSI Interface

Internal
processor

Phase
controller

Transfer
controller

Timer

Various
registers

(32 bytes)
Receive
MSG, CMD,
Status
buffer

(32 bytes)
Send MSG,
CMD, Sta-
tus buffer

(512 bytes)

User
program
memory

MPU interface

Data regis-
ter
(64 bytes)

DB15 to DB8, UDBP

DB7 to DB0, LDBP

DBOE15 to DBOE8,

UDBOEP

DBOE7 to DBOE0,

LDBOEP

S/DSEL

DMA Interface

INT

CS0

CS1

A4 to A0

BHE

MODE

D15 to
D8,
UDP

D7 to
D0,
LDP

MB86603

BLOCK DESCRIPTION

1. Internal processor (sequensor)

This processor provides sequence control between each phase.

Information-transfer phase

Bus-free phase

Arbitration phase

Selection phase

Information-transfer phase

Command phase

Data phase

Status phase

Message phase

2. Timer

This timer manages timing specified by the SCSI and the following timing.

REQ/ACK assertion time for data at asynchronous transfer

Selection/reselection retry time

Selection/reselection timeout time

REQ/ACK timeout time during transfer

Asynchronous transfer (target): Time required for initiator to assert ACK signal after asserting REQ signal
Asynchronous transfer (initiator): Time required for target to negate REQ signal after asserting ACK signal
Synchronous transfer (target only): Time required for target to send REQ signal and then receive ACK signal for setting offset to 0 from

initiator

3. Phase Controller

This controller controls the arbitration, selection/reselection, data in/out, command, status, and message in/out phases executed on the SCSI bus.

4. Transfer Controller

This controller controls the information (data, command, status, message) transfer phase executed on the SCSI bus.

There are two transfer types for executing the information transfer phase.

Asynchronous transfer: Control by interlocking REQ and ACK signals

Synchronous transfer: Control with maximum of 32-byte offset value in data in/out phase

There are two types of modes depending on the data movement as follows:

Program transfer: Performed via MPU interface using data registers

DMA transfer: Performed via DMA interface using DREQ and DACK pins

At synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of REQ or ACK signal sent from SPC in synchronous
transfer, and maximum REQ/ACK offset value in synchronous transfer) can be saved for each ID and automatically set when the data phase is
started. The transfer byte count is determined by block length x number of blocks.

Part Number MB86603